include/bsp/i2c.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup lpc32xx_i2c
0007  *
0008  * @brief I2C support API.
0009  */
0010
0011 /*
0012  * Copyright (c) 2010 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_ARM_LPC32XX_I2C_H
0037 #define LIBBSP_ARM_LPC32XX_I2C_H
0038
0039 #include <rtems.h>
0040
0041 #include <bsp/lpc32xx.h>
0042
0043 #ifdef __cplusplus
0044 extern "C" {
0045 #endif /* __cplusplus */
0046
0047 /**
0048  * @defgroup lpc32xx_i2c I2C Support
0049  *
0050  * @ingroup RTEMSBSPsARMLPC32XX
0051  *
0052  * @brief I2C Support
0053  *
0054  * All writes and reads will be performed in master mode.  Exclusive bus access
0055  * will be assumed.
0056  *
0057  * @{
0058  */
0059
0060 /**
0061  * @name I2C Clock Control Register (I2CCLK_CTRL)
0062  *
0063  * @{
0064  */
0065
0066 #define I2CCLK_1_EN BSP_BIT32(0)
0067 #define I2CCLK_2_EN BSP_BIT32(1)
0068 #define I2CCLK_1_HIGH_DRIVE BSP_BIT32(2)
0069 #define I2CCLK_2_HIGH_DRIVE BSP_BIT32(3)
0070 #define I2CCLK_USB_HIGH_DRIVE BSP_BIT32(4)
0071
0072 /** @} */
0073
0074 /**
0075  * @name I2C TX Data FIFO Register (I2Cn_TX)
0076  *
0077  * @{
0078  */
0079
0080 #define I2C_TX_READ BSP_BIT32(0)
0081 #define I2C_TX_ADDR(val) BSP_FLD32(val, 1, 7)
0082 #define I2C_TX_START BSP_BIT32(8)
0083 #define I2C_TX_STOP BSP_BIT32(9)
0084
0085 /** @} */
0086
0087 /**
0088  * @name I2C Status Register (I2Cn_STAT)
0089  *
0090  * @{
0091  */
0092
0093 #define I2C_STAT_TDI BSP_BIT32(0)
0094 #define I2C_STAT_AFI BSP_BIT32(1)
0095 #define I2C_STAT_NAI BSP_BIT32(2)
0096 #define I2C_STAT_DRMI BSP_BIT32(3)
0097 #define I2C_STAT_DRSI BSP_BIT32(4)
0098 #define I2C_STAT_ACTIVE BSP_BIT32(5)
0099 #define I2C_STAT_SCL BSP_BIT32(6)
0100 #define I2C_STAT_SDA BSP_BIT32(7)
0101 #define I2C_STAT_RFF BSP_BIT32(8)
0102 #define I2C_STAT_RFE BSP_BIT32(9)
0103 #define I2C_STAT_TFF BSP_BIT32(10)
0104 #define I2C_STAT_TFE BSP_BIT32(11)
0105 #define I2C_STAT_TFFS BSP_BIT32(12)
0106 #define I2C_STAT_TFES BSP_BIT32(13)
0107
0108 /** @} */
0109
0110 /**
0111  * @name I2C Control Register (I2Cn_CTRL)
0112  *
0113  * @{
0114  */
0115
0116 #define I2C_CTRL_TDIE BSP_BIT32(0)
0117 #define I2C_CTRL_AFIE BSP_BIT32(1)
0118 #define I2C_CTRL_NAIE BSP_BIT32(2)
0119 #define I2C_CTRL_DRMIE BSP_BIT32(3)
0120 #define I2C_CTRL_DRSIE BSP_BIT32(4)
0121 #define I2C_CTRL_RFFIE BSP_BIT32(5)
0122 #define I2C_CTRL_RFDAIE BSP_BIT32(6)
0123 #define I2C_CTRL_TFFIO BSP_BIT32(7)
0124 #define I2C_CTRL_RESET BSP_BIT32(8)
0125 #define I2C_CTRL_SEVEN BSP_BIT32(9)
0126 #define I2C_CTRL_TFFSIE BSP_BIT32(10)
0127
0128 /** @} */
0129
0130 /**
0131  * @brief Initializes the I2C module @a i2c.
0132  *
0133  * Valid @a clock_in_hz values are 100000 and 400000.
0134  *
0135  * @retval RTEMS_SUCCESSFUL Successful operation.
0136  * @retval RTEMS_INVALID_ID Invalid @a i2c value.
0137  * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value.
0138  */
0139 rtems_status_code lpc32xx_i2c_init(
0140   volatile lpc32xx_i2c *i2c,
0141   unsigned clock_in_hz
0142 );
0143
0144 /**
0145  * @brief Resets the I2C module @a i2c.
0146  */
0147 void lpc32xx_i2c_reset(volatile lpc32xx_i2c *i2c);
0148
0149 /**
0150  * @brief Sets the I2C module @a i2c clock.
0151  *
0152  * Valid @a clock_in_hz values are 100000 and 400000.
0153  *
0154  * @retval RTEMS_SUCCESSFUL Successful operation.
0155  * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value.
0156  */
0157 rtems_status_code lpc32xx_i2c_clock(
0158   volatile lpc32xx_i2c *i2c,
0159   unsigned clock_in_hz
0160 );
0161
0162 /**
0163  * @brief Starts a write transaction on the I2C module @a i2c.
0164  *
0165  * The address parameter @a addr must not contain the read/write bit.
0166  *
0167  * The error status may be delayed to the next
0168  * lpc32xx_i2c_write_with_optional_stop() due to controller flaws.
0169  *
0170  * @retval RTEMS_SUCCESSFUL Successful operation.
0171  * @retval RTEMS_IO_ERROR Received a NACK from the slave.
0172  */
0173 rtems_status_code lpc32xx_i2c_write_start(
0174   volatile lpc32xx_i2c *i2c,
0175   unsigned addr
0176 );
0177
0178 /**
0179  * @brief Writes data via the I2C module @a i2c with optional stop.
0180  *
0181  * The error status may be delayed to the next
0182  * lpc32xx_i2c_write_with_optional_stop() due to controller flaws.
0183  *
0184  * @retval RTEMS_SUCCESSFUL Successful operation.
0185  * @retval RTEMS_IO_ERROR Received a NACK from the slave.
0186  */
0187 rtems_status_code lpc32xx_i2c_write_with_optional_stop(
0188   volatile lpc32xx_i2c *i2c,
0189   const uint8_t *out,
0190   size_t n,
0191   bool stop
0192 );
0193
0194 /**
0195  * @brief Starts a read transaction on the I2C module @a i2c.
0196  *
0197  * The address parameter @a addr must not contain the read/write bit.
0198  *
0199  * The error status may be delayed to the next
0200  * lpc32xx_i2c_read_with_optional_stop() due to controller flaws.
0201  *
0202  * @retval RTEMS_SUCCESSFUL Successful operation.
0203  * @retval RTEMS_IO_ERROR Received a NACK from the slave.
0204  */
0205 rtems_status_code lpc32xx_i2c_read_start(
0206   volatile lpc32xx_i2c *i2c,
0207   unsigned addr
0208 );
0209
0210 /**
0211  * @brief Reads data via the I2C module @a i2c with optional stop.
0212  *
0213  * @retval RTEMS_SUCCESSFUL Successful operation.
0214  * @retval RTEMS_IO_ERROR Received a NACK from the slave.
0215  * @retval RTEMS_NOT_IMPLEMENTED Stop is @a false.
0216  */
0217 rtems_status_code lpc32xx_i2c_read_with_optional_stop(
0218   volatile lpc32xx_i2c *i2c,
0219   uint8_t *in,
0220   size_t n,
0221   bool stop
0222 );
0223
0224 /**
0225  * @brief Writes and reads data via the I2C module @a i2c.
0226  *
0227  * This will be one bus transaction.
0228  *
0229  * @retval RTEMS_SUCCESSFUL Successful operation.
0230  * @retval RTEMS_IO_ERROR Received a NACK from the slave.
0231  */
0232 rtems_status_code lpc32xx_i2c_write_and_read(
0233   volatile lpc32xx_i2c *i2c,
0234   unsigned addr,
0235   const uint8_t *out,
0236   size_t out_size,
0237   uint8_t *in,
0238   size_t in_size
0239 );
0240
0241 /**
0242  * @brief Writes data via the I2C module @a i2c.
0243  *
0244  * This will be one bus transaction.
0245  *
0246  * @retval RTEMS_SUCCESSFUL Successful operation.
0247  * @retval RTEMS_IO_ERROR Received a NACK from the slave.
0248  */
0249 static inline rtems_status_code lpc32xx_i2c_write(
0250   volatile lpc32xx_i2c *i2c,
0251   unsigned addr,
0252   const uint8_t *out,
0253   size_t out_size
0254 )
0255 {
0256   return lpc32xx_i2c_write_and_read(i2c, addr, out, out_size, NULL, 0);
0257 }
0258
0259 /**
0260  * @brief Reads data via the I2C module @a i2c.
0261  *
0262  * This will be one bus transaction.
0263  *
0264  * @retval RTEMS_SUCCESSFUL Successful operation.
0265  * @retval RTEMS_IO_ERROR Received a NACK from the slave.
0266  */
0267 static inline rtems_status_code lpc32xx_i2c_read(
0268   volatile lpc32xx_i2c *i2c,
0269   unsigned addr,
0270   uint8_t *in,
0271   size_t in_size
0272 )
0273 {
0274   return lpc32xx_i2c_write_and_read(i2c, addr, NULL, 0, in, in_size);
0275 }
0276
0277 /** @} */
0278
0279 #ifdef __cplusplus
0280 }
0281 #endif /* __cplusplus */
0282
0283 #endif /* LIBBSP_ARM_LPC32XX_I2C_H */