include/bsp/emc.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup lpc32xx_emc
0007  *
0008  * @brief EMC support API.
0009  */
0010
0011 /*
0012  * Copyright (C) 2010, 2011 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_ARM_LPC32XX_EMC_H
0037 #define LIBBSP_ARM_LPC32XX_EMC_H
0038
0039 #include <rtems.h>
0040
0041 #include <bsp/lpc-emc.h>
0042
0043 #ifdef __cplusplus
0044 extern "C" {
0045 #endif /* __cplusplus */
0046
0047 /**
0048  * @addtogroup lpc_emc
0049  *
0050  * @brief EMC Support
0051  *
0052  * @{
0053  */
0054
0055 /**
0056  * @name SDRAM Clock Control Register (SDRAMCLK_CTRL)
0057  *
0058  * @{
0059  */
0060
0061 #define SDRAMCLK_CLOCKS_DIS BSP_BIT32(0)
0062 #define SDRAMCLK_DDR_MODE BSP_BIT32(1)
0063 #define SDRAMCLK_DDR_DQSIN_DELAY(val) BSP_FLD32(val, 2, 6)
0064 #define SDRAMCLK_RTC_TICK_EN BSP_BIT32(7)
0065 #define SDRAMCLK_SW_DDR_CAL BSP_BIT32(8)
0066 #define SDRAMCLK_CAL_DELAY BSP_BIT32(9)
0067 #define SDRAMCLK_SENSITIVITY_FACTOR(val) BSP_FLD32(val, 10, 12)
0068 #define SDRAMCLK_DCA_STATUS BSP_BIT32(13)
0069 #define SDRAMCLK_COMMAND_DELAY(val) BSP_FLD32(val, 14, 18)
0070 #define SDRAMCLK_SW_DDR_RESET BSP_BIT32(19)
0071 #define SDRAMCLK_PIN_1_FAST BSP_BIT32(20)
0072 #define SDRAMCLK_PIN_2_FAST BSP_BIT32(21)
0073 #define SDRAMCLK_PIN_3_FAST BSP_BIT32(22)
0074
0075 /** @} */
0076
0077 /**
0078  * @name EMC AHB Control Register (EMCAHBControl)
0079  *
0080  * @{
0081  */
0082
0083 #define EMC_AHB_PORT_BUFF_EN BSP_BIT32(0)
0084
0085 /** @} */
0086
0087 /**
0088  * @name EMC AHB Timeout Register (EMCAHBTimeOut)
0089  *
0090  * @{
0091  */
0092
0093 #define EMC_AHB_TIMEOUT(val) BSP_FLD32(val, 0, 9)
0094
0095 /** @} */
0096
0097 /**
0098  * @name SDRAM Mode and Extended Mode Registers
0099  *
0100  * @{
0101  */
0102
0103 #define SDRAM_ADDR_ROW_16MB(val) ((uint32_t) (val) << 10)
0104 #define SDRAM_ADDR_ROW_32MB(val) ((uint32_t) (val) << 11)
0105 #define SDRAM_ADDR_ROW_64MB(val) ((uint32_t) (val) << 11)
0106
0107 #define SDRAM_ADDR_BANK_16MB(ba1, ba0) \
0108   (((uint32_t) (ba1) << 23) | ((uint32_t) (ba0) << 22))
0109 #define SDRAM_ADDR_BANK_32MB(ba1, ba0) \
0110   (((uint32_t) (ba1) << 23) | ((uint32_t) (ba0) << 24))
0111 #define SDRAM_ADDR_BANK_64MB(ba1, ba0) \
0112   (((uint32_t) (ba1) << 25) | ((uint32_t) (ba0) << 24))
0113
0114 #define SDRAM_MODE_16MB(mode) \
0115   (SDRAM_ADDR_BANK_16MB(0, 0) | SDRAM_ADDR_ROW_16MB(mode))
0116 #define SDRAM_MODE_32MB(mode) \
0117   (SDRAM_ADDR_BANK_32MB(0, 0) | SDRAM_ADDR_ROW_32MB(mode))
0118 #define SDRAM_MODE_64MB(mode) \
0119   (SDRAM_ADDR_BANK_64MB(0, 0) | SDRAM_ADDR_ROW_64MB(mode))
0120
0121 #define SDRAM_EXTMODE_16MB(mode) \
0122   (SDRAM_ADDR_BANK_16MB(1, 0) | SDRAM_ADDR_ROW_16MB(mode))
0123 #define SDRAM_EXTMODE_32MB(mode) \
0124   (SDRAM_ADDR_BANK_32MB(1, 0) | SDRAM_ADDR_ROW_32MB(mode))
0125 #define SDRAM_EXTMODE_64MB(mode) \
0126   (SDRAM_ADDR_BANK_64MB(1, 0) | SDRAM_ADDR_ROW_64MB(mode))
0127
0128 #define SDRAM_MODE_BURST_LENGTH(val) BSP_FLD32(val, 0, 2)
0129 #define SDRAM_MODE_BURST_INTERLEAVE BSP_BIT32(3)
0130 #define SDRAM_MODE_CAS(val) BSP_FLD32(val, 4, 6)
0131 #define SDRAM_MODE_TEST_MODE(val) BSP_FLD32(val, 7, 8)
0132 #define SDRAM_MODE_WRITE_BURST_SINGLE_BIT BSP_BIT32(9)
0133
0134 #define SDRAM_EXTMODE_PASR(val) BSP_FLD32(val, 0, 2)
0135 #define SDRAM_EXTMODE_DRIVER_STRENGTH(val) BSP_FLD32(val, 5, 6)
0136
0137 /** @} */
0138
0139 typedef struct {
0140   uint32_t size;
0141   uint32_t config;
0142   uint32_t rascas;
0143   uint32_t mode;
0144   uint32_t extmode;
0145 } lpc32xx_emc_dynamic_chip_config;
0146
0147 typedef struct {
0148   uint32_t sdramclk_ctrl;
0149   uint32_t nop_time_in_us;
0150   uint32_t control;
0151   uint32_t refresh;
0152   uint32_t readconfig;
0153   uint32_t trp;
0154   uint32_t tras;
0155   uint32_t tsrex;
0156   uint32_t twr;
0157   uint32_t trc;
0158   uint32_t trfc;
0159   uint32_t txsr;
0160   uint32_t trrd;
0161   uint32_t tmrd;
0162   uint32_t tcdlr;
0163   lpc32xx_emc_dynamic_chip_config chip [EMC_DYN_CHIP_COUNT];
0164 } lpc32xx_emc_dynamic_config;
0165
0166 void lpc32xx_emc_init(const lpc32xx_emc_dynamic_config *dyn_cfg);
0167
0168 /** @} */
0169
0170 #ifdef __cplusplus
0171 }
0172 #endif /* __cplusplus */
0173
0174 #endif /* LIBBSP_ARM_LPC32XX_EMC_H */