lpc32xx/include/bsp.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMLPC32XX
0007  *
0008  * @brief Global BSP definitions.
0009  */
0010
0011 /*
0012  * Copyright (C) 2009, 2011 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_ARM_LPC32XX_BSP_H
0037 #define LIBBSP_ARM_LPC32XX_BSP_H
0038
0039 /**
0040  * @defgroup RTEMSBSPsARMLPC32XX NXP LPC32XX
0041  *
0042  * @ingroup RTEMSBSPsARM
0043  *
0044  * @brief NXP LPC32XX Board Support Package.
0045  *
0046  * @{
0047  */
0048
0049 #include <bspopts.h>
0050
0051 #define BSP_FEATURE_IRQ_EXTENSION
0052
0053 #ifndef ASM
0054
0055 #include <rtems.h>
0056
0057 #include <bsp/lpc32xx.h>
0058 #include <bsp/default-initial-extension.h>
0059
0060 #ifdef __cplusplus
0061 extern "C" {
0062 #endif /* __cplusplus */
0063
0064 struct rtems_bsdnet_ifconfig;
0065
0066 /**
0067  * @brief Network driver attach and detach function.
0068  */
0069 int lpc_eth_attach_detach(
0070   struct rtems_bsdnet_ifconfig *config,
0071   int attaching
0072 );
0073
0074 /**
0075  * @brief Standard network driver attach and detach function.
0076  */
0077 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach
0078
0079 /**
0080  * @brief Standard network driver name.
0081  */
0082 #define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
0083
0084 /**
0085  * @brief Optimized idle task.
0086  *
0087  * This idle task sets the power mode to idle.  This causes the processor clock
0088  * to be stopped, while on-chip peripherals remain active.  Any enabled
0089  * interrupt from a peripheral or an external interrupt source will cause the
0090  * processor to resume execution.
0091  *
0092  * To enable the idle task use the following in the system configuration:
0093  *
0094  * @code
0095  * #include <bsp.h>
0096  *
0097  * #define CONFIGURE_INIT
0098  *
0099  * #define CONFIGURE_IDLE_TASK_BODY lpc32xx_idle
0100  *
0101  * #include <confdefs.h>
0102  * @endcode
0103  */
0104 void *lpc32xx_idle(uintptr_t ignored);
0105
0106 #define LPC32XX_STANDARD_TIMER (&lpc32xx.timer_1)
0107
0108 static inline unsigned lpc32xx_timer(void)
0109 {
0110   volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER;
0111
0112   return timer->tc;
0113 }
0114
0115 static inline void lpc32xx_micro_seconds_delay(unsigned us)
0116 {
0117   unsigned start = lpc32xx_timer();
0118   unsigned delay = us * (LPC32XX_PERIPH_CLK / 1000000);
0119   unsigned elapsed = 0;
0120
0121   do {
0122     elapsed = lpc32xx_timer() - start;
0123   } while (elapsed < delay);
0124 }
0125
0126 #if LPC32XX_OSCILLATOR_MAIN == 13000000U
0127   #define LPC32XX_HCLKPLL_CTRL_INIT_VALUE \
0128     (HCLK_PLL_POWER | HCLK_PLL_DIRECT | HCLK_PLL_M(16 - 1))
0129   #define LPC32XX_HCLKDIV_CTRL_INIT_VALUE \
0130     (HCLK_DIV_HCLK(2 - 1) | HCLK_DIV_PERIPH_CLK(16 - 1) | HCLK_DIV_DDRAM_CLK(0))
0131 #else
0132   #error "unexpected main oscillator frequency"
0133 #endif
0134
0135 bool lpc32xx_start_pll_setup(
0136   uint32_t hclkpll_ctrl,
0137   uint32_t hclkdiv_ctrl,
0138   bool force
0139 );
0140
0141 uint32_t lpc32xx_sysclk(void);
0142
0143 uint32_t lpc32xx_hclkpll_clk(void);
0144
0145 uint32_t lpc32xx_periph_clk(void);
0146
0147 uint32_t lpc32xx_hclk(void);
0148
0149 uint32_t lpc32xx_arm_clk(void);
0150
0151 uint32_t lpc32xx_ddram_clk(void);
0152
0153 typedef enum {
0154   LPC32XX_NAND_CONTROLLER_NONE,
0155   LPC32XX_NAND_CONTROLLER_MLC,
0156   LPC32XX_NAND_CONTROLLER_SLC
0157 } lpc32xx_nand_controller;
0158
0159 void lpc32xx_select_nand_controller(lpc32xx_nand_controller nand_controller);
0160
0161 void bsp_restart(void *addr);
0162
0163 void *bsp_idle_thread(uintptr_t arg);
0164
0165 #define BSP_IDLE_TASK_BODY bsp_idle_thread
0166
0167 #define BSP_CONSOLE_UART_BASE LPC32XX_BASE_UART_5
0168
0169 /**
0170  * @brief Begin of magic zero area.
0171  *
0172  * A read from this area returns zero.  Writes have no effect.
0173  */
0174 extern uint32_t lpc32xx_magic_zero_begin [];
0175
0176 /**
0177  * @brief End of magic zero area.
0178  *
0179  * A read from this area returns zero.  Writes have no effect.
0180  */
0181 extern uint32_t lpc32xx_magic_zero_end [];
0182
0183 /**
0184  * @brief Size of magic zero area.
0185  *
0186  * A read from this area returns zero.  Writes have no effect.
0187  */
0188 extern uint32_t lpc32xx_magic_zero_size [];
0189
0190 #ifdef LPC32XX_SCRATCH_AREA_SIZE
0191   /**
0192    * @rief Scratch area.
0193    *
0194    * The usage is application specific.
0195    */
0196   extern uint8_t lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE]
0197     __attribute__((aligned(32)));
0198 #endif
0199
0200 #define LPC32XX_DO_STOP_GPDMA \
0201   do { \
0202     if ((LPC32XX_DMACLK_CTRL & 0x1) != 0) { \
0203       if ((lpc32xx.dma.cfg & DMA_CFG_E) != 0) { \
0204         int i = 0; \
0205         for (i = 0; i < 8; ++i) { \
0206           lpc32xx.dma.channels [i].cfg = 0; \
0207         } \
0208         lpc32xx.dma.cfg &= ~DMA_CFG_E; \
0209       } \
0210       LPC32XX_DMACLK_CTRL = 0; \
0211     } \
0212   } while (0)
0213
0214 #define LPC32XX_DO_STOP_ETHERNET \
0215   do { \
0216     if ((LPC32XX_MAC_CLK_CTRL & 0x7) == 0x7) { \
0217       lpc32xx.eth.command = 0x38; \
0218       lpc32xx.eth.mac1 = 0xcf00; \
0219       lpc32xx.eth.mac1 = 0; \
0220       LPC32XX_MAC_CLK_CTRL = 0; \
0221     } \
0222   } while (0)
0223
0224 #define LPC32XX_DO_STOP_USB \
0225   do { \
0226     if ((LPC32XX_USB_CTRL & 0x010e8000) != 0) { \
0227       LPC32XX_OTG_CLK_CTRL = 0; \
0228       LPC32XX_USB_CTRL = 0x80000; \
0229     } \
0230   } while (0)
0231
0232 #define LPC32XX_DO_RESTART(addr) \
0233   do { \
0234     ARM_SWITCH_REGISTERS; \
0235     rtems_interrupt_level level; \
0236     uint32_t ctrl = 0; \
0237   \
0238     rtems_interrupt_disable(level); \
0239     (void) level; /* avoid set but not used warning */ \
0240   \
0241     arm_cp15_data_cache_test_and_clean(); \
0242     arm_cp15_instruction_cache_invalidate(); \
0243   \
0244     ctrl = arm_cp15_get_control(); \
0245     ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M); \
0246     arm_cp15_set_control(ctrl); \
0247   \
0248     __asm__ volatile ( \
0249       ARM_SWITCH_TO_ARM \
0250       "mov pc, %[addr]\n" \
0251       ARM_SWITCH_BACK \
0252       : ARM_SWITCH_OUTPUT \
0253       : [addr] "r" (addr) \
0254     ); \
0255   } while (0)
0256
0257 #ifdef __cplusplus
0258 }
0259 #endif /* __cplusplus */
0260
0261 #endif /* ASM */
0262
0263 /** @} */
0264
0265 #endif /* LIBBSP_ARM_LPC32XX_BSP_H */