lpc24xx/start/start-config-emc-static.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMLPC24XX
0007  *
0008  * @brief BSP start EMC static memory configuration.
0009  */
0010
0011 /*
0012  * Copyright (c) 2011 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <bsp/start-config.h>
0037 #include <bsp/lpc24xx.h>
0038
0039 BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config
0040    lpc24xx_start_config_emc_static_chip [] = {
0041 #if defined(LPC24XX_EMC_M29W160E)
0042   /*
0043    * Static Memory 1: Numonyx M29W160EB
0044    *
0045    * 1 clock cycle = 1/72MHz = 13.9ns
0046    */
0047   {
0048     .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_1,
0049     .config = {
0050       /*
0051        * 16 bit, page mode disabled, active LOW chip select, extended wait
0052        * disabled, writes not protected, byte lane state LOW/LOW (!).
0053        */
0054       .config = 0x81,
0055
0056       /* 1 clock cycles delay from the chip select 1 to the write enable */
0057       .waitwen = 0,
0058
0059       /*
0060        * 0 clock cycles delay from the chip select 1 or address change
0061        * (whichever is later) to the output enable
0062        */
0063       .waitoen = 0,
0064
0065       /* 7 clock cycles delay from the chip select 1 to the read access */
0066       .waitrd = 0x6,
0067
0068       /*
0069        * 32 clock cycles delay for asynchronous page mode sequential accesses
0070        */
0071       .waitpage = 0x1f,
0072
0073       /* 5 clock cycles delay from the chip select 1 to the write access */
0074       .waitwr = 0x3,
0075
0076       /* 16 bus turnaround cycles */
0077       .waitrun = 0xf
0078     }
0079   }
0080 #elif defined(LPC24XX_EMC_M29W320E70)
0081   /* Static Memory 0: M29W320E70 */
0082   {
0083     .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0,
0084     .config = {
0085       /*
0086        * 16 bit, page mode disabled, active LOW chip select, extended wait
0087        * disabled, writes not protected, byte lane state LOW/LOW.
0088        */
0089       .config = 0x81,
0090
0091       /* 30ns (tWHWL) */
0092       .waitwen = LPC24XX_PS_TO_EMCCLK(30000, 1),
0093
0094       /* 0ns */
0095       .waitoen = LPC24XX_PS_TO_EMCCLK(0, 1),
0096
0097       /* 70ns (tAVQV, tELQV) */
0098       .waitrd = LPC24XX_PS_TO_EMCCLK(70000, 1),
0099
0100       /* 70ns (tAVQV, tELQV) */
0101       .waitpage = LPC24XX_PS_TO_EMCCLK(70000, 1),
0102
0103       /* max(30ns (tWHWL) + 45ns (tWLWH), 70ns (tAVAV)) */
0104       .waitwr = LPC24XX_PS_TO_EMCCLK(75000, 2),
0105
0106       /* 25ns (tEHQZ) */
0107       .waitrun = LPC24XX_PS_TO_EMCCLK(25000, 1)
0108     }
0109   }
0110 #elif defined(LPC24XX_EMC_SST39VF3201)
0111   /* Static Memory 0: SST39VF3201 */
0112   {
0113     .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0,
0114     .config = {
0115       /*
0116        * 16 bit, page mode disabled, active LOW chip select, extended wait
0117        * disabled, writes not protected, byte lane state LOW/LOW.
0118        */
0119       .config = 0x81,
0120
0121       /* 0ns (tCS, tAS) */
0122       .waitwen = LPC24XX_PS_TO_EMCCLK(0, 1),
0123
0124       /* 0ns (tOES) */
0125       .waitoen = LPC24XX_PS_TO_EMCCLK(0, 1),
0126
0127       /* 70ns (tRC) */
0128       .waitrd = LPC24XX_PS_TO_EMCCLK(70000, 1),
0129
0130       /* 70ns (tRC) */
0131       .waitpage = LPC24XX_PS_TO_EMCCLK(70000, 1),
0132
0133       /* 20ns (tCHZ, TOHZ) */
0134       .waitwr = LPC24XX_PS_TO_EMCCLK(20000, 2),
0135
0136       /* 20ns (tCHZ, TOHZ) */
0137       .waitrun = LPC24XX_PS_TO_EMCCLK(20000, 1)
0138     }
0139   }
0140 #endif
0141 };
0142
0143 BSP_START_DATA_SECTION const size_t
0144   lpc24xx_start_config_emc_static_chip_count =
0145     sizeof(lpc24xx_start_config_emc_static_chip)
0146       / sizeof(lpc24xx_start_config_emc_static_chip [0]);