lpc24xx/start/start-config-emc-dynamic.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMLPC24XX
0007  *
0008  * @brief BSP start EMC dynamic memory configuration.
0009  */
0010
0011 /*
0012  * Copyright (C) 2011, 2019 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <bsp/start-config.h>
0037 #include <bsp/lpc24xx.h>
0038
0039 /*
0040  * FIXME: The NXP example code uses different values for the following two
0041  * defines.  In the NXP example code they depend on the EMCCLK.  It is unclear
0042  * how these values are determined.  The values from the NXP example code do
0043  * not work.
0044  */
0045
0046 /* Use command delayed strategy */
0047 #define LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT 0x1
0048
0049 #define LPC24XX_EMCDLYCTL_DEFAULT 0x1112
0050
0051 BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
0052   lpc24xx_start_config_emc_dynamic [] = {
0053 #if defined(LPC24XX_EMC_MT48LC4M16A2)
0054   /* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
0055   {
0056     /* 15.6 us */
0057     .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
0058
0059     .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
0060
0061     /* Precharge command period 20 ns */
0062     .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
0063
0064     /* Active to precharge command period 44 ns */
0065     .tras = LPC24XX_PS_TO_EMCCLK(44000, 1),
0066
0067     /*
0068      * UM: "devices without this parameter you use the same value as tXSR"
0069      *
0070      * The tXSR is 75 ns.
0071      */
0072     .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
0073
0074     /*
0075      * Forum: "tAPR, not in datasheet, if fail, use tRCD val"
0076      *
0077      * The tRCD is 20 ns */
0078     .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
0079
0080     /* Data-in to active command period tWR + tRP */
0081     .tdal = LPC24XX_PS_TO_EMCCLK(15000 + 20000, 0),
0082
0083     /* Write recovery time 15 ns or 1 CLK + 7.5ns */
0084     .twr = LPC24XX_PS_TO_EMCCLK(15000, 1),
0085
0086     /* Active to active command period 66 ns */
0087     .trc = LPC24XX_PS_TO_EMCCLK(66000, 1),
0088
0089     /* Auto refresh period 66 ns */
0090     .trfc = LPC24XX_PS_TO_EMCCLK(66000, 1),
0091
0092     /* Exit self refresh to active command period 75 ns */
0093     .txsr = LPC24XX_PS_TO_EMCCLK(75000, 1),
0094
0095     /* Active bank a to active bank b command period 15 ns */
0096     .trrd = LPC24XX_PS_TO_EMCCLK(15000, 1),
0097
0098     /* Load mode register to active or refresh command period 2 tCK */
0099     .tmrd = 1, /* + 1 */
0100
0101     .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
0102   }
0103 #elif defined(LPC24XX_EMC_IS42S32800D7)
0104   /* Dynamic Memory 0: ISSI IS42S32800D7 */
0105   {
0106     /* 15.6 us */
0107     .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
0108
0109     .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
0110
0111     /* 20ns */
0112     .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
0113
0114     /* 45ns */
0115     .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
0116
0117     /* 70ns (tXSR) */
0118     .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
0119
0120     /* 20ns (tRCD) */
0121     .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
0122
0123     /* n clock cycles -> 38.8ns >= 35ns */
0124     .tdal = LPC24XX_PS_TO_EMCCLK(35000, 0),
0125
0126     /* 14ns (tDPL) */
0127     .twr = LPC24XX_PS_TO_EMCCLK(14000, 1),
0128
0129     /* 67.5ns */
0130     .trc = LPC24XX_PS_TO_EMCCLK(67500, 1),
0131
0132     /* 67.5ns (tRC) */
0133     .trfc = LPC24XX_PS_TO_EMCCLK(67500, 1),
0134
0135     /* 70ns */
0136     .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
0137
0138     /* 14ns */
0139     .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
0140
0141     /* 14ns */
0142     .tmrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
0143
0144     .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
0145   }
0146 #elif defined(LPC24XX_EMC_W9825G2JB75I)
0147   /* Dynamic Memory 0: Winbond W9825G2JB75I */
0148   {
0149     /* 15.6 us */
0150     .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
0151
0152     .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
0153
0154     /* 20ns */
0155     .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
0156
0157     /* 45ns */
0158     .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
0159
0160     /* 75ns (tXSR) */
0161     .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
0162
0163     /* 20ns (tRCD) */
0164     .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
0165
0166     /* tWR + tRP -> 2 * tCK + 20ns */
0167     .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
0168
0169     /* (n + 1) clock cycles == 2 * tCK */
0170     .twr = 1,
0171
0172     /* 65ns */
0173     .trc = LPC24XX_PS_TO_EMCCLK(65000, 1),
0174
0175     /* 65ns (tRC) */
0176     .trfc = LPC24XX_PS_TO_EMCCLK(65000, 1),
0177
0178     /* 75ns */
0179     .txsr = LPC24XX_PS_TO_EMCCLK(50000, 1),
0180
0181     /* (n + 1) clock cycles == 2 * tCK */
0182     .trrd = 1,
0183
0184     /* (n + 1) clock cycles == 2 * tCK (tRSC)*/
0185     .tmrd = 1,
0186
0187     .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
0188   }
0189 #elif defined(LPC24XX_EMC_K4S561632E)
0190   {
0191     .refresh = 35,
0192     .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
0193     .trp = 2,
0194     .tras = 4,
0195     .tsrex = 5,
0196     .tapr = 1,
0197     .tdal = 5,
0198     .twr = 3,
0199     .trc = 5,
0200     .trfc = 5,
0201     .txsr = 5,
0202     .trrd = 3,
0203     .tmrd = 2,
0204     .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
0205   }
0206 #elif defined(LPC24XX_EMC_IS42S32800B)
0207   {
0208     /* 15.6us */
0209     .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
0210
0211     .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
0212
0213     /* 20ns */
0214     .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
0215
0216     /* 45ns */
0217     .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
0218
0219     /* 70ns (tRC) */
0220     .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
0221
0222     /* FIXME */
0223     .tapr = LPC24XX_PS_TO_EMCCLK(40000, 1),
0224
0225     /* tWR + tRP -> 2 * tCK + 20ns */
0226     .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
0227
0228     /* (n + 1) clock cycles == 2 * tCK */
0229     .twr = 1,
0230
0231     /* 70ns */
0232     .trc = LPC24XX_PS_TO_EMCCLK(70000, 1),
0233
0234     /* 70ns */
0235     .trfc = LPC24XX_PS_TO_EMCCLK(70000, 1),
0236
0237     /* 70ns (tRC) */
0238     .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
0239
0240     /* 14ns */
0241     .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
0242
0243     /* (n + 1) clock cycles == 2 * tCK */
0244     .tmrd = 1,
0245
0246     .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
0247   }
0248 #endif
0249 };
0250
0251 /*
0252  * Mode shift is determined for RBC by:
0253  *
0254  *   bus width in bits / 16 + bank bits + column bits
0255  *
0256  * Mode shift is determined for BRC by:
0257  *
0258  *   bus width in bits / 16 + column bits
0259  */
0260 BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config
0261   lpc24xx_start_config_emc_dynamic_chip [] = {
0262 #if defined(LPC24XX_EMC_MT48LC4M16A2)
0263   {
0264     .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
0265
0266     /*
0267      * Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected
0268      * writes.  4 banks, 12 row lines, 8 column lines, RBC.
0269      */
0270     .config = 0x280,
0271
0272     .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
0273     .mode = 0xa0000000 | (0x23 << (1 + 2 + 8))
0274   }
0275 #elif defined(LPC24XX_EMC_W9825G2JB75I) \
0276   || defined(LPC24XX_EMC_IS42S32800D7) \
0277   || defined(LPC24XX_EMC_IS42S32800B)
0278   {
0279     .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
0280
0281     /* 32-bit data bus, 4 banks, 12 row lines, 9 column lines, RBC */
0282     .config = 0x4480,
0283
0284     /* RAS based on tRCD = 20ns */
0285     .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
0286
0287     /* CAS 2, burst length 4 */
0288     .mode = 0xa0000000 | (0x22 << (2 + 2 + 9))
0289   }
0290 #elif defined(LPC24XX_EMC_K4S561632E)
0291   {
0292     .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
0293     .config = 0x680,
0294     .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
0295     .mode = 0xa0000000 | (0x33 << 12)
0296   }
0297 #endif
0298 };
0299
0300 BSP_START_DATA_SECTION const size_t
0301   lpc24xx_start_config_emc_dynamic_chip_count =
0302     sizeof(lpc24xx_start_config_emc_dynamic_chip)
0303       / sizeof(lpc24xx_start_config_emc_dynamic_chip [0]);