lpc24xx/irq/irq.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSImplClassicIntr
0007  *
0008  * @brief LPC24XX interrupt support.
0009  */
0010
0011 /*
0012  * Copyright (C) 2008, 2012 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #include <rtems/score/armv4.h>
0037 #include <rtems/score/armv7m.h>
0038
0039 #include <bsp.h>
0040 #include <bsp/irq.h>
0041 #include <bsp/irq-generic.h>
0042 #include <bsp/lpc24xx.h>
0043 #include <bsp/linker-symbols.h>
0044
0045 static inline bool lpc24xx_irq_is_valid(rtems_vector_number vector)
0046 {
0047   return vector < BSP_INTERRUPT_VECTOR_COUNT;
0048 }
0049
0050 #ifdef ARM_MULTILIB_ARCH_V4
0051
0052 rtems_status_code bsp_interrupt_get_attributes(
0053   rtems_vector_number         vector,
0054   rtems_interrupt_attributes *attributes
0055 )
0056 {
0057   attributes->maximum_priority = LPC24XX_IRQ_PRIORITY_VALUE_MAX;
0058   attributes->can_get_priority = true;
0059   attributes->can_set_priority = true;
0060   return RTEMS_SUCCESSFUL;
0061 }
0062
0063 rtems_status_code bsp_interrupt_is_pending(
0064   rtems_vector_number vector,
0065   bool               *pending
0066 )
0067 {
0068   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0069   bsp_interrupt_assert(pending != NULL);
0070   *pending = false;
0071   return RTEMS_UNSATISFIED;
0072 }
0073
0074 rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
0075 {
0076   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0077   return RTEMS_UNSATISFIED;
0078 }
0079
0080 rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
0081 {
0082   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0083   return RTEMS_UNSATISFIED;
0084 }
0085
0086 rtems_status_code bsp_interrupt_vector_is_enabled(
0087   rtems_vector_number vector,
0088   bool               *enabled
0089 )
0090 {
0091   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0092   bsp_interrupt_assert(enabled != NULL);
0093   *enabled = false;
0094   return RTEMS_UNSATISFIED;
0095 }
0096
0097 rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
0098 {
0099   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0100   VICIntEnable = 1U << vector;
0101   return RTEMS_SUCCESSFUL;
0102 }
0103
0104 rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
0105 {
0106   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0107   VICIntEnClear = 1U << vector;
0108   return RTEMS_SUCCESSFUL;
0109 }
0110
0111 rtems_status_code bsp_interrupt_set_priority(
0112   rtems_vector_number vector,
0113   uint32_t priority
0114 )
0115 {
0116   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0117
0118   if (priority > LPC24XX_IRQ_PRIORITY_VALUE_MAX) {
0119     return RTEMS_INVALID_PRIORITY;
0120   }
0121
0122   VICVectPriorityBase [vector] = priority;
0123   return RTEMS_SUCCESSFUL;
0124 }
0125
0126 rtems_status_code bsp_interrupt_get_priority(
0127   rtems_vector_number vector,
0128   uint32_t *priority
0129 )
0130 {
0131   bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
0132   bsp_interrupt_assert(priority != NULL);
0133
0134   *priority = VICVectPriorityBase [vector];
0135   return RTEMS_SUCCESSFUL;
0136 }
0137
0138 void bsp_interrupt_facility_initialize(void)
0139 {
0140   volatile uint32_t *addr = VICVectAddrBase;
0141   volatile uint32_t *prio = VICVectPriorityBase;
0142   rtems_vector_number i = 0;
0143
0144   /* Disable all interrupts */
0145   VICIntEnClear = 0xffffffff;
0146
0147   /* Clear all software interrupts */
0148   VICSoftIntClear = 0xffffffff;
0149
0150   /* Use IRQ category */
0151   VICIntSelect = 0;
0152
0153   for (i = 0; i < BSP_INTERRUPT_VECTOR_COUNT; ++i) {
0154     /* Use the vector address register to store the vector number */
0155     addr [i] = i;
0156
0157     /* Give vector lowest priority */
0158     prio [i] = 15;
0159   }
0160
0161   /* Reset priority mask register */
0162   VICSWPrioMask = 0xffff;
0163
0164   /* Acknowledge interrupts for all priorities */
0165   for (
0166     i = LPC24XX_IRQ_PRIORITY_VALUE_MIN;
0167     i <= LPC24XX_IRQ_PRIORITY_VALUE_MAX;
0168     ++i
0169   ) {
0170     VICVectAddr = 0;
0171   }
0172
0173   /* Install the IRQ exception handler */
0174   _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
0175 }
0176
0177 #endif /* ARM_MULTILIB_ARCH_V4 */