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0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002 
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMLPC24XX_regs
0007  *
0008  * @brief Register definitions.
0009  */
0010 
0011 /*
0012  * Copyright (C) 2008, 2011 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035 
0036 #ifndef LIBBSP_ARM_LPC24XX_LPC24XX_H
0037 #define LIBBSP_ARM_LPC24XX_LPC24XX_H
0038 
0039 #include <rtems/score/cpu.h>
0040 #include <bsp/utility.h>
0041 #include <bsp/lpc-i2s.h>
0042 
0043 #ifdef ARM_MULTILIB_ARCH_V7M
0044   #include <bsp/lpc17xx.h>
0045 #endif
0046 
0047 /**
0048  * @defgroup lpc24xx_regs Register Definitions
0049  *
0050  * @ingroup RTEMSBSPsARMLPC24XX
0051  *
0052  * @brief Register definitions.
0053  *
0054  * @{
0055  */
0056 
0057 #ifdef ARM_MULTILIB_ARCH_V4
0058 
0059 /* Vectored Interrupt Controller (VIC) */
0060 #define VIC_BASE_ADDR   0xFFFFF000
0061 #define VICIRQStatus   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x000))
0062 #define VICFIQStatus   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x004))
0063 #define VICRawIntr     (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x008))
0064 #define VICIntSelect   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x00C))
0065 #define VICIntEnable   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x010))
0066 #define VICIntEnClear  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x014))
0067 #define VICSoftInt     (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x018))
0068 #define VICSoftIntClear (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x01C))
0069 #define VICProtection  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x020))
0070 #define VICSWPrioMask  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x024))
0071 
0072 #define VICVectAddrBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
0073 #define VICVectAddr0   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
0074 #define VICVectAddr1   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x104))
0075 #define VICVectAddr2   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x108))
0076 #define VICVectAddr3   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x10C))
0077 #define VICVectAddr4   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x110))
0078 #define VICVectAddr5   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x114))
0079 #define VICVectAddr6   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x118))
0080 #define VICVectAddr7   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x11C))
0081 #define VICVectAddr8   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x120))
0082 #define VICVectAddr9   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x124))
0083 #define VICVectAddr10  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x128))
0084 #define VICVectAddr11  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x12C))
0085 #define VICVectAddr12  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x130))
0086 #define VICVectAddr13  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x134))
0087 #define VICVectAddr14  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x138))
0088 #define VICVectAddr15  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x13C))
0089 #define VICVectAddr16  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x140))
0090 #define VICVectAddr17  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x144))
0091 #define VICVectAddr18  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x148))
0092 #define VICVectAddr19  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x14C))
0093 #define VICVectAddr20  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x150))
0094 #define VICVectAddr21  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x154))
0095 #define VICVectAddr22  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x158))
0096 #define VICVectAddr23  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x15C))
0097 #define VICVectAddr24  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x160))
0098 #define VICVectAddr25  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x164))
0099 #define VICVectAddr26  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x168))
0100 #define VICVectAddr27  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x16C))
0101 #define VICVectAddr28  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x170))
0102 #define VICVectAddr29  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x174))
0103 #define VICVectAddr30  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x178))
0104 #define VICVectAddr31  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x17C))
0105 
0106 #define VICVectPriorityBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
0107 #define VICVectPriority0   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
0108 #define VICVectPriority1   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x204))
0109 #define VICVectPriority2   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x208))
0110 #define VICVectPriority3   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x20C))
0111 #define VICVectPriority4   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x210))
0112 #define VICVectPriority5   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x214))
0113 #define VICVectPriority6   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x218))
0114 #define VICVectPriority7   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x21C))
0115 #define VICVectPriority8   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x220))
0116 #define VICVectPriority9   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x224))
0117 #define VICVectPriority10  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x228))
0118 #define VICVectPriority11  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x22C))
0119 #define VICVectPriority12  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x230))
0120 #define VICVectPriority13  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x234))
0121 #define VICVectPriority14  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x238))
0122 #define VICVectPriority15  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x23C))
0123 #define VICVectPriority16  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x240))
0124 #define VICVectPriority17  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x244))
0125 #define VICVectPriority18  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x248))
0126 #define VICVectPriority19  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x24C))
0127 #define VICVectPriority20  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x250))
0128 #define VICVectPriority21  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x254))
0129 #define VICVectPriority22  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x258))
0130 #define VICVectPriority23  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x25C))
0131 #define VICVectPriority24  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x260))
0132 #define VICVectPriority25  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x264))
0133 #define VICVectPriority26  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x268))
0134 #define VICVectPriority27  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x26C))
0135 #define VICVectPriority28  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x270))
0136 #define VICVectPriority29  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x274))
0137 #define VICVectPriority30  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x278))
0138 #define VICVectPriority31  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x27C))
0139 
0140 #define VICVectAddr    (*(volatile uint32_t *) (VIC_BASE_ADDR + 0xF00))
0141 
0142 #endif /* ARM_MULTILIB_ARCH_V4 */
0143 
0144 /* Pin Connect Block */
0145 #ifdef ARM_MULTILIB_ARCH_V4
0146   #define PINSEL_BASE_ADDR  0xE002C000
0147 #else
0148   #define PINSEL_BASE_ADDR  0x4002C000
0149 #endif
0150 
0151 #ifdef ARM_MULTILIB_ARCH_V4
0152 
0153 #define PINSEL0        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x00))
0154 #define PINSEL1        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x04))
0155 #define PINSEL2        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x08))
0156 #define PINSEL3        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x0C))
0157 #define PINSEL4        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x10))
0158 #define PINSEL5        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x14))
0159 #define PINSEL6        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x18))
0160 #define PINSEL7        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x1C))
0161 #define PINSEL8        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x20))
0162 #define PINSEL9        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x24))
0163 #define PINSEL10       (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x28))
0164 #define PINSEL11       (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x2C))
0165 
0166 #define PINMODE0        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x40))
0167 #define PINMODE1        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x44))
0168 #define PINMODE2        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x48))
0169 #define PINMODE3        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x4C))
0170 #define PINMODE4        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x50))
0171 #define PINMODE5        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x54))
0172 #define PINMODE6        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x58))
0173 #define PINMODE7        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x5C))
0174 #define PINMODE8        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x60))
0175 #define PINMODE9        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x64))
0176 
0177 #endif /* ARM_MULTILIB_ARCH_V4 */
0178 
0179 /* General Purpose Input/Output (GPIO) */
0180 #ifdef ARM_MULTILIB_ARCH_V4
0181   #define GPIO_BASE_ADDR        0xE0028000
0182 #else
0183   #define GPIO_BASE_ADDR        0x40028000
0184 #endif
0185 #define IOPIN0         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x00))
0186 #define IOSET0         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x04))
0187 #define IODIR0         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x08))
0188 #define IOCLR0         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x0C))
0189 #define IOPIN1         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x10))
0190 #define IOSET1         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x14))
0191 #define IODIR1         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x18))
0192 #define IOCLR1         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x1C))
0193 
0194 /* GPIO Interrupt Registers */
0195 #define IO0_INT_EN_R    (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x90))
0196 #define IO0_INT_EN_F    (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x94))
0197 #define IO0_INT_STAT_R  (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x84))
0198 #define IO0_INT_STAT_F  (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x88))
0199 #define IO0_INT_CLR     (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x8C))
0200 
0201 #define IO2_INT_EN_R    (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB0))
0202 #define IO2_INT_EN_F    (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB4))
0203 #define IO2_INT_STAT_R  (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA4))
0204 #define IO2_INT_STAT_F  (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA8))
0205 #define IO2_INT_CLR     (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xAC))
0206 
0207 #define IO_INT_STAT     (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x80))
0208 
0209 #ifdef ARM_MULTILIB_ARCH_V4
0210 
0211 #define PARTCFG_BASE_ADDR       0x3FFF8000
0212 #define PARTCFG        (*(volatile uint32_t *) (PARTCFG_BASE_ADDR + 0x00))
0213 
0214 #endif /* ARM_MULTILIB_ARCH_V4 */
0215 
0216 /* Fast I/O setup */
0217 #ifdef ARM_MULTILIB_ARCH_V4
0218   #define FIO_BASE_ADDR     0x3FFFC000
0219 #else
0220   #define FIO_BASE_ADDR     0x20098000
0221 #endif
0222 #define FIO0DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x00))
0223 #define FIO0MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x10))
0224 #define FIO0PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x14))
0225 #define FIO0SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x18))
0226 #define FIO0CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x1C))
0227 
0228 #define FIO1DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x20))
0229 #define FIO1MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x30))
0230 #define FIO1PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x34))
0231 #define FIO1SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x38))
0232 #define FIO1CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x3C))
0233 
0234 #define FIO2DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x40))
0235 #define FIO2MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x50))
0236 #define FIO2PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x54))
0237 #define FIO2SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x58))
0238 #define FIO2CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x5C))
0239 
0240 #define FIO3DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x60))
0241 #define FIO3MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x70))
0242 #define FIO3PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x74))
0243 #define FIO3SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x78))
0244 #define FIO3CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x7C))
0245 
0246 #define FIO4DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x80))
0247 #define FIO4MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x90))
0248 #define FIO4PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x94))
0249 #define FIO4SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x98))
0250 #define FIO4CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x9C))
0251 
0252 #ifdef ARM_MULTILIB_ARCH_V7M
0253 
0254 #define FIO5DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xa0))
0255 #define FIO5MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb0))
0256 #define FIO5PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb4))
0257 #define FIO5SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb8))
0258 #define FIO5CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xbC))
0259 
0260 #endif /* ARM_MULTILIB_ARCH_V7M */
0261 
0262 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
0263 #define FIO0DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x00))
0264 #define FIO1DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x20))
0265 #define FIO2DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x40))
0266 #define FIO3DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x60))
0267 #define FIO4DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x80))
0268 
0269 #define FIO0DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x01))
0270 #define FIO1DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
0271 #define FIO2DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x41))
0272 #define FIO3DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x61))
0273 #define FIO4DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x81))
0274 
0275 #define FIO0DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x02))
0276 #define FIO1DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x22))
0277 #define FIO2DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x42))
0278 #define FIO3DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x62))
0279 #define FIO4DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x82))
0280 
0281 #define FIO0DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x03))
0282 #define FIO1DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x23))
0283 #define FIO2DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x43))
0284 #define FIO3DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x63))
0285 #define FIO4DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x83))
0286 
0287 #define FIO0DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x00))
0288 #define FIO1DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x20))
0289 #define FIO2DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x40))
0290 #define FIO3DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x60))
0291 #define FIO4DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x80))
0292 
0293 #define FIO0DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x02))
0294 #define FIO1DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x22))
0295 #define FIO2DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x42))
0296 #define FIO3DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x62))
0297 #define FIO4DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x82))
0298 
0299 #define FIO0MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x10))
0300 #define FIO1MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x30))
0301 #define FIO2MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x50))
0302 #define FIO3MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x70))
0303 #define FIO4MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x90))
0304 
0305 #define FIO0MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x11))
0306 #define FIO1MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
0307 #define FIO2MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x51))
0308 #define FIO3MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x71))
0309 #define FIO4MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x91))
0310 
0311 #define FIO0MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x12))
0312 #define FIO1MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x32))
0313 #define FIO2MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x52))
0314 #define FIO3MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x72))
0315 #define FIO4MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x92))
0316 
0317 #define FIO0MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x13))
0318 #define FIO1MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x33))
0319 #define FIO2MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x53))
0320 #define FIO3MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x73))
0321 #define FIO4MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x93))
0322 
0323 #define FIO0MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x10))
0324 #define FIO1MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x30))
0325 #define FIO2MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x50))
0326 #define FIO3MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x70))
0327 #define FIO4MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x90))
0328 
0329 #define FIO0MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x12))
0330 #define FIO1MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x32))
0331 #define FIO2MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x52))
0332 #define FIO3MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x72))
0333 #define FIO4MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x92))
0334 
0335 #define FIO0PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x14))
0336 #define FIO1PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x34))
0337 #define FIO2PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x54))
0338 #define FIO3PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x74))
0339 #define FIO4PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x94))
0340 
0341 #define FIO0PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x15))
0342 #define FIO1PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x25))
0343 #define FIO2PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x55))
0344 #define FIO3PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x75))
0345 #define FIO4PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x95))
0346 
0347 #define FIO0PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x16))
0348 #define FIO1PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x36))
0349 #define FIO2PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x56))
0350 #define FIO3PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x76))
0351 #define FIO4PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x96))
0352 
0353 #define FIO0PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x17))
0354 #define FIO1PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x37))
0355 #define FIO2PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x57))
0356 #define FIO3PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x77))
0357 #define FIO4PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x97))
0358 
0359 #define FIO0PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x14))
0360 #define FIO1PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x34))
0361 #define FIO2PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x54))
0362 #define FIO3PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x74))
0363 #define FIO4PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x94))
0364 
0365 #define FIO0PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x16))
0366 #define FIO1PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x36))
0367 #define FIO2PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x56))
0368 #define FIO3PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x76))
0369 #define FIO4PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x96))
0370 
0371 #define FIO0SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x18))
0372 #define FIO1SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x38))
0373 #define FIO2SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x58))
0374 #define FIO3SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x78))
0375 #define FIO4SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x98))
0376 
0377 #define FIO0SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x19))
0378 #define FIO1SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x29))
0379 #define FIO2SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x59))
0380 #define FIO3SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x79))
0381 #define FIO4SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x99))
0382 
0383 #define FIO0SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1A))
0384 #define FIO1SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3A))
0385 #define FIO2SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5A))
0386 #define FIO3SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7A))
0387 #define FIO4SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9A))
0388 
0389 #define FIO0SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1B))
0390 #define FIO1SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3B))
0391 #define FIO2SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5B))
0392 #define FIO3SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7B))
0393 #define FIO4SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9B))
0394 
0395 #define FIO0SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x18))
0396 #define FIO1SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x38))
0397 #define FIO2SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x58))
0398 #define FIO3SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x78))
0399 #define FIO4SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x98))
0400 
0401 #define FIO0SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1A))
0402 #define FIO1SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3A))
0403 #define FIO2SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5A))
0404 #define FIO3SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7A))
0405 #define FIO4SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9A))
0406 
0407 #define FIO0CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1C))
0408 #define FIO1CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3C))
0409 #define FIO2CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5C))
0410 #define FIO3CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7C))
0411 #define FIO4CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9C))
0412 
0413 #define FIO0CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1D))
0414 #define FIO1CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x2D))
0415 #define FIO2CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5D))
0416 #define FIO3CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7D))
0417 #define FIO4CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9D))
0418 
0419 #define FIO0CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1E))
0420 #define FIO1CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3E))
0421 #define FIO2CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5E))
0422 #define FIO3CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7E))
0423 #define FIO4CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9E))
0424 
0425 #define FIO0CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1F))
0426 #define FIO1CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3F))
0427 #define FIO2CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5F))
0428 #define FIO3CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7F))
0429 #define FIO4CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9F))
0430 
0431 #define FIO0CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1C))
0432 #define FIO1CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3C))
0433 #define FIO2CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5C))
0434 #define FIO3CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7C))
0435 #define FIO4CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9C))
0436 
0437 #define FIO0CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1E))
0438 #define FIO1CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3E))
0439 #define FIO2CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5E))
0440 #define FIO3CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7E))
0441 #define FIO4CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9E))
0442 
0443 #ifdef ARM_MULTILIB_ARCH_V4
0444 
0445 /* System Control Block(SCB) modules include Memory Accelerator Module,
0446 Phase Locked Loop, VPB divider, Power Control, External Interrupt,
0447 Reset, and Code Security/Debugging */
0448 #define SCB_BASE_ADDR   0xE01FC000
0449 
0450 /* Memory Accelerator Module (MAM) */
0451 #define MAMCR          (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x000))
0452 #define MAMTIM         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x004))
0453 #define MEMMAP         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x040))
0454 
0455 /* Phase Locked Loop (PLL) */
0456 #define PLLCON         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x080))
0457 #define PLLCFG         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x084))
0458 #define PLLSTAT        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x088))
0459 #define PLLFEED        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x08C))
0460 
0461 /* Power Control */
0462 #define PCON           (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C0))
0463 #define PCONP          (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C4))
0464 
0465 /* Clock Divider */
0466 // #define APBDIV         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x100))
0467 #define CCLKCFG        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x104))
0468 #define USBCLKCFG      (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x108))
0469 #define CLKSRCSEL      (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x10C))
0470 #define PCLKSEL0       (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A8))
0471 #define PCLKSEL1       (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1AC))
0472 
0473 /* External Interrupts */
0474 #define EXTINT         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x140))
0475 #define INTWAKE        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x144))
0476 #define EXTMODE        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x148))
0477 #define EXTPOLAR       (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x14C))
0478 
0479 /* Reset, reset source identification */
0480 #define RSIR           (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x180))
0481 
0482 /* RSID, code security protection */
0483 #define CSPR           (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x184))
0484 
0485 /* AHB configuration */
0486 #define AHBCFG1        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x188))
0487 #define AHBCFG2        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x18C))
0488 
0489 /* System Controls and Status */
0490 #define SCS            (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A0))
0491 
0492 #endif /* ARM_MULTILIB_ARCH_V4 */
0493 
0494 /* External Memory Controller (EMC) */
0495 #ifdef ARM_MULTILIB_ARCH_V4
0496   #define EMC_BASE_ADDR     0xFFE08000
0497 #else
0498   #define EMC_BASE_ADDR     0x2009c000
0499 #endif
0500 #define EMC_CTRL       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x000))
0501 #define EMC_STAT       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x004))
0502 #define EMC_CONFIG     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x008))
0503 
0504 /* Dynamic RAM access registers */
0505 #define EMC_DYN_CTRL     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x020))
0506 #define EMC_DYN_RFSH     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x024))
0507 #define EMC_DYN_RD_CFG   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x028))
0508 #define EMC_DYN_RP       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x030))
0509 #define EMC_DYN_RAS      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x034))
0510 #define EMC_DYN_SREX     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x038))
0511 #define EMC_DYN_APR      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x03C))
0512 #define EMC_DYN_DAL      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x040))
0513 #define EMC_DYN_WR       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x044))
0514 #define EMC_DYN_RC       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x048))
0515 #define EMC_DYN_RFC      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x04C))
0516 #define EMC_DYN_XSR      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x050))
0517 #define EMC_DYN_RRD      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x054))
0518 #define EMC_DYN_MRD      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x058))
0519 
0520 #define EMC_DYN_CFG0     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x100))
0521 #define EMC_DYN_RASCAS0  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x104))
0522 #define EMC_DYN_CFG1     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x140))
0523 #define EMC_DYN_RASCAS1  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x144))
0524 #define EMC_DYN_CFG2     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x160))
0525 #define EMC_DYN_RASCAS2  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x164))
0526 #define EMC_DYN_CFG3     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x180))
0527 #define EMC_DYN_RASCAS3  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x184))
0528 
0529 /* static RAM access registers */
0530 #define EMC_STA_BASE_0    ((uint32_t *) (EMC_BASE_ADDR + 0x200))
0531 #define EMC_STA_CFG0      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x200))
0532 #define EMC_STA_WAITWEN0  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x204))
0533 #define EMC_STA_WAITOEN0  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x208))
0534 #define EMC_STA_WAITRD0   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x20C))
0535 #define EMC_STA_WAITPAGE0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x210))
0536 #define EMC_STA_WAITWR0   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x214))
0537 #define EMC_STA_WAITTURN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x218))
0538 
0539 #define EMC_STA_BASE_1    ((uint32_t *) (EMC_BASE_ADDR + 0x220))
0540 #define EMC_STA_CFG1      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x220))
0541 #define EMC_STA_WAITWEN1  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x224))
0542 #define EMC_STA_WAITOEN1  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x228))
0543 #define EMC_STA_WAITRD1   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x22C))
0544 #define EMC_STA_WAITPAGE1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x230))
0545 #define EMC_STA_WAITWR1   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x234))
0546 #define EMC_STA_WAITTURN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x238))
0547 
0548 #define EMC_STA_BASE_2    ((uint32_t *) (EMC_BASE_ADDR + 0x240))
0549 #define EMC_STA_CFG2      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x240))
0550 #define EMC_STA_WAITWEN2  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x244))
0551 #define EMC_STA_WAITOEN2  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x248))
0552 #define EMC_STA_WAITRD2   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x24C))
0553 #define EMC_STA_WAITPAGE2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x250))
0554 #define EMC_STA_WAITWR2   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x254))
0555 #define EMC_STA_WAITTURN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x258))
0556 
0557 #define EMC_STA_BASE_3    ((uint32_t *) (EMC_BASE_ADDR + 0x260))
0558 #define EMC_STA_CFG3      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x260))
0559 #define EMC_STA_WAITWEN3  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x264))
0560 #define EMC_STA_WAITOEN3  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x268))
0561 #define EMC_STA_WAITRD3   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x26C))
0562 #define EMC_STA_WAITPAGE3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x270))
0563 #define EMC_STA_WAITWR3   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x274))
0564 #define EMC_STA_WAITTURN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x278))
0565 
0566 #define EMC_STA_EXT_WAIT  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x880))
0567 
0568 
0569 /* Timer 0 */
0570 #ifdef ARM_MULTILIB_ARCH_V4
0571   #define TMR0_BASE_ADDR        0xE0004000
0572 #else
0573   #define TMR0_BASE_ADDR        0x40004000
0574 #endif
0575 #define T0IR           (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x00))
0576 #define T0TCR          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x04))
0577 #define T0TC           (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x08))
0578 #define T0PR           (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x0C))
0579 #define T0PC           (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x10))
0580 #define T0MCR          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x14))
0581 #define T0MR0          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x18))
0582 #define T0MR1          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x1C))
0583 #define T0MR2          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x20))
0584 #define T0MR3          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x24))
0585 #define T0CCR          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x28))
0586 #define T0CR0          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x2C))
0587 #define T0CR1          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x30))
0588 #define T0CR2          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x34))
0589 #define T0CR3          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x38))
0590 #define T0EMR          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x3C))
0591 #define T0CTCR         (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x70))
0592 
0593 /* Timer 1 */
0594 #ifdef ARM_MULTILIB_ARCH_V4
0595   #define TMR1_BASE_ADDR        0xE0008000
0596 #else
0597   #define TMR1_BASE_ADDR        0x40008000
0598 #endif
0599 #define T1IR           (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x00))
0600 #define T1TCR          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x04))
0601 #define T1TC           (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x08))
0602 #define T1PR           (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x0C))
0603 #define T1PC           (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x10))
0604 #define T1MCR          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x14))
0605 #define T1MR0          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x18))
0606 #define T1MR1          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x1C))
0607 #define T1MR2          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x20))
0608 #define T1MR3          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x24))
0609 #define T1CCR          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x28))
0610 #define T1CR0          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x2C))
0611 #define T1CR1          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x30))
0612 #define T1CR2          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x34))
0613 #define T1CR3          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x38))
0614 #define T1EMR          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x3C))
0615 #define T1CTCR         (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x70))
0616 
0617 /* Timer 2 */
0618 #ifdef ARM_MULTILIB_ARCH_V4
0619   #define TMR2_BASE_ADDR        0xE0070000
0620 #else
0621   #define TMR2_BASE_ADDR        0x40090000
0622 #endif
0623 #define T2IR           (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x00))
0624 #define T2TCR          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x04))
0625 #define T2TC           (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x08))
0626 #define T2PR           (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x0C))
0627 #define T2PC           (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x10))
0628 #define T2MCR          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x14))
0629 #define T2MR0          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x18))
0630 #define T2MR1          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x1C))
0631 #define T2MR2          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x20))
0632 #define T2MR3          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x24))
0633 #define T2CCR          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x28))
0634 #define T2CR0          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x2C))
0635 #define T2CR1          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x30))
0636 #define T2CR2          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x34))
0637 #define T2CR3          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x38))
0638 #define T2EMR          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x3C))
0639 #define T2CTCR         (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x70))
0640 
0641 /* Timer 3 */
0642 #ifdef ARM_MULTILIB_ARCH_V4
0643   #define TMR3_BASE_ADDR        0xE0074000
0644 #else
0645   #define TMR3_BASE_ADDR        0x40094000
0646 #endif
0647 #define T3IR           (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x00))
0648 #define T3TCR          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x04))
0649 #define T3TC           (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x08))
0650 #define T3PR           (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x0C))
0651 #define T3PC           (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x10))
0652 #define T3MCR          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x14))
0653 #define T3MR0          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x18))
0654 #define T3MR1          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x1C))
0655 #define T3MR2          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x20))
0656 #define T3MR3          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x24))
0657 #define T3CCR          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x28))
0658 #define T3CR0          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x2C))
0659 #define T3CR1          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x30))
0660 #define T3CR2          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x34))
0661 #define T3CR3          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x38))
0662 #define T3EMR          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x3C))
0663 #define T3CTCR         (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x70))
0664 
0665 
0666 /* Pulse Width Modulator (PWM) */
0667 #ifdef ARM_MULTILIB_ARCH_V4
0668   #define PWM0_BASE_ADDR        0xE0014000
0669 #else
0670   #define PWM0_BASE_ADDR        0x40014000
0671 #endif
0672 #define PWM0IR          (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x00))
0673 #define PWM0TCR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x04))
0674 #define PWM0TC          (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x08))
0675 #define PWM0PR          (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x0C))
0676 #define PWM0PC          (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x10))
0677 #define PWM0MCR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x14))
0678 #define PWM0MR0         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x18))
0679 #define PWM0MR1         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x1C))
0680 #define PWM0MR2         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x20))
0681 #define PWM0MR3         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x24))
0682 #define PWM0CCR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x28))
0683 #define PWM0CR0         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x2C))
0684 #define PWM0CR1         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x30))
0685 #define PWM0CR2         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x34))
0686 #define PWM0CR3         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x38))
0687 #define PWM0EMR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x3C))
0688 #define PWM0MR4         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x40))
0689 #define PWM0MR5         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x44))
0690 #define PWM0MR6         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x48))
0691 #define PWM0PCR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x4C))
0692 #define PWM0LER         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x50))
0693 #define PWM0CTCR        (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x70))
0694 
0695 #ifdef ARM_MULTILIB_ARCH_V4
0696   #define PWM1_BASE_ADDR        0xE0018000
0697 #else
0698   #define PWM1_BASE_ADDR        0x40018000
0699 #endif
0700 #define PWM1IR          (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x00))
0701 #define PWM1TCR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x04))
0702 #define PWM1TC          (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x08))
0703 #define PWM1PR          (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x0C))
0704 #define PWM1PC          (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x10))
0705 #define PWM1MCR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x14))
0706 #define PWM1MR0         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x18))
0707 #define PWM1MR1         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x1C))
0708 #define PWM1MR2         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x20))
0709 #define PWM1MR3         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x24))
0710 #define PWM1CCR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x28))
0711 #define PWM1CR0         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x2C))
0712 #define PWM1CR1         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x30))
0713 #define PWM1CR2         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x34))
0714 #define PWM1CR3         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x38))
0715 #define PWM1EMR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x3C))
0716 #define PWM1MR4         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x40))
0717 #define PWM1MR5         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x44))
0718 #define PWM1MR6         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x48))
0719 #define PWM1PCR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x4C))
0720 #define PWM1LER         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x50))
0721 #define PWM1CTCR        (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x70))
0722 
0723 
0724 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
0725 #ifdef ARM_MULTILIB_ARCH_V4
0726   #define UART0_BASE_ADDR       0xE000C000
0727 #else
0728   #define UART0_BASE_ADDR       0x4000C000
0729 #endif
0730 #define U0RBR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
0731 #define U0THR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
0732 #define U0DLL          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
0733 #define U0DLM          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04))
0734 #define U0IER          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04))
0735 #define U0IIR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08))
0736 #define U0FCR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08))
0737 #define U0LCR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x0C))
0738 #define U0LSR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x14))
0739 #define U0SCR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x1C))
0740 #define U0ACR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x20))
0741 #define U0ICR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x24))
0742 #define U0FDR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x28))
0743 #define U0TER          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x30))
0744 
0745 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
0746 #ifdef ARM_MULTILIB_ARCH_V4
0747   #define UART1_BASE_ADDR       0xE0010000
0748 #else
0749   #define UART1_BASE_ADDR       0x40010000
0750 #endif
0751 #define U1RBR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
0752 #define U1THR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
0753 #define U1DLL          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
0754 #define U1DLM          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04))
0755 #define U1IER          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04))
0756 #define U1IIR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08))
0757 #define U1FCR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08))
0758 #define U1LCR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x0C))
0759 #define U1MCR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x10))
0760 #define U1LSR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x14))
0761 #define U1MSR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x18))
0762 #define U1SCR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x1C))
0763 #define U1ACR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x20))
0764 #define U1FDR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x28))
0765 #define U1TER          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x30))
0766 
0767 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
0768 #ifdef ARM_MULTILIB_ARCH_V4
0769   #define UART2_BASE_ADDR       0xE0078000
0770 #else
0771   #define UART2_BASE_ADDR       0x40098000
0772 #endif
0773 #define U2RBR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
0774 #define U2THR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
0775 #define U2DLL          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
0776 #define U2DLM          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04))
0777 #define U2IER          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04))
0778 #define U2IIR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08))
0779 #define U2FCR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08))
0780 #define U2LCR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x0C))
0781 #define U2LSR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x14))
0782 #define U2SCR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x1C))
0783 #define U2ACR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x20))
0784 #define U2ICR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x24))
0785 #define U2FDR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x28))
0786 #define U2TER          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x30))
0787 
0788 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
0789 #ifdef ARM_MULTILIB_ARCH_V4
0790   #define UART3_BASE_ADDR       0xE007C000
0791 #else
0792   #define UART3_BASE_ADDR       0x4009C000
0793 #endif
0794 #define U3RBR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
0795 #define U3THR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
0796 #define U3DLL          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
0797 #define U3DLM          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04))
0798 #define U3IER          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04))
0799 #define U3IIR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08))
0800 #define U3FCR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08))
0801 #define U3LCR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x0C))
0802 #define U3LSR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x14))
0803 #define U3SCR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x1C))
0804 #define U3ACR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x20))
0805 #define U3ICR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x24))
0806 #define U3FDR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x28))
0807 #define U3TER          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x30))
0808 
0809 /* I2C Interface 0 */
0810 #ifdef ARM_MULTILIB_ARCH_V4
0811   #define I2C0_BASE_ADDR        0xE001C000
0812 #else
0813   #define I2C0_BASE_ADDR        0x4001C000
0814 #endif
0815 #define I20CONSET      (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x00))
0816 #define I20STAT        (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x04))
0817 #define I20DAT         (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x08))
0818 #define I20ADR         (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x0C))
0819 #define I20SCLH        (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x10))
0820 #define I20SCLL        (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x14))
0821 #define I20CONCLR      (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x18))
0822 
0823 /* I2C Interface 1 */
0824 #ifdef ARM_MULTILIB_ARCH_V4
0825   #define I2C1_BASE_ADDR        0xE005C000
0826 #else
0827   #define I2C1_BASE_ADDR        0x4005C000
0828 #endif
0829 #define I21CONSET      (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x00))
0830 #define I21STAT        (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x04))
0831 #define I21DAT         (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x08))
0832 #define I21ADR         (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x0C))
0833 #define I21SCLH        (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x10))
0834 #define I21SCLL        (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x14))
0835 #define I21CONCLR      (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x18))
0836 
0837 /* I2C Interface 2 */
0838 #ifdef ARM_MULTILIB_ARCH_V4
0839   #define I2C2_BASE_ADDR        0xE0080000
0840 #else
0841   #define I2C2_BASE_ADDR        0x400a0000
0842 #endif
0843 #define I22CONSET      (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x00))
0844 #define I22STAT        (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x04))
0845 #define I22DAT         (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x08))
0846 #define I22ADR         (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x0C))
0847 #define I22SCLH        (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x10))
0848 #define I22SCLL        (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x14))
0849 #define I22CONCLR      (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x18))
0850 
0851 /* SPI0 (Serial Peripheral Interface 0) */
0852 #define SPI0_BASE_ADDR      0xE0020000
0853 #define S0SPCR         (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x00))
0854 #define S0SPSR         (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x04))
0855 #define S0SPDR         (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x08))
0856 #define S0SPCCR        (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x0C))
0857 #define S0SPINT        (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x1C))
0858 
0859 /* SSP0 Controller */
0860 #ifdef ARM_MULTILIB_ARCH_V4
0861   #define SSP0_BASE_ADDR        0xE0068000
0862 #else
0863   #define SSP0_BASE_ADDR        0x40088000
0864 #endif
0865 #define SSP0CR0        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x00))
0866 #define SSP0CR1        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x04))
0867 #define SSP0DR         (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x08))
0868 #define SSP0SR         (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x0C))
0869 #define SSP0CPSR       (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x10))
0870 #define SSP0IMSC       (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x14))
0871 #define SSP0RIS        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x18))
0872 #define SSP0MIS        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x1C))
0873 #define SSP0ICR        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x20))
0874 #define SSP0DMACR      (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x24))
0875 
0876 /* SSP1 Controller */
0877 #ifdef ARM_MULTILIB_ARCH_V4
0878   #define SSP1_BASE_ADDR        0xE0030000
0879 #else
0880   #define SSP1_BASE_ADDR        0x40030000
0881 #endif
0882 #define SSP1CR0        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x00))
0883 #define SSP1CR1        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x04))
0884 #define SSP1DR         (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x08))
0885 #define SSP1SR         (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x0C))
0886 #define SSP1CPSR       (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x10))
0887 #define SSP1IMSC       (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x14))
0888 #define SSP1RIS        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x18))
0889 #define SSP1MIS        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x1C))
0890 #define SSP1ICR        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x20))
0891 #define SSP1DMACR      (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x24))
0892 
0893 #ifdef ARM_MULTILIB_ARCH_V7M
0894 
0895 /* SSP2 Controller */
0896 #define SSP2_BASE_ADDR      0x400ac000
0897 #define SSP2CR0        (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x00))
0898 #define SSP2CR1        (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x04))
0899 #define SSP2DR         (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x08))
0900 #define SSP2SR         (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x0C))
0901 #define SSP2CPSR       (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x10))
0902 #define SSP2IMSC       (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x14))
0903 #define SSP2RIS        (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x18))
0904 #define SSP2MIS        (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x1C))
0905 #define SSP2ICR        (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x20))
0906 #define SSP2DMACR      (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x24))
0907 
0908 #endif /* ARM_MULTILIB_ARCH_V4 */
0909 
0910 /* Real Time Clock */
0911 #ifdef ARM_MULTILIB_ARCH_V4
0912   #define RTC_BASE_ADDR     0xE0024000
0913 #else
0914   #define RTC_BASE_ADDR     0x40024000
0915 #endif
0916 #define RTC_ILR         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x00))
0917 #define RTC_CTC         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x04))
0918 #define RTC_CCR         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x08))
0919 #define RTC_CIIR        (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x0C))
0920 #define RTC_AMR         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x10))
0921 #define RTC_CTIME0      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x14))
0922 #define RTC_CTIME1      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x18))
0923 #define RTC_CTIME2      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x1C))
0924 #define RTC_SEC         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x20))
0925 #define RTC_MIN         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x24))
0926 #define RTC_HOUR        (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x28))
0927 #define RTC_DOM         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x2C))
0928 #define RTC_DOW         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x30))
0929 #define RTC_DOY         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x34))
0930 #define RTC_MONTH       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x38))
0931 #define RTC_YEAR        (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x3C))
0932 #define RTC_CISS        (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x40))
0933 #define RTC_ALSEC       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x60))
0934 #define RTC_ALMIN       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x64))
0935 #define RTC_ALHOUR      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x68))
0936 #define RTC_ALDOM       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x6C))
0937 #define RTC_ALDOW       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x70))
0938 #define RTC_ALDOY       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x74))
0939 #define RTC_ALMON       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x78))
0940 #define RTC_ALYEAR      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x7C))
0941 #define RTC_PREINT      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x80))
0942 #define RTC_PREFRAC     (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x84))
0943 
0944 
0945 /* A/D Converter 0 (AD0) */
0946 #ifdef ARM_MULTILIB_ARCH_V4
0947   #define AD0_BASE_ADDR     0xE0034000
0948 #else
0949   #define AD0_BASE_ADDR     0x40034000
0950 #endif
0951 #define AD0CR          (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x00))
0952 #define AD0GDR         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x04))
0953 #define AD0INTEN       (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x0C))
0954 #define AD0_DATA_START ((volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
0955 #define AD0DR0         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
0956 #define AD0DR1         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x14))
0957 #define AD0DR2         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x18))
0958 #define AD0DR3         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x1C))
0959 #define AD0DR4         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x20))
0960 #define AD0DR5         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x24))
0961 #define AD0DR6         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x28))
0962 #define AD0DR7         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x2C))
0963 #define AD0STAT        (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x30))
0964 
0965 
0966 /* D/A Converter */
0967 #ifdef ARM_MULTILIB_ARCH_V4
0968   #define DAC_BASE_ADDR     0xE006C000
0969 #else
0970   #define DAC_BASE_ADDR     0x4008C000
0971 #endif
0972 #define DACR           (*(volatile uint32_t *) (DAC_BASE_ADDR + 0x00))
0973 
0974 
0975 /* Watchdog */
0976 #ifdef ARM_MULTILIB_ARCH_V4
0977   #define WDG_BASE_ADDR     0xE0000000
0978 #else
0979   #define WDG_BASE_ADDR     0x40000000
0980 #endif
0981 #define WDMOD          (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x00))
0982 #define WDTC           (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x04))
0983 #define WDFEED         (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x08))
0984 #define WDTV           (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x0C))
0985 #define WDCLKSEL       (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x10))
0986 
0987 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
0988 #ifdef ARM_MULTILIB_ARCH_V4
0989   #define CAN_ACCEPT_BASE_ADDR      0xE003C000
0990 #else
0991   #define CAN_ACCEPT_BASE_ADDR      0x4003C000
0992 #endif
0993 #define CAN_AFMR        (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x00))
0994 #define CAN_SFF_SA      (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x04))
0995 #define CAN_SFF_GRP_SA  (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x08))
0996 #define CAN_EFF_SA      (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x0C))
0997 #define CAN_EFF_GRP_SA  (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x10))
0998 #define CAN_EOT         (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x14))
0999 #define CAN_LUT_ERR_ADR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x18))
1000 #define CAN_LUT_ERR     (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x1C))
1001 
1002 #ifdef ARM_MULTILIB_ARCH_V4
1003   #define CAN_CENTRAL_BASE_ADDR     0xE0040000
1004 #else
1005   #define CAN_CENTRAL_BASE_ADDR     0x40040000
1006 #endif
1007 #define CAN_TX_SR   (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x00))
1008 #define CAN_RX_SR   (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x04))
1009 #define CAN_MSR     (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x08))
1010 
1011 #ifdef ARM_MULTILIB_ARCH_V4
1012   #define CAN1_BASE_ADDR        0xE0044000
1013 #else
1014   #define CAN1_BASE_ADDR        0x40044000
1015 #endif
1016 #define CAN1MOD     (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x00))
1017 #define CAN1CMR     (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x04))
1018 #define CAN1GSR     (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x08))
1019 #define CAN1ICR     (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x0C))
1020 #define CAN1IER     (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x10))
1021 #define CAN1BTR     (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x14))
1022 #define CAN1EWL     (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x18))
1023 #define CAN1SR      (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x1C))
1024 #define CAN1RFS     (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x20))
1025 #define CAN1RID     (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x24))
1026 #define CAN1RDA     (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x28))
1027 #define CAN1RDB     (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x2C))
1028 
1029 #define CAN1TFI1    (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x30))
1030 #define CAN1TID1    (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x34))
1031 #define CAN1TDA1    (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x38))
1032 #define CAN1TDB1    (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x3C))
1033 #define CAN1TFI2    (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x40))
1034 #define CAN1TID2    (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x44))
1035 #define CAN1TDA2    (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x48))
1036 #define CAN1TDB2    (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x4C))
1037 #define CAN1TFI3    (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x50))
1038 #define CAN1TID3    (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x54))
1039 #define CAN1TDA3    (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x58))
1040 #define CAN1TDB3    (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x5C))
1041 
1042 #ifdef ARM_MULTILIB_ARCH_V4
1043   #define CAN2_BASE_ADDR        0xE0048000
1044 #else
1045   #define CAN2_BASE_ADDR        0x40048000
1046 #endif
1047 #define CAN2MOD     (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x00))
1048 #define CAN2CMR     (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x04))
1049 #define CAN2GSR     (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x08))
1050 #define CAN2ICR     (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x0C))
1051 #define CAN2IER     (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x10))
1052 #define CAN2BTR     (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x14))
1053 #define CAN2EWL     (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x18))
1054 #define CAN2SR      (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x1C))
1055 #define CAN2RFS     (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x20))
1056 #define CAN2RID     (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x24))
1057 #define CAN2RDA     (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x28))
1058 #define CAN2RDB     (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x2C))
1059 
1060 #define CAN2TFI1    (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x30))
1061 #define CAN2TID1    (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x34))
1062 #define CAN2TDA1    (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x38))
1063 #define CAN2TDB1    (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x3C))
1064 #define CAN2TFI2    (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x40))
1065 #define CAN2TID2    (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x44))
1066 #define CAN2TDA2    (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x48))
1067 #define CAN2TDB2    (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x4C))
1068 #define CAN2TFI3    (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x50))
1069 #define CAN2TID3    (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x54))
1070 #define CAN2TDA3    (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x58))
1071 #define CAN2TDB3    (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x5C))
1072 
1073 
1074 /* MultiMedia Card Interface(MCI) Controller */
1075 #ifdef ARM_MULTILIB_ARCH_V4
1076   #define MCI_BASE_ADDR     0xE008C000
1077 #else
1078   #define MCI_BASE_ADDR     0x400c0000
1079 #endif
1080 #define MCI_POWER      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x00))
1081 #define MCI_CLOCK      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x04))
1082 #define MCI_ARGUMENT   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x08))
1083 #define MCI_COMMAND    (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x0C))
1084 #define MCI_RESP_CMD   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x10))
1085 #define MCI_RESP0      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x14))
1086 #define MCI_RESP1      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x18))
1087 #define MCI_RESP2      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x1C))
1088 #define MCI_RESP3      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x20))
1089 #define MCI_DATA_TMR   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x24))
1090 #define MCI_DATA_LEN   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x28))
1091 #define MCI_DATA_CTRL  (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x2C))
1092 #define MCI_DATA_CNT   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x30))
1093 #define MCI_STATUS     (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x34))
1094 #define MCI_CLEAR      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x38))
1095 #define MCI_MASK0      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x3C))
1096 #define MCI_MASK1      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x40))
1097 #define MCI_FIFO_CNT   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x48))
1098 #define MCI_FIFO       (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x80))
1099 
1100 
1101 /* I2S Interface Controller (I2S) */
1102 #ifdef ARM_MULTILIB_ARCH_V4
1103   #define I2S_BASE_ADDR     0xE0088000
1104 #else
1105   #define I2S_BASE_ADDR     0x400a8000
1106 #endif
1107 #define I2S_DAO        (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x00))
1108 #define I2S_DAI        (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x04))
1109 #define I2S_TX_FIFO    (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x08))
1110 #define I2S_RX_FIFO    (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x0C))
1111 #define I2S_STATE      (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x10))
1112 #define I2S_DMA1       (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x14))
1113 #define I2S_DMA2       (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x18))
1114 #define I2S_IRQ        (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x1C))
1115 #define I2S_TXRATE     (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x20))
1116 #define I2S_RXRATE     (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x24))
1117 
1118 
1119 /* General-purpose DMA Controller */
1120 #ifdef ARM_MULTILIB_ARCH_V4
1121   #define DMA_BASE_ADDR     0xFFE04000
1122 #else
1123   #define DMA_BASE_ADDR     0x20080000
1124 #endif
1125 #define GPDMA_INT_STAT         (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x000))
1126 #define GPDMA_INT_TCSTAT       (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x004))
1127 #define GPDMA_INT_TCCLR        (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x008))
1128 #define GPDMA_INT_ERR_STAT     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x00C))
1129 #define GPDMA_INT_ERR_CLR      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x010))
1130 #define GPDMA_RAW_INT_TCSTAT   (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x014))
1131 #define GPDMA_RAW_INT_ERR_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x018))
1132 #define GPDMA_ENABLED_CHNS     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x01C))
1133 #define GPDMA_SOFT_BREQ        (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x020))
1134 #define GPDMA_SOFT_SREQ        (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x024))
1135 #define GPDMA_SOFT_LBREQ       (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x028))
1136 #define GPDMA_SOFT_LSREQ       (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x02C))
1137 #define GPDMA_CONFIG           (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x030))
1138 #define GPDMA_SYNC             (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x034))
1139 
1140 /* DMA channel 0 registers */
1141 #define GPDMA_CH0_BASE_ADDR (DMA_BASE_ADDR + 0x100)
1142 #define GPDMA_CH0_SRC      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x100))
1143 #define GPDMA_CH0_DEST     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x104))
1144 #define GPDMA_CH0_LLI      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x108))
1145 #define GPDMA_CH0_CTRL     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x10C))
1146 #define GPDMA_CH0_CFG      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x110))
1147 
1148 /* DMA channel 1 registers */
1149 #define GPDMA_CH1_BASE_ADDR (DMA_BASE_ADDR + 0x120)
1150 #define GPDMA_CH1_SRC      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x120))
1151 #define GPDMA_CH1_DEST     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x124))
1152 #define GPDMA_CH1_LLI      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x128))
1153 #define GPDMA_CH1_CTRL     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x12C))
1154 #define GPDMA_CH1_CFG      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x130))
1155 
1156 /* USB Controller */
1157 #ifdef ARM_MULTILIB_ARCH_V4
1158   #define USB_INT_BASE_ADDR 0xE01FC1C0
1159   #define USB_BASE_ADDR     0xFFE0C200      /* USB Base Address */
1160 #else
1161   #define USB_INT_BASE_ADDR 0x400fc1c0
1162   #define USB_BASE_ADDR     0x2008c200
1163 #endif
1164 
1165 #define USB_INT_STAT    (*(volatile uint32_t *) (USB_INT_BASE_ADDR + 0x00))
1166 
1167 /* USB Device Interrupt Registers */
1168 #define DEV_INT_STAT    (*(volatile uint32_t *) (USB_BASE_ADDR + 0x00))
1169 #define DEV_INT_EN      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x04))
1170 #define DEV_INT_CLR     (*(volatile uint32_t *) (USB_BASE_ADDR + 0x08))
1171 #define DEV_INT_SET     (*(volatile uint32_t *) (USB_BASE_ADDR + 0x0C))
1172 #define DEV_INT_PRIO    (*(volatile uint32_t *) (USB_BASE_ADDR + 0x2C))
1173 
1174 /* USB Device Endpoint Interrupt Registers */
1175 #define EP_INT_STAT     (*(volatile uint32_t *) (USB_BASE_ADDR + 0x30))
1176 #define EP_INT_EN       (*(volatile uint32_t *) (USB_BASE_ADDR + 0x34))
1177 #define EP_INT_CLR      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x38))
1178 #define EP_INT_SET      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x3C))
1179 #define EP_INT_PRIO     (*(volatile uint32_t *) (USB_BASE_ADDR + 0x40))
1180 
1181 /* USB Device Endpoint Realization Registers */
1182 #define REALIZE_EP      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x44))
1183 #define EP_INDEX        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x48))
1184 #define MAXPACKET_SIZE  (*(volatile uint32_t *) (USB_BASE_ADDR + 0x4C))
1185 
1186 /* USB Device Command Reagisters */
1187 #define CMD_CODE        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x10))
1188 #define CMD_DATA        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x14))
1189 
1190 /* USB Device Data Transfer Registers */
1191 #define RX_DATA         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x18))
1192 #define TX_DATA         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x1C))
1193 #define RX_PLENGTH      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x20))
1194 #define TX_PLENGTH      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x24))
1195 #define USB_CTRL        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x28))
1196 
1197 /* USB Device DMA Registers */
1198 #define DMA_REQ_STAT        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x50))
1199 #define DMA_REQ_CLR         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x54))
1200 #define DMA_REQ_SET         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x58))
1201 #define UDCA_HEAD           (*(volatile uint32_t *) (USB_BASE_ADDR + 0x80))
1202 #define EP_DMA_STAT         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x84))
1203 #define EP_DMA_EN           (*(volatile uint32_t *) (USB_BASE_ADDR + 0x88))
1204 #define EP_DMA_DIS          (*(volatile uint32_t *) (USB_BASE_ADDR + 0x8C))
1205 #define DMA_INT_STAT        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x90))
1206 #define DMA_INT_EN          (*(volatile uint32_t *) (USB_BASE_ADDR + 0x94))
1207 #define EOT_INT_STAT        (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA0))
1208 #define EOT_INT_CLR         (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA4))
1209 #define EOT_INT_SET         (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA8))
1210 #define NDD_REQ_INT_STAT    (*(volatile uint32_t *) (USB_BASE_ADDR + 0xAC))
1211 #define NDD_REQ_INT_CLR     (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB0))
1212 #define NDD_REQ_INT_SET     (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB4))
1213 #define SYS_ERR_INT_STAT    (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB8))
1214 #define SYS_ERR_INT_CLR     (*(volatile uint32_t *) (USB_BASE_ADDR + 0xBC))
1215 #define SYS_ERR_INT_SET     (*(volatile uint32_t *) (USB_BASE_ADDR + 0xC0))
1216 
1217 /* USB Host Controller */
1218 #ifdef ARM_MULTILIB_ARCH_V4
1219   #define USBHC_BASE_ADDR       0xFFE0C000
1220 #else
1221   #define USBHC_BASE_ADDR       0x2008c000
1222 #endif
1223 #define HC_REVISION         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x00))
1224 #define HC_CONTROL          (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x04))
1225 #define HC_CMD_STAT         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x08))
1226 #define HC_INT_STAT         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x0C))
1227 #define HC_INT_EN           (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x10))
1228 #define HC_INT_DIS          (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x14))
1229 #define HC_HCCA             (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x18))
1230 #define HC_PERIOD_CUR_ED    (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x1C))
1231 #define HC_CTRL_HEAD_ED     (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x20))
1232 #define HC_CTRL_CUR_ED      (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x24))
1233 #define HC_BULK_HEAD_ED     (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x28))
1234 #define HC_BULK_CUR_ED      (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x2C))
1235 #define HC_DONE_HEAD        (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x30))
1236 #define HC_FM_INTERVAL      (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x34))
1237 #define HC_FM_REMAINING     (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x38))
1238 #define HC_FM_NUMBER        (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x3C))
1239 #define HC_PERIOD_START     (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x40))
1240 #define HC_LS_THRHLD        (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x44))
1241 #define HC_RH_DESCA         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x48))
1242 #define HC_RH_DESCB         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x4C))
1243 #define HC_RH_STAT          (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x50))
1244 #define HC_RH_PORT_STAT1    (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x54))
1245 #define HC_RH_PORT_STAT2    (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x58))
1246 
1247 /* USB OTG Controller */
1248 #ifdef ARM_MULTILIB_ARCH_V4
1249   #define USBOTG_BASE_ADDR  0xFFE0C100
1250 #else
1251   #define USBOTG_BASE_ADDR  0x2008c100
1252 #endif
1253 #define OTG_INT_STAT        (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x00))
1254 #define OTG_INT_EN          (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x04))
1255 #define OTG_INT_SET         (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x08))
1256 #define OTG_INT_CLR         (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x0C))
1257 #define OTG_STAT_CTRL       (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x10))
1258 #define OTG_TIMER           (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x14))
1259 
1260 #ifdef ARM_MULTILIB_ARCH_V4
1261   #define USBOTG_I2C_BASE_ADDR  0xFFE0C300
1262 #else
1263   #define USBOTG_I2C_BASE_ADDR  0x2008c300
1264 #endif
1265 #define OTG_I2C_RX          (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
1266 #define OTG_I2C_TX          (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
1267 #define OTG_I2C_STS         (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x04))
1268 #define OTG_I2C_CTL         (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x08))
1269 #define OTG_I2C_CLKHI       (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x0C))
1270 #define OTG_I2C_CLKLO       (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x10))
1271 
1272 #ifdef ARM_MULTILIB_ARCH_V4
1273   #define USBOTG_CLK_BASE_ADDR  0xFFE0CFF0
1274 #else
1275   #define USBOTG_CLK_BASE_ADDR  0x2008cff0
1276 #endif
1277 #define OTG_CLK_CTRL        (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x04))
1278 #define OTG_CLK_STAT        (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x08))
1279 
1280 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
1281 #ifdef ARM_MULTILIB_ARCH_V4
1282   #define MAC_BASE_ADDR     0xFFE00000 /* AHB Peripheral # 0 */
1283 #else
1284   #define MAC_BASE_ADDR     0x20084000
1285 #endif
1286 #define MAC_MAC1            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
1287 #define MAC_MAC2            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
1288 #define MAC_IPGT            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
1289 #define MAC_IPGR            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
1290 #define MAC_CLRT            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
1291 #define MAC_MAXF            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
1292 #define MAC_SUPP            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
1293 #define MAC_TEST            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x01C)) /* TEST reg */
1294 #define MAC_MCFG            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
1295 #define MAC_MCMD            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
1296 #define MAC_MADR            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
1297 #define MAC_MWTD            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
1298 #define MAC_MRDD            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
1299 #define MAC_MIND            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
1300 
1301 #define MAC_SA0             (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
1302 #define MAC_SA1             (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
1303 #define MAC_SA2             (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
1304 
1305 #define MAC_COMMAND         (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x100)) /* Command reg */
1306 #define MAC_STATUS          (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
1307 #define MAC_RXDESCRIPTOR    (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
1308 #define MAC_RXSTATUS        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
1309 #define MAC_RXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
1310 #define MAC_RXPRODUCEINDEX  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
1311 #define MAC_RXCONSUMEINDEX  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
1312 #define MAC_TXDESCRIPTOR    (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
1313 #define MAC_TXSTATUS        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
1314 #define MAC_TXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
1315 #define MAC_TXPRODUCEINDEX  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
1316 #define MAC_TXCONSUMEINDEX  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
1317 
1318 #define MAC_TSV0            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
1319 #define MAC_TSV1            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
1320 #define MAC_RSV             (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
1321 
1322 #define MAC_FLOWCONTROLCNT  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
1323 #define MAC_FLOWCONTROLSTS  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
1324 
1325 #define MAC_RXFILTERCTRL    (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
1326 #define MAC_RXFILTERWOLSTS  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
1327 #define MAC_RXFILTERWOLCLR  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
1328 
1329 #define MAC_HASHFILTERL     (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
1330 #define MAC_HASHFILTERH     (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
1331 
1332 #define MAC_INTSTATUS       (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
1333 #define MAC_INTENABLE       (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg  */
1334 #define MAC_INTCLEAR        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
1335 #define MAC_INTSET          (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
1336 
1337 #define MAC_POWERDOWN       (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
1338 #define MAC_MODULEID        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
1339 
1340 /* LCD Controller */
1341 
1342 #ifdef ARM_MULTILIB_ARCH_V4
1343   #define LCD_CFG     (*(volatile uint32_t *) 0xE01FC1B8)
1344   #define LCD_BASE_ADDR 0xFFE10000
1345 #else
1346   #define LCD_CFG     (*(volatile uint32_t *) 0x400FC1B8)
1347   #define LCD_BASE_ADDR 0x20088000
1348 #endif
1349 #define LCD_TIMH      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x000))
1350 #define LCD_TIMV      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x004))
1351 #define LCD_POL       (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x008))
1352 #define LCD_LE        (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x00C))
1353 #define LCD_UPBASE    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x010))
1354 #define LCD_LPBASE    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x014))
1355 #define LCD_CTRL      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x018))
1356 #define LCD_INTMSK    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x01C))
1357 #define LCD_INTRAW    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x020))
1358 #define LCD_INTSTAT   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x024))
1359 #define LCD_INTCLR    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x028))
1360 #define LCD_UPCURR    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x02C))
1361 #define LCD_LPCURR    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x030))
1362 #define LCD_PAL_ADDR  (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x200))
1363 #define CRSR_IMG      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x800))
1364 #define CRSR_CTLR     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC00))
1365 #define CRSR_CFG      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC04))
1366 #define CRSR_PAL0     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC08))
1367 #define CRSR_PAL1     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC0C))
1368 #define CRSR_XY       (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC10))
1369 #define CRSR_CLIP     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC14))
1370 #define CRSR_INTMSK   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC20))
1371 #define CRSR_INTCLR   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC24))
1372 #define CRSR_INTRAW   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC28))
1373 #define CRSR_INTSTAT  (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC2C))
1374 
1375 /* Register Fields */
1376 
1377 #define GET_FIELD( val, mask, shift) \
1378   (((val) & (mask)) >> (shift))
1379 
1380 #define SET_FIELD( val, field, mask, shift) \
1381   (((val) & ~(mask)) | (((field) << (shift)) & (mask)))
1382 
1383 /* CLKSRCSEL */
1384 
1385 #define CLKSRCSEL_CLKSRC_MASK 0x00000003U
1386 
1387 #define GET_CLKSRCSEL_CLKSRC(reg) \
1388   GET_FIELD(reg, CLKSRCSEL_CLKSRC_MASK, 0)
1389 
1390 #define SET_CLKSRCSEL_CLKSRC(reg, val) \
1391   SET_FIELD(reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
1392 
1393 /* PLLCON */
1394 
1395 #define PLLCON_PLLE 0x00000001U
1396 
1397 #define PLLCON_PLLC 0x00000002U
1398 
1399 /* PLLCFG */
1400 
1401 #define PLLCFG_MSEL_MASK 0x00007fffU
1402 
1403 #define GET_PLLCFG_MSEL(reg) \
1404   GET_FIELD(reg, PLLCFG_MSEL_MASK, 0)
1405 
1406 #define SET_PLLCFG_MSEL(reg, val) \
1407   SET_FIELD(reg, val, PLLCFG_MSEL_MASK, 0)
1408 
1409 #define PLLCFG_NSEL_MASK 0x00ff0000U
1410 
1411 #define GET_PLLCFG_NSEL(reg) \
1412   GET_FIELD(reg, PLLCFG_NSEL_MASK, 16)
1413 
1414 #define SET_PLLCFG_NSEL(reg, val) \
1415   SET_FIELD(reg, val, PLLCFG_NSEL_MASK, 16)
1416 
1417 /* PLLSTAT */
1418 
1419 #define PLLSTAT_MSEL_MASK 0x00007fffU
1420 
1421 #define GET_PLLSTAT_MSEL(reg) \
1422   GET_FIELD(reg, PLLSTAT_MSEL_MASK, 0)
1423 
1424 #define SET_PLLSTAT_MSEL(reg, val) \
1425   SET_FIELD(reg, val, PLLSTAT_MSEL_MASK, 0)
1426 
1427 #define PLLSTAT_NSEL_MASK 0x00ff0000U
1428 
1429 #define GET_PLLSTAT_NSEL(reg) \
1430   GET_FIELD(reg, PLLSTAT_NSEL_MASK, 16)
1431 
1432 #define SET_PLLSTAT_NSEL(reg, val) \
1433   SET_FIELD(reg, val, PLLSTAT_NSEL_MASK, 16)
1434 
1435 #define PLLSTAT_PLLE 0x01000000U
1436 
1437 #define PLLSTAT_PLLC 0x02000000U
1438 
1439 #define PLLSTAT_PLOCK 0x04000000U
1440 
1441 /* CCLKCFG */
1442 
1443 #define CCLKCFG_CCLKSEL_MASK 0x000000ffU
1444 
1445 #define GET_CCLKCFG_CCLKSEL(reg) \
1446   GET_FIELD(reg, CCLKCFG_CCLKSEL_MASK, 0)
1447 
1448 #define SET_CCLKCFG_CCLKSEL(reg, val) \
1449   SET_FIELD(reg, val, CCLKCFG_CCLKSEL_MASK, 0)
1450 
1451 /* MEMMAP */
1452 
1453 #define MEMMAP_MAP_MASK 0x00000003U
1454 
1455 #define GET_MEMMAP_MAP(reg) \
1456   GET_FIELD(reg, MEMMAP_MAP_MASK, 0)
1457 
1458 #define SET_MEMMAP_MAP(reg, val) \
1459   SET_FIELD(reg, val, MEMMAP_MAP_MASK, 0)
1460 
1461 /* TIR */
1462 
1463 #define TIR_MR0 0x00000001U
1464 
1465 #define TIR_MR1 0x00000002U
1466 
1467 #define TIR_MR2 0x00000004U
1468 
1469 #define TIR_MR3 0x00000008U
1470 
1471 #define TIR_CR0 0x00000010U
1472 
1473 #define TIR_CR1 0x00000020U
1474 
1475 #define TIR_CR2 0x00000040U
1476 
1477 #define TIR_CR3 0x00000080U
1478 
1479 /* TCR */
1480 
1481 #define TCR_EN 0x00000001U
1482 
1483 #define TCR_RST 0x00000002U
1484 
1485 /* TMCR */
1486 
1487 #define TMCR_MR0I 0x00000001U
1488 
1489 #define TMCR_MR0R 0x00000002U
1490 
1491 #define TMCR_MR0S 0x00000004U
1492 
1493 #define TMCR_MR1I 0x00000008U
1494 
1495 #define TMCR_MR1R 0x00000010U
1496 
1497 #define TMCR_MR1S 0x00000020U
1498 
1499 #define TMCR_MR2I 0x00000040U
1500 
1501 #define TMCR_MR2R 0x00000080U
1502 
1503 #define TMCR_MR2S 0x00000100U
1504 
1505 #define TMCR_MR3I 0x00000200U
1506 
1507 #define TMCR_MR3R 0x00000400U
1508 
1509 #define TMCR_MR3S 0x00000800U
1510 
1511 /* PCLKSEL0 */
1512 
1513 #define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
1514 
1515 #define GET_PCLKSEL0_PCLK_WDT(reg) \
1516   GET_FIELD(reg, PCLKSEL0_PCLK_WDT_MASK, 0)
1517 
1518 #define SET_PCLKSEL0_PCLK_WDT(reg, val) \
1519   SET_FIELD(reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
1520 
1521 #define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
1522 
1523 #define GET_PCLKSEL0_PCLK_TIMER0(reg) \
1524   GET_FIELD(reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
1525 
1526 #define SET_PCLKSEL0_PCLK_TIMER0(reg, val) \
1527   SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
1528 
1529 #define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
1530 
1531 #define GET_PCLKSEL0_PCLK_TIMER1(reg) \
1532   GET_FIELD(reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
1533 
1534 #define SET_PCLKSEL0_PCLK_TIMER1(reg, val) \
1535   SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
1536 
1537 #define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
1538 
1539 #define GET_PCLKSEL0_PCLK_UART0(reg) \
1540   GET_FIELD(reg, PCLKSEL0_PCLK_UART0_MASK, 6)
1541 
1542 #define SET_PCLKSEL0_PCLK_UART0(reg, val) \
1543   SET_FIELD(reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
1544 
1545 #define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
1546 
1547 #define GET_PCLKSEL0_PCLK_UART1(reg) \
1548   GET_FIELD(reg, PCLKSEL0_PCLK_UART1_MASK, 8)
1549 
1550 #define SET_PCLKSEL0_PCLK_UART1(reg, val) \
1551   SET_FIELD(reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
1552 
1553 #define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
1554 
1555 #define GET_PCLKSEL0_PCLK_PWM0(reg) \
1556   GET_FIELD(reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
1557 
1558 #define SET_PCLKSEL0_PCLK_PWM0(reg, val) \
1559   SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
1560 
1561 #define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
1562 
1563 #define GET_PCLKSEL0_PCLK_PWM1(reg) \
1564   GET_FIELD(reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
1565 
1566 #define SET_PCLKSEL0_PCLK_PWM1(reg, val) \
1567   SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
1568 
1569 #define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
1570 
1571 #define GET_PCLKSEL0_PCLK_I2C0(reg) \
1572   GET_FIELD(reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
1573 
1574 #define SET_PCLKSEL0_PCLK_I2C0(reg, val) \
1575   SET_FIELD(reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
1576 
1577 #define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
1578 
1579 #define GET_PCLKSEL0_PCLK_SPI(reg) \
1580   GET_FIELD(reg, PCLKSEL0_PCLK_SPI_MASK, 16)
1581 
1582 #define SET_PCLKSEL0_PCLK_SPI(reg, val) \
1583   SET_FIELD(reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
1584 
1585 #define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
1586 
1587 #define GET_PCLKSEL0_PCLK_RTC(reg) \
1588   GET_FIELD(reg, PCLKSEL0_PCLK_RTC_MASK, 18)
1589 
1590 #define SET_PCLKSEL0_PCLK_RTC(reg, val) \
1591   SET_FIELD(reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
1592 
1593 #define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
1594 
1595 #define GET_PCLKSEL0_PCLK_SSP1(reg) \
1596   GET_FIELD(reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
1597 
1598 #define SET_PCLKSEL0_PCLK_SSP1(reg, val) \
1599   SET_FIELD(reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
1600 
1601 #define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
1602 
1603 #define GET_PCLKSEL0_PCLK_DAC(reg) \
1604   GET_FIELD(reg, PCLKSEL0_PCLK_DAC_MASK, 22)
1605 
1606 #define SET_PCLKSEL0_PCLK_DAC(reg, val) \
1607   SET_FIELD(reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
1608 
1609 #define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
1610 
1611 #define GET_PCLKSEL0_PCLK_ADC(reg) \
1612   GET_FIELD(reg, PCLKSEL0_PCLK_ADC_MASK, 24)
1613 
1614 #define SET_PCLKSEL0_PCLK_ADC(reg, val) \
1615   SET_FIELD(reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
1616 
1617 #define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
1618 
1619 #define GET_PCLKSEL0_PCLK_CAN1(reg) \
1620   GET_FIELD(reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
1621 
1622 #define SET_PCLKSEL0_PCLK_CAN1(reg, val) \
1623   SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
1624 
1625 #define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
1626 
1627 #define GET_PCLKSEL0_PCLK_CAN2(reg) \
1628   GET_FIELD(reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
1629 
1630 #define SET_PCLKSEL0_PCLK_CAN2(reg, val) \
1631   SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
1632 
1633 /* PCLKSEL1 */
1634 
1635 #define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
1636 
1637 #define GET_PCLKSEL1_PCLK_BAT_RAM(reg) \
1638   GET_FIELD(reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
1639 
1640 #define SET_PCLKSEL1_PCLK_BAT_RAM(reg, val) \
1641   SET_FIELD(reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
1642 
1643 #define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
1644 
1645 #define GET_PCLKSEL1_PCLK_GPIO(reg) \
1646   GET_FIELD(reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
1647 
1648 #define SET_PCLKSEL1_PCLK_GPIO(reg, val) \
1649   SET_FIELD(reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
1650 
1651 #define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
1652 
1653 #define GET_PCLKSEL1_PCLK_PCB(reg) \
1654   GET_FIELD(reg, PCLKSEL1_PCLK_PCB_MASK, 4)
1655 
1656 #define SET_PCLKSEL1_PCLK_PCB(reg, val) \
1657   SET_FIELD(reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
1658 
1659 #define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
1660 
1661 #define GET_PCLKSEL1_PCLK_I2C1(reg) \
1662   GET_FIELD(reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
1663 
1664 #define SET_PCLKSEL1_PCLK_I2C1(reg, val) \
1665   SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
1666 
1667 #define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
1668 
1669 #define GET_PCLKSEL1_PCLK_SSP0(reg) \
1670   GET_FIELD(reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
1671 
1672 #define SET_PCLKSEL1_PCLK_SSP0(reg, val) \
1673   SET_FIELD(reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
1674 
1675 #define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
1676 
1677 #define GET_PCLKSEL1_PCLK_TIMER2(reg) \
1678   GET_FIELD(reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
1679 
1680 #define SET_PCLKSEL1_PCLK_TIMER2(reg, val) \
1681   SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
1682 
1683 #define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
1684 
1685 #define GET_PCLKSEL1_PCLK_TIMER3(reg) \
1686   GET_FIELD(reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
1687 
1688 #define SET_PCLKSEL1_PCLK_TIMER3(reg, val) \
1689   SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
1690 
1691 #define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
1692 
1693 #define GET_PCLKSEL1_PCLK_UART2(reg) \
1694   GET_FIELD(reg, PCLKSEL1_PCLK_UART2_MASK, 16)
1695 
1696 #define SET_PCLKSEL1_PCLK_UART2(reg, val) \
1697   SET_FIELD(reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
1698 
1699 #define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
1700 
1701 #define GET_PCLKSEL1_PCLK_UART3(reg) \
1702   GET_FIELD(reg, PCLKSEL1_PCLK_UART3_MASK, 18)
1703 
1704 #define SET_PCLKSEL1_PCLK_UART3(reg, val) \
1705   SET_FIELD(reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
1706 
1707 #define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
1708 
1709 #define GET_PCLKSEL1_PCLK_I2C2(reg) \
1710   GET_FIELD(reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
1711 
1712 #define SET_PCLKSEL1_PCLK_I2C2(reg, val) \
1713   SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
1714 
1715 #define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
1716 
1717 #define GET_PCLKSEL1_PCLK_I2S(reg) \
1718   GET_FIELD(reg, PCLKSEL1_PCLK_I2S_MASK, 22)
1719 
1720 #define SET_PCLKSEL1_PCLK_I2S(reg, val) \
1721   SET_FIELD(reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
1722 
1723 #define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
1724 
1725 #define GET_PCLKSEL1_PCLK_MCI(reg) \
1726   GET_FIELD(reg, PCLKSEL1_PCLK_MCI_MASK, 24)
1727 
1728 #define SET_PCLKSEL1_PCLK_MCI(reg, val) \
1729   SET_FIELD(reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
1730 
1731 #define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
1732 
1733 #define GET_PCLKSEL1_PCLK_SYSCON(reg) \
1734   GET_FIELD(reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
1735 
1736 #define SET_PCLKSEL1_PCLK_SYSCON(reg, val) \
1737   SET_FIELD(reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
1738 
1739 /* RTC_ILR */
1740 
1741 #define RTC_ILR_RTCCIF 0x00000001U
1742 
1743 #define RTC_ILR_RTCALF 0x00000002U
1744 
1745 #define RTC_ILR_RTSSF 0x00000004U
1746 
1747 /* RTC_CCR */
1748 
1749 #define RTC_CCR_CLKEN 0x00000001U
1750 
1751 #define RTC_CCR_CTCRST 0x00000002U
1752 
1753 #define RTC_CCR_CLKSRC 0x00000010U
1754 
1755 /* SSP */
1756 
1757 typedef struct {
1758   uint32_t cr0;
1759   uint32_t cr1;
1760   uint32_t dr;
1761   uint32_t sr;
1762   uint32_t cpsr;
1763   uint32_t imsc;
1764   uint32_t ris;
1765   uint32_t mis;
1766   uint32_t icr;
1767   uint32_t dmacr;
1768 } lpc24xx_ssp;
1769 
1770 /* SSP_CR0 */
1771 
1772 #define SSP_CR0_DSS_MASK 0x0000000fU
1773 
1774 #define GET_SSP_CR0_DSS(reg) \
1775   GET_FIELD(reg, SSP_CR0_DSS_MASK, 0)
1776 
1777 #define SET_SSP_CR0_DSS(reg, val) \
1778   SET_FIELD(reg, val, SSP_CR0_DSS_MASK, 0)
1779 
1780 #define SSP_CR0_FRF_MASK 0x00000030U
1781 
1782 #define GET_SSP_CR0_FRF(reg) \
1783   GET_FIELD(reg, SSP_CR0_FRF_MASK, 4)
1784 
1785 #define SET_SSP_CR0_FRF(reg, val) \
1786   SET_FIELD(reg, val, SSP_CR0_FRF_MASK, 4)
1787 
1788 #define SSP_CR0_CPOL 0x00000040U
1789 
1790 #define SSP_CR0_CPHA 0x00000080U
1791 
1792 #define SSP_CR0_SCR_MASK 0x0000ff00U
1793 
1794 #define GET_SSP_CR0_SCR(reg) \
1795   GET_FIELD(reg, SSP_CR0_SCR_MASK, 8)
1796 
1797 #define SET_SSP_CR0_SCR(reg, val) \
1798   SET_FIELD(reg, val, SSP_CR0_SCR_MASK, 8)
1799 
1800 /* SSP_CR1 */
1801 
1802 #define SSP_CR1_LBM 0x00000001U
1803 
1804 #define SSP_CR1_SSE 0x00000002U
1805 
1806 #define SSP_CR1_MS 0x00000004U
1807 
1808 #define SSP_CR1_SOD 0x00000008U
1809 
1810 /* SSP_SR */
1811 
1812 #define SSP_SR_TFE 0x00000001U
1813 
1814 #define SSP_SR_TNF 0x00000002U
1815 
1816 #define SSP_SR_RNE 0x00000004U
1817 
1818 #define SSP_SR_RFF 0x00000008U
1819 
1820 #define SSP_SR_BSY 0x00000010U
1821 
1822 /* SSP_IMSC */
1823 
1824 #define SSP_IMSC_RORIM 0x00000001U
1825 
1826 #define SSP_IMSC_RTIM 0x00000002U
1827 
1828 #define SSP_IMSC_RXIM 0x00000004U
1829 
1830 #define SSP_IMSC_TXIM 0x00000008U
1831 
1832 /* SSP_RIS */
1833 
1834 #define SSP_RIS_RORRIS 0x00000001U
1835 
1836 #define SSP_RIS_RTRIS 0x00000002U
1837 
1838 #define SSP_RIS_RXRIS 0x00000004U
1839 
1840 #define SSP_RIS_TXRIS 0x00000008U
1841 
1842 /* SSP_MIS */
1843 
1844 #define SSP_MIS_RORRIS 0x00000001U
1845 
1846 #define SSP_MIS_RTRIS 0x00000002U
1847 
1848 #define SSP_MIS_RXRIS 0x00000004U
1849 
1850 #define SSP_MIS_TXRIS 0x00000008U
1851 
1852 /* SSP_ICR */
1853 
1854 #define SSP_ICR_RORRIS 0x00000001U
1855 
1856 #define SSP_ICR_RTRIS 0x00000002U
1857 
1858 #define SSP_ICR_RXRIS 0x00000004U
1859 
1860 #define SSP_ICR_TXRIS 0x00000008U
1861 
1862 /* SSP_DMACR */
1863 
1864 #define SSP_DMACR_RXDMAE 0x00000001U
1865 
1866 #define SSP_DMACR_TXDMAE 0x00000002U
1867 
1868 /* GPDMA */
1869 
1870 typedef struct {
1871   uint32_t src;
1872   uint32_t dest;
1873   uint32_t lli;
1874   uint32_t ctrl;
1875 } lpc24xx_dma_descriptor;
1876 
1877 typedef struct {
1878   lpc24xx_dma_descriptor desc;
1879   uint32_t cfg;
1880 } lpc24xx_dma_channel;
1881 
1882 #define GPDMA_CH_NUMBER 2
1883 
1884 #define GPDMA_STATUS_CH_0 0x00000001U
1885 
1886 #define GPDMA_STATUS_CH_1 0x00000002U
1887 
1888 #define GPDMA_CH_BASE_ADDR(i) \
1889   ((volatile lpc24xx_dma_channel *) \
1890     ((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR))
1891 
1892 /* GPDMA_CONFIG */
1893 
1894 #define GPDMA_CONFIG_EN 0x00000001U
1895 
1896 #define GPDMA_CONFIG_MODE 0x00000002U
1897 
1898 /* GPDMA_ENABLED_CHNS */
1899 
1900 #define GPDMA_ENABLED_CHNS_CH0 0x00000001U
1901 
1902 #define GPDMA_ENABLED_CHNS_CH1 0x00000002U
1903 
1904 /* GPDMA_CH_CTRL */
1905 
1906 #define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
1907 
1908 #define GET_GPDMA_CH_CTRL_TSZ(reg) \
1909   GET_FIELD(reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
1910 
1911 #define SET_GPDMA_CH_CTRL_TSZ(reg, val) \
1912   SET_FIELD(reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
1913 
1914 #define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
1915 
1916 #define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
1917 
1918 #define GET_GPDMA_CH_CTRL_SBSZ(reg) \
1919   GET_FIELD(reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
1920 
1921 #define SET_GPDMA_CH_CTRL_SBSZ(reg, val) \
1922   SET_FIELD(reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
1923 
1924 #define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
1925 
1926 #define GET_GPDMA_CH_CTRL_DBSZ(reg) \
1927   GET_FIELD(reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
1928 
1929 #define SET_GPDMA_CH_CTRL_DBSZ(reg, val) \
1930   SET_FIELD(reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
1931 
1932 #define GPDMA_CH_CTRL_BSZ_1 0x00000000U
1933 
1934 #define GPDMA_CH_CTRL_BSZ_4 0x00000001U
1935 
1936 #define GPDMA_CH_CTRL_BSZ_8 0x00000002U
1937 
1938 #define GPDMA_CH_CTRL_BSZ_16 0x00000003U
1939 
1940 #define GPDMA_CH_CTRL_BSZ_32 0x00000004U
1941 
1942 #define GPDMA_CH_CTRL_BSZ_64 0x00000005U
1943 
1944 #define GPDMA_CH_CTRL_BSZ_128 0x00000006U
1945 
1946 #define GPDMA_CH_CTRL_BSZ_256 0x00000007U
1947 
1948 #define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
1949 
1950 #define GET_GPDMA_CH_CTRL_SW(reg) \
1951   GET_FIELD(reg, GPDMA_CH_CTRL_SW_MASK, 18)
1952 
1953 #define SET_GPDMA_CH_CTRL_SW(reg, val) \
1954   SET_FIELD(reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
1955 
1956 #define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
1957 
1958 #define GET_GPDMA_CH_CTRL_DW(reg) \
1959   GET_FIELD(reg, GPDMA_CH_CTRL_DW_MASK, 21)
1960 
1961 #define SET_GPDMA_CH_CTRL_DW(reg, val) \
1962   SET_FIELD(reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
1963 
1964 #define GPDMA_CH_CTRL_W_8 0x00000000U
1965 
1966 #define GPDMA_CH_CTRL_W_16 0x00000001U
1967 
1968 #define GPDMA_CH_CTRL_W_32 0x00000002U
1969 
1970 #define GPDMA_CH_CTRL_SI 0x04000000U
1971 
1972 #define GPDMA_CH_CTRL_DI 0x08000000U
1973 
1974 #define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
1975 
1976 #define GET_GPDMA_CH_CTRL_PROT(reg) \
1977   GET_FIELD(reg, GPDMA_CH_CTRL_PROT_MASK, 28)
1978 
1979 #define SET_GPDMA_CH_CTRL_PROT(reg, val) \
1980   SET_FIELD(reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
1981 
1982 #define GPDMA_CH_CTRL_ITC 0x80000000U
1983 
1984 /* GPDMA_CH_CFG */
1985 
1986 #define GPDMA_CH_CFG_EN 0x00000001U
1987 
1988 #define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
1989 
1990 #define GET_GPDMA_CH_CFG_SRCPER(reg) \
1991   GET_FIELD(reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
1992 
1993 #define SET_GPDMA_CH_CFG_SRCPER(reg, val) \
1994   SET_FIELD(reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
1995 
1996 #define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
1997 
1998 #define GET_GPDMA_CH_CFG_DESTPER(reg) \
1999   GET_FIELD(reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
2000 
2001 #define SET_GPDMA_CH_CFG_DESTPER(reg, val) \
2002   SET_FIELD(reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
2003 
2004 #define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
2005 
2006 #define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U
2007 
2008 #define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U
2009 
2010 #define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U
2011 
2012 #define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U
2013 
2014 #define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U
2015 
2016 #define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U
2017 
2018 #define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
2019 
2020 #define GET_GPDMA_CH_CFG_FLOW(reg) \
2021   GET_FIELD(reg, GPDMA_CH_CFG_FLOW_MASK, 11)
2022 
2023 #define SET_GPDMA_CH_CFG_FLOW(reg, val) \
2024   SET_FIELD(reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
2025 
2026 #define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
2027 
2028 #define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U
2029 
2030 #define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U
2031 
2032 #define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U
2033 
2034 #define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U
2035 
2036 #define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U
2037 
2038 #define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U
2039 
2040 #define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U
2041 
2042 #define GPDMA_CH_CFG_IE 0x00004000U
2043 
2044 #define GPDMA_CH_CFG_ITC 0x00008000U
2045 
2046 #define GPDMA_CH_CFG_LOCK 0x00010000U
2047 
2048 #define GPDMA_CH_CFG_ACTIVE 0x00020000U
2049 
2050 #define GPDMA_CH_CFG_HALT 0x00040000U
2051 
2052 /* AHBCFG */
2053 
2054 #define AHBCFG_SCHEDULER_UNIFORM 0x00000001U
2055 
2056 #define AHBCFG_BREAK_BURST_MASK 0x00000006U
2057 
2058 #define GET_AHBCFG_BREAK_BURST(reg) \
2059   GET_FIELD(reg, AHBCFG_BREAK_BURST_MASK, 1)
2060 
2061 #define SET_AHBCFG_BREAK_BURST(reg, val) \
2062   SET_FIELD(reg, val, AHBCFG_BREAK_BURST_MASK, 1)
2063 
2064 #define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
2065 
2066 #define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
2067 
2068 #define GET_AHBCFG_QUANTUM_SIZE(reg) \
2069   GET_FIELD(reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
2070 
2071 #define SET_AHBCFG_QUANTUM_SIZE(reg, val) \
2072   SET_FIELD(reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
2073 
2074 #define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
2075 
2076 #define GET_AHBCFG_DEFAULT_MASTER(reg) \
2077   GET_FIELD(reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
2078 
2079 #define SET_AHBCFG_DEFAULT_MASTER(reg, val) \
2080   SET_FIELD(reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
2081 
2082 #define AHBCFG_EP1_MASK 0x00007000U
2083 
2084 #define GET_AHBCFG_EP1(reg) \
2085   GET_FIELD(reg, AHBCFG_EP1_MASK, 12)
2086 
2087 #define SET_AHBCFG_EP1(reg, val) \
2088   SET_FIELD(reg, val, AHBCFG_EP1_MASK, 12)
2089 
2090 #define AHBCFG_EP2_MASK 0x00070000U
2091 
2092 #define GET_AHBCFG_EP2(reg) \
2093   GET_FIELD(reg, AHBCFG_EP2_MASK, 16)
2094 
2095 #define SET_AHBCFG_EP2(reg, val) \
2096   SET_FIELD(reg, val, AHBCFG_EP2_MASK, 16)
2097 
2098 #define AHBCFG_EP3_MASK 0x00700000U
2099 
2100 #define GET_AHBCFG_EP3(reg) \
2101   GET_FIELD(reg, AHBCFG_EP3_MASK, 20)
2102 
2103 #define SET_AHBCFG_EP3(reg, val) \
2104   SET_FIELD(reg, val, AHBCFG_EP3_MASK, 20)
2105 
2106 #define AHBCFG_EP4_MASK 0x07000000U
2107 
2108 #define GET_AHBCFG_EP4(reg) \
2109   GET_FIELD(reg, AHBCFG_EP4_MASK, 24)
2110 
2111 #define SET_AHBCFG_EP4(reg, val) \
2112   SET_FIELD(reg, val, AHBCFG_EP4_MASK, 24)
2113 
2114 #define AHBCFG_EP5_MASK 0x70000000U
2115 
2116 #define GET_AHBCFG_EP5(reg) \
2117   GET_FIELD(reg, AHBCFG_EP5_MASK, 28)
2118 
2119 #define SET_AHBCFG_EP5(reg, val) \
2120   SET_FIELD(reg, val, AHBCFG_EP5_MASK, 28)
2121 
2122 /* I2C */
2123 
2124 typedef struct {
2125   uint32_t conset;
2126   uint32_t stat;
2127   uint32_t dat;
2128   uint32_t adr;
2129   uint32_t sclh;
2130   uint32_t scll;
2131   uint32_t conclr;
2132 } lpc24xx_i2c;
2133 
2134 #define LPC24XX_I2C_AA (1U << 2U)
2135 
2136 #define LPC24XX_I2C_SI (1U << 3U)
2137 
2138 #define LPC24XX_I2C_STO (1U << 4U)
2139 
2140 #define LPC24XX_I2C_STA (1U << 5U)
2141 
2142 #define LPC24XX_I2C_EN (1U << 6U)
2143 
2144 /* IO */
2145 
2146 #ifdef ARM_MULTILIB_ARCH_V4
2147   #define LPC24XX_PINSEL ((volatile uint32_t *) &PINSEL0)
2148   #define LPC24XX_PINMODE ((volatile uint32_t *) &PINMODE0)
2149 #else
2150   #define IOCON_FUNC(val) BSP_FLD32(val, 0, 2)
2151   #define IOCON_FUNC_GET(reg) BSP_FLD32GET(reg, 0, 2)
2152   #define IOCON_FUNC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
2153   #define IOCON_MODE(val) BSP_FLD32(val, 3, 4)
2154   #define IOCON_MODE_GET(reg) BSP_FLD32GET(reg, 3, 4)
2155   #define IOCON_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 3, 4)
2156   #define IOCON_HYS BSP_BIT32(5)
2157   #define IOCON_INV BSP_BIT32(6)
2158   #define IOCON_ADMODE BSP_BIT32(7)
2159   #define IOCON_FILTER BSP_BIT32(8)
2160   #define IOCON_HS BSP_BIT32(8)
2161   #define IOCON_SLEW BSP_BIT32(9)
2162   #define IOCON_HIDRIVE BSP_BIT32(9)
2163   #define IOCON_OD BSP_BIT32(10)
2164   #define IOCON_DACEN BSP_BIT32(16)
2165   #define LPC17XX_IOCON ((volatile uint32_t *) PINSEL_BASE_ADDR)
2166 #endif
2167 
2168 typedef struct {
2169   uint32_t dir;
2170   uint32_t reserved [3];
2171   uint32_t mask;
2172   uint32_t pin;
2173   uint32_t set;
2174   uint32_t clr;
2175 } lpc24xx_fio;
2176 
2177 #define LPC24XX_FIO ((volatile lpc24xx_fio *) FIO_BASE_ADDR)
2178 
2179 #ifdef ARM_MULTILIB_ARCH_V4
2180 
2181 /* PCONP */
2182 
2183 #define PCONP_GPDMA (1U << 29)
2184 #define PCONP_ETHERNET (1U << 30)
2185 #define PCONP_USB (1U << 31)
2186 
2187 #endif /* ARM_MULTILIB_ARCH_V4 */
2188 
2189 /* I2S */
2190 
2191 static volatile lpc_i2s *const lpc24xx_i2s = (lpc_i2s *) I2S_BASE_ADDR;
2192 
2193 /* ADC */
2194 
2195 #define ADC_CR_SEL(val) BSP_FLD32(val, 0, 7)
2196 #define ADC_CR_SEL_GET(val) BSP_FLD32GET(val, 0, 7)
2197 #define ADC_CR_SEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
2198 #define ADC_CR_CLKDIV(val) BSP_FLD32(val, 8, 15)
2199 #define ADC_CR_CLKDIV_GET(reg) BSP_FLD32GET(reg, 8, 15)
2200 #define ADC_CR_CLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
2201 #define ADC_CR_BURST BSP_BIT32(16)
2202 #define ADC_CR_CLKS(val) BSP_FLD32(val, 17, 19)
2203 #define ADC_CR_PDN BSP_BIT32(21)
2204 #define ADC_CR_START(val) BSP_FLD32(val, 24, 26)
2205 #define ADC_CR_EDGE BSP_BIT32(27)
2206 
2207 #define ADC_DR_VALUE(reg) BSP_FLD32GET(reg, 6, 15)
2208 #define ADC_DR_OVERRUN BSP_BIT32(30)
2209 #define ADC_DR_DONE BSP_BIT32(31)
2210 
2211 /* DAC */
2212 
2213 #define DAC_STEPS 1024
2214 #define DAC_VALUE(val) BSP_FLD32(val, 6, 15)
2215 #define DAC_BIAS BSP_BIT32(16)
2216 
2217 /** @} */
2218 
2219 #endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */
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