include/bsp/lpc17xx.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMLPC24XX_regs
0007  *
0008  * @brief Register definitions.
0009  */
0010
0011 /*
0012  * Copyright (c) 2011 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LPC17XX_REGS_H
0037 #define LPC17XX_REGS_H
0038
0039 #include <bsp/utility.h>
0040
0041 #define LPC17XX_BASE 0x00
0042
0043 typedef struct {
0044 #define LPC17XX_WWDT_MOD_WDEN BSP_BIT32(0)
0045 #define LPC17XX_WWDT_MOD_WDRESET BSP_BIT32(1)
0046 #define LPC17XX_WWDT_MOD_WDTOF BSP_BIT32(2)
0047 #define LPC17XX_WWDT_MOD_WDINT BSP_BIT32(3)
0048 #define LPC17XX_WWDT_MOD_WDPROTECT BSP_BIT32(4)
0049     uint32_t mod;
0050     uint32_t tc;
0051     uint32_t feed;
0052     uint32_t tv;
0053     uint32_t reserved_10;
0054     uint32_t warnint;
0055     uint32_t window;
0056     uint32_t reserved_1c;
0057 } lpc17xx_wwdt;
0058
0059 #define LPC17XX_WWDT (*(volatile lpc17xx_wwdt *) (LPC17XX_BASE + 0x40000000))
0060
0061 typedef struct {
0062 #define LPC17XX_PLL_CON_PLLE BSP_BIT32(0)
0063 #define LPC17XX_PLL_SEL_MSEL(val) BSP_FLD32(val, 0, 4)
0064 #define LPC17XX_PLL_SEL_MSEL_GET(reg) BSP_FLD32GET(reg, 0, 4)
0065 #define LPC17XX_PLL_SEL_MSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
0066 #define LPC17XX_PLL_SEL_PSEL(val) BSP_FLD32(val, 5, 6)
0067 #define LPC17XX_PLL_SEL_PSEL_GET(reg) BSP_FLD32GET(reg, 5, 6)
0068 #define LPC17XX_PLL_SEL_PSEL_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6)
0069 #define LPC17XX_PLL_STAT_PLLE BSP_BIT32(8)
0070 #define LPC17XX_PLL_STAT_PLOCK BSP_BIT32(10)
0071     uint32_t con;
0072     uint32_t cfg;
0073     uint32_t stat;
0074     uint32_t feed;
0075 } lpc17xx_pll;
0076
0077 typedef struct {
0078     uint32_t flashcfg;
0079 #define LPC17XX_SCB_FLASHCFG_FLASHTIM(val) BSP_FLD32(val, 12, 15)
0080 #define LPC17XX_SCB_FLASHCFG_FLASHTIM_GET(reg) BSP_FLD32GET(reg, 12, 15)
0081 #define LPC17XX_SCB_FLASHCFG_FLASHTIM_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
0082     uint32_t reserved_04 [15];
0083     uint32_t memmap;
0084 #define LPC17XX_SCB_MEMMAP_MAP BSP_BIT32(0)
0085     uint32_t reserved_44 [15];
0086     lpc17xx_pll pll_0;
0087     uint32_t reserved_90 [4];
0088     lpc17xx_pll pll_1;
0089     uint32_t reserved_b0 [4];
0090     uint32_t pcon;
0091 #define LPC17XX_SCB_PCON_PM0 BSP_BIT32(0)
0092 #define LPC17XX_SCB_PCON_PM1 BSP_BIT32(1)
0093 #define LPC17XX_SCB_PCON_BODRPM BSP_BIT32(2)
0094 #define LPC17XX_SCB_PCON_BOGD BSP_BIT32(3)
0095 #define LPC17XX_SCB_PCON_BORD BSP_BIT32(4)
0096 #define LPC17XX_SCB_PCON_SMFLAG BSP_BIT32(8)
0097 #define LPC17XX_SCB_PCON_DSFLAG BSP_BIT32(9)
0098 #define LPC17XX_SCB_PCON_PDFLAG BSP_BIT32(10)
0099 #define LPC17XX_SCB_PCON_DPDFLAG BSP_BIT32(11)
0100     uint32_t pconp;
0101 #define LPC17XX_SCB_PCONP_LCD BSP_BIT32(0)
0102 #define LPC17XX_SCB_PCONP_TIMER_0 BSP_BIT32(1)
0103 #define LPC17XX_SCB_PCONP_TIMER_1 BSP_BIT32(2)
0104 #define LPC17XX_SCB_PCONP_UART_0 BSP_BIT32(3)
0105 #define LPC17XX_SCB_PCONP_UART_1 BSP_BIT32(4)
0106 #define LPC17XX_SCB_PCONP_PWM_0 BSP_BIT32(5)
0107 #define LPC17XX_SCB_PCONP_PWM_1 BSP_BIT32(6)
0108 #define LPC17XX_SCB_PCONP_I2C_0 BSP_BIT32(7)
0109 #define LPC17XX_SCB_PCONP_UART_4 BSP_BIT32(8)
0110 #define LPC17XX_SCB_PCONP_RTC BSP_BIT32(9)
0111 #define LPC17XX_SCB_PCONP_SSP_1 BSP_BIT32(10)
0112 #define LPC17XX_SCB_PCONP_EMC BSP_BIT32(11)
0113 #define LPC17XX_SCB_PCONP_ADC BSP_BIT32(12)
0114 #define LPC17XX_SCB_PCONP_CAN_0 BSP_BIT32(13)
0115 #define LPC17XX_SCB_PCONP_CAN_1 BSP_BIT32(14)
0116 #define LPC17XX_SCB_PCONP_GPIO BSP_BIT32(15)
0117 #define LPC17XX_SCB_PCONP_QEI BSP_BIT32(17)
0118 #define LPC17XX_SCB_PCONP_I2C_1 BSP_BIT32(18)
0119 #define LPC17XX_SCB_PCONP_SSP_2 BSP_BIT32(19)
0120 #define LPC17XX_SCB_PCONP_SSP_0 BSP_BIT32(20)
0121 #define LPC17XX_SCB_PCONP_TIMER_2 BSP_BIT32(21)
0122 #define LPC17XX_SCB_PCONP_TIMER_3 BSP_BIT32(22)
0123 #define LPC17XX_SCB_PCONP_UART_2 BSP_BIT32(23)
0124 #define LPC17XX_SCB_PCONP_UART_3 BSP_BIT32(24)
0125 #define LPC17XX_SCB_PCONP_I2C_2 BSP_BIT32(25)
0126 #define LPC17XX_SCB_PCONP_I2S BSP_BIT32(26)
0127 #define LPC17XX_SCB_PCONP_SDC BSP_BIT32(27)
0128 #define LPC17XX_SCB_PCONP_GPDMA BSP_BIT32(28)
0129 #define LPC17XX_SCB_PCONP_ENET BSP_BIT32(29)
0130 #define LPC17XX_SCB_PCONP_USB BSP_BIT32(30)
0131 #define LPC17XX_SCB_PCONP_MCPWM BSP_BIT32(31)
0132     uint32_t reserved_c8 [14];
0133     uint32_t emcclksel;
0134 #define LPC17XX_SCB_EMCCLKSEL_EMCDIV BSP_BIT32(0)
0135     uint32_t cclksel;
0136 #define LPC17XX_SCB_CCLKSEL_CCLKDIV(val) BSP_FLD32(val, 0, 4)
0137 #define LPC17XX_SCB_CCLKSEL_CCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
0138 #define LPC17XX_SCB_CCLKSEL_CCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
0139 #define LPC17XX_SCB_CCLKSEL_CCLKSEL BSP_BIT32(8)
0140     uint32_t usbclksel;
0141 #define LPC17XX_SCB_USBCLKSEL_USBDIV(val) BSP_FLD32(val, 0, 4)
0142 #define LPC17XX_SCB_USBCLKSEL_USBDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
0143 #define LPC17XX_SCB_USBCLKSEL_USBDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
0144 #define LPC17XX_SCB_USBCLKSEL_USBSEL(val) BSP_FLD32(val, 8, 9)
0145 #define LPC17XX_SCB_USBCLKSEL_USBSEL_GET(reg) BSP_FLD32GET(reg, 8, 9)
0146 #define LPC17XX_SCB_USBCLKSEL_USBSEL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
0147     uint32_t clksrcsel;
0148 #define LPC17XX_SCB_CLKSRCSEL_CLKSRC BSP_BIT32(0)
0149     uint32_t reserved_110 [12];
0150     uint32_t extint;
0151     uint32_t reserved_144;
0152     uint32_t extmode;
0153     uint32_t extpolar;
0154     uint32_t reserved_150 [12];
0155     uint32_t rsid;
0156     uint32_t reserved_184 [1];
0157     uint32_t matrixarb;
0158     uint32_t reserved_18c [5];
0159     uint32_t scs;
0160 #define LPC17XX_SCB_SCS_EMC_SHIFT_CTL BSP_BIT32(0)
0161 #define LPC17XX_SCB_SCS_EMC_RESET_DIS BSP_BIT32(1)
0162 #define LPC17XX_SCB_SCS_EMC_BURST_CTL BSP_BIT32(2)
0163 #define LPC17XX_SCB_SCS_MCIPWR BSP_BIT32(3)
0164 #define LPC17XX_SCB_SCS_OSC_RANGE_SEL BSP_BIT32(4)
0165 #define LPC17XX_SCB_SCS_OSC_ENABLE BSP_BIT32(5)
0166 #define LPC17XX_SCB_SCS_OSC_STATUS BSP_BIT32(6)
0167     uint32_t reserved_1a4;
0168     uint32_t pclksel;
0169 #define LPC17XX_SCB_PCLKSEL_PCLKDIV(val) BSP_FLD32(val, 0, 4)
0170 #define LPC17XX_SCB_PCLKSEL_PCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
0171 #define LPC17XX_SCB_PCLKSEL_PCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
0172     uint32_t reserved_1ac;
0173     uint32_t pboost;
0174 #define LPC17XX_SCB_PBOOST_BOOST BSP_BIT32(0)
0175     uint32_t reserved_1b4 [5];
0176     uint32_t clkoutcfg;
0177 #define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL(val) BSP_FLD32(val, 3, 0)
0178 #define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_GET(reg) BSP_FLD32GET(reg, 3, 0)
0179 #define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 0)
0180 #define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV(val) BSP_FLD32(val, 7, 4)
0181 #define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_GET(reg) BSP_FLD32GET(reg, 7, 4)
0182 #define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_SET(reg, val) BSP_FLD32SET(reg, val, 7, 4)
0183 #define LPC17XX_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32(8)
0184 #define LPC17XX_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32(9)
0185     uint32_t rstcon0;
0186     uint32_t rstcon1;
0187     uint32_t reserved_1d4 [2];
0188     uint32_t emcdlyctl;
0189 #define LPC17XX_SCB_EMCDLYCTL_CMDDLY(val) BSP_FLD32(val, 0, 4)
0190 #define LPC17XX_SCB_EMCDLYCTL_CMDDLY_GET(reg) BSP_FLD32GET(reg, 0, 4)
0191 #define LPC17XX_SCB_EMCDLYCTL_CMDDLY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
0192 #define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY(val) BSP_FLD32(val, 8, 12)
0193 #define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_GET(reg) BSP_FLD32GET(reg, 8, 12)
0194 #define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 12)
0195 #define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY(val) BSP_FLD32(val, 16, 20)
0196 #define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_GET(reg) BSP_FLD32GET(reg, 16, 20)
0197 #define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20)
0198 #define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY(val) BSP_FLD32(val, 24, 28)
0199 #define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_GET(reg) BSP_FLD32GET(reg, 24, 28)
0200 #define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_SET(reg, val) BSP_FLD32SET(reg, val, 24, 28)
0201     uint32_t emccal;
0202 #define LPC17XX_SCB_EMCCAL_CALVALUE(val) BSP_FLD32(val, 0, 7)
0203 #define LPC17XX_SCB_EMCCAL_CALVALUE_GET(reg) BSP_FLD32GET(reg, 0, 7)
0204 #define LPC17XX_SCB_EMCCAL_CALVALUE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0205 #define LPC17XX_SCB_EMCCAL_START BSP_BIT32(14)
0206 #define LPC17XX_SCB_EMCCAL_DONE BSP_BIT32(15)
0207 } lpc17xx_scb;
0208
0209 #define LPC17XX_SCB (*(volatile lpc17xx_scb *) (LPC17XX_BASE + 0x400fc000))
0210
0211 typedef struct {
0212     uint32_t reserved_00 [268435456];
0213     lpc17xx_wwdt wwdt;
0214     uint32_t reserved_40000020 [258040];
0215     lpc17xx_scb scb;
0216 } lpc17xx;
0217
0218 #define LPC17XX (*(volatile lpc17xx *) (LPC17XX_BASE))
0219
0220 #endif /* LPC17XX_REGS_H */