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0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMLPC176X
0005  *
0006  * @brief API definitions of the for the timer of the lpc176x bsp.
0007  */
0008 
0009 /*
0010  * Copyright (c) 2014 Taller Technologies.
0011  *
0012  * @author  Boretto Martin    (martin.boretto@tallertechnologies.com)
0013  * @author  Diaz Marcos (marcos.diaz@tallertechnologies.com)
0014  * @author  Lenarduzzi Federico  (federico.lenarduzzi@tallertechnologies.com)
0015  * @author  Daniel Chicco  (daniel.chicco@tallertechnologies.com)
0016  *
0017  * The license and distribution terms for this file may be
0018  * found in the file LICENSE in this distribution or at
0019  * http://www.rtems.org/license/LICENSE.
0020  */
0021 
0022 #ifndef LIBBSP_ARM_LPC176X_TIMER_DEFS_H
0023 #define LIBBSP_ARM_LPC176X_TIMER_DEFS_H
0024 
0025 #include <bsp/common-types.h>
0026 
0027 #ifdef __cplusplus
0028 extern "C" {
0029 #endif /* __cplusplus */
0030 
0031 /* Timer 0 */
0032 #define LPC176X_TMR0_BASE_ADDR 0x40004000U
0033 
0034 #define LPC176X_T0IR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0035                                                 0x00U ) )
0036 #define LPC176X_T0TCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0037                                                  0x04U ) )
0038 #define LPC176X_T0TC ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0039                                                 0x08U ) )
0040 #define LPC176X_T0PR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0041                                                 0x0CU ) )
0042 #define LPC176X_T0PC ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0043                                                 0x10U ) )
0044 #define LPC176X_T0MCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0045                                                  0x14U ) )
0046 #define LPC176X_T0MR0 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0047                                                  0x18U ) )
0048 #define LPC176X_T0MR1 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0049                                                  0x1CU ) )
0050 #define LPC176X_T0MR2 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0051                                                  0x20U ) )
0052 #define LPC176X_T0MR3 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0053                                                  0x24U ) )
0054 #define LPC176X_T0CCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0055                                                  0x28U ) )
0056 #define LPC176X_T0CR0 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0057                                                  0x2CU ) )
0058 #define LPC176X_T0CR1 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0059                                                  0x30U ) )
0060 #define LPC176X_T0CR2 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0061                                                  0x34U ) )
0062 #define LPC176X_T0CR3 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0063                                                  0x38U ) )
0064 #define LPC176X_T0EMR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0065                                                  0x3CU ) )
0066 #define LPC176X_T0CTCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
0067                                                   0x70U ) )
0068 
0069 /* Timer 1 */
0070 #define LPC176X_TMR1_BASE_ADDR 0x40008000U
0071 
0072 #define LPC176X_T1IR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0073                                                 0x00U ) )
0074 #define LPC176X_T1TCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0075                                                  0x04U ) )
0076 #define LPC176X_T1TC ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0077                                                 0x08U ) )
0078 #define LPC176X_T1PR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0079                                                 0x0CU ) )
0080 #define LPC176X_T1PC ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0081                                                 0x10U ) )
0082 #define LPC176X_T1MCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0083                                                  0x14U ) )
0084 #define LPC176X_T1MR0 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0085                                                  0x18U ) )
0086 #define LPC176X_T1MR1 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0087                                                  0x1CU ) )
0088 #define LPC176X_T1MR2 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0089                                                  0x20U ) )
0090 #define LPC176X_T1MR3 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0091                                                  0x24U ) )
0092 #define LPC176X_T1CCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0093                                                  0x28U ) )
0094 #define LPC176X_T1CR0 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0095                                                  0x2CU ) )
0096 #define LPC176X_T1CR1 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0097                                                  0x30U ) )
0098 #define LPC176X_T1CR2 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0099                                                  0x34U ) )
0100 #define LPC176X_T1CR3 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0101                                                  0x38U ) )
0102 #define LPC176X_T1EMR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0103                                                  0x3CU ) )
0104 #define LPC176X_T1CTCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
0105                                                   0x70U ) )
0106 
0107 /* Timer 2 */
0108 #define LPC176X_TMR2_BASE_ADDR 0x40090000U
0109 
0110 #define LPC176X_T2IR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0111                                                 0x00U ) )
0112 #define LPC176X_T2TCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0113                                                  0x04U ) )
0114 #define LPC176X_T2TC ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0115                                                 0x08U ) )
0116 #define LPC176X_T2PR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0117                                                 0x0CU ) )
0118 #define LPC176X_T2PC ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0119                                                 0x10U ) )
0120 #define LPC176X_T2MCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0121                                                  0x14U ) )
0122 #define LPC176X_T2MR0 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0123                                                  0x18U ) )
0124 #define LPC176X_T2MR1 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0125                                                  0x1CU ) )
0126 #define LPC176X_T2MR2 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0127                                                  0x20U ) )
0128 #define LPC176X_T2MR3 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0129                                                  0x24U ) )
0130 #define LPC176X_T2CCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0131                                                  0x28U ) )
0132 #define LPC176X_T2CR0 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0133                                                  0x2CU ) )
0134 #define LPC176X_T2CR1 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0135                                                  0x30U ) )
0136 #define LPC176X_T2CR2 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0137                                                  0x34U ) )
0138 #define LPC176X_T2CR3 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0139                                                  0x38U ) )
0140 #define LPC176X_T2EMR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0141                                                  0x3CU ) )
0142 #define LPC176X_T2CTCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
0143                                                   0x70U ) )
0144 
0145 /* Timer 3 */
0146 #define LPC176X_TMR3_BASE_ADDR 0x40094000U
0147 
0148 #define LPC176X_T3IR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0149                                                 0x00U ) )
0150 #define LPC176X_T3TCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0151                                                  0x04U ) )
0152 #define LPC176X_T3TC ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0153                                                 0x08U ) )
0154 #define LPC176X_T3PR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0155                                                 0x0CU ) )
0156 #define LPC176X_T3PC ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0157                                                 0x10U ) )
0158 #define LPC176X_T3MCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0159                                                  0x14U ) )
0160 #define LPC176X_T3MR0 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0161                                                  0x18U ) )
0162 #define LPC176X_T3MR1 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0163                                                  0x1CU ) )
0164 #define LPC176X_T3MR2 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0165                                                  0x20U ) )
0166 #define LPC176X_T3MR3 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0167                                                  0x24U ) )
0168 #define LPC176X_T3CCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0169                                                  0x28U ) )
0170 #define LPC176X_T3CR0 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0171                                                  0x2CU ) )
0172 #define LPC176X_T3CR1 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0173                                                  0x30U ) )
0174 #define LPC176X_T3CR2 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0175                                                  0x34U ) )
0176 #define LPC176X_T3CR3 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0177                                                  0x38U ) )
0178 #define LPC176X_T3EMR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0179                                                  0x3CU ) )
0180 #define LPC176X_T3CTCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
0181                                                   0x70U ) )
0182 
0183 /**
0184  * @brief Represents the timer device registers.
0185  */
0186 typedef struct {
0187   /**
0188    * @brief Interrupt Register.
0189    */
0190   volatile uint32_t IR;
0191   /**
0192    * @brief Timer Control Register.
0193    */
0194   volatile uint32_t TCR;
0195   /**
0196    * @brief Timer Counter.
0197    */
0198   volatile uint32_t TC;
0199   /**
0200    * @brief Prescale Register.
0201    */
0202   volatile uint32_t PR;
0203   /**
0204    * @brief Prescale Counter.
0205    */
0206   volatile uint32_t PC;
0207   /**
0208    * @brief Match Control Register.
0209    */
0210   volatile uint32_t MCR;
0211   /**
0212    * @brief Match Register (0, 1, 2, 3)
0213    */
0214   volatile uint32_t MR[ 4 ];
0215   /**
0216    * @brief Capture Control Register.
0217    */
0218   volatile uint32_t CCR;
0219   /**
0220    * @brief Capture Register (0, 1)
0221    */
0222   volatile uint32_t CR[ 2 ];
0223   volatile uint32_t reserved0;
0224   volatile uint32_t reserved1;
0225   /**
0226    * @brief External Match Register.
0227    */
0228   volatile uint32_t EMR;
0229   volatile uint32_t reserved2[ 12 ];
0230   /**
0231    * @brief Count Control Register.
0232    */
0233   volatile uint32_t CTCR;
0234 } lpc176x_timer_device;
0235 
0236 #define LPC176X_PIN_SELECT_TIMER 3U
0237 #define LPC176X_PINSEL_NO_PORT 999U
0238 
0239 #define LPC176X_TIMER_RESET ( 1U << 1U )
0240 #define LPC176X_TIMER_START 1U
0241 #define LPC176X_TIMER_MODE_COUNTER_SOURCE_CAP0 0U
0242 #define LPC176X_TIMER_MODE_COUNTER_SOURCE_CAP1 ( 1U << 2U )
0243 #define LPC176X_TIMER0_CAPTURE_PORTS { 58U, 59U }
0244 #define LPC176X_TIMER1_CAPTURE_PORTS { 50U, 51U }
0245 #define LPC176X_TIMER2_CAPTURE_PORTS { 4U, 5U }
0246 #define LPC176X_TIMER3_CAPTURE_PORTS { 23U, 24U }
0247 #define LPC176X_TIMER0_EMATCH_PORTS { 60U,   \
0248                                       61U,    \
0249                                       LPC176X_PINSEL_NO_PORT, \
0250                                       LPC176X_PINSEL_NO_PORT }
0251 #define LPC176X_TIMER1_EMATCH_PORTS { 54U, \
0252                                       57U,    \
0253                                       LPC176X_PINSEL_NO_PORT, \
0254                                       LPC176X_PINSEL_NO_PORT }
0255 #define LPC176X_TIMER2_EMATCH_PORTS { 6U, 7U, 8U, 9U }
0256 #define LPC176X_TIMER3_EMATCH_PORTS { 10U, \
0257                                       11U, \
0258                                       LPC176X_PINSEL_NO_PORT, \
0259                                       LPC176X_PINSEL_NO_PORT }
0260 #define LPC176X_TIMER_DEFAULT_RESOLUTION 1U
0261 #define LPC176X_TIMER_MCR_MASK 7U
0262 #define LPC176X_TIMER_MCR_MASK_SIZE 3U
0263 #define LPC176X_TIMER_CCR_MASK 7U
0264 #define LPC176X_TIMER_CCR_MASK_SIZE 3U
0265 #define LPC176X_TIMER_EMR_MASK 3U
0266 #define LPC176X_TIMER_EMR_MASK_SIZE 2U
0267 #define LPC176X_TIMER_EMR_MASK_OFFSET 4U
0268 #define LPC176X_TIMER_CLEAR_FUNCTION 0U
0269 #define LPC176X_TIMER_PRESCALER_DIVISOR 1000000U
0270 #define LPC176X_TIMER_VECTOR_NUMBER( timernumber ) ( timernumber + 1U )
0271 #define LPC176X_TIMER_INTERRUPT_SOURCE_BIT( i ) ( 1U << i )
0272 #define LPC176X_TIMER_MATCH_FUNCTION_COUNT 8U
0273 #define LPC176X_TIMER_CAPTURE_FUNCTION_COUNT 8U
0274 
0275 #define LPC176X_ISR_NAME_STRING_SIZE 10U
0276 
0277 #define LPC176X_SET_MCR( mcr, match_port, function )  \
0278   SET_FIELD( mcr, \
0279   function, \
0280   ( 0x7U << ( 3U * match_port ) ), \
0281   ( 3U * match_port ) )
0282 #define LPC176X_SET_CCR( mcr, capture_port, function )  \
0283   SET_FIELD( mcr, function, ( 0x7U << ( 3U * capture_port ) ), \
0284   ( 3U * capture_port ) )
0285 #define LPC176X_SET_EMR( mcr, match_port, function )  \
0286   SET_FIELD( mcr, function, ( 0x3U << ( 2U * match_port + 4U ) ), \
0287   ( 2U * match_port + 4U ) )
0288 
0289 /**
0290  * @brief Capture ports of a timer.
0291  *
0292  * Enumerated type to define the set of capture ports for a timer device.
0293  */
0294 typedef enum {
0295   LPC176X_CAPn_0,
0296   LPC176X_CAPn_1,
0297   LPC176X_CAPTURE_PORTS_COUNT
0298 } lpc176x_capture_port;
0299 
0300 /**
0301  * @brief Match ports of a timer.
0302  *
0303  * Enumerated type to define the set of match ports for a timer device.
0304  */
0305 typedef enum {
0306   LPC176X_MATn_0,
0307   LPC176X_MATn_1,
0308   LPC176X_MATn_2,
0309   LPC176X_MATn_3,
0310   LPC176X_EMATCH_PORTS_COUNT
0311 } lpc176x_match_port;
0312 
0313 /**
0314  * @brief Timer modes of a timer.
0315  *
0316  * Enumerated type to define the set of modes for a timer device.
0317  */
0318 typedef enum {
0319   LPC176X_TIMER_MODE_TIMER,
0320   LPC176X_TIMER_MODE_COUNTER_RISING_CAP0,
0321   LPC176X_TIMER_MODE_COUNTER_FALLING_CAP0,
0322   LPC176X_TIMER_MODE_COUNTER_BOTH_CAP0,
0323   LPC176X_TIMER_MODE_COUNTER_RISING_CAP1 = ( 1U & ( 1U << 2U ) ),
0324   LPC176X_TIMER_MODE_COUNTER_FALLING_CAP1 = ( 2U & ( 1U << 2U ) ),
0325   LPC176X_TIMER_MODE_COUNTER_BOTH_CAP1 = ( 3U & ( 1U << 2U ) ),
0326 } lpc176x_timer_mode;
0327 
0328 /**
0329  * @brief The timer devices in the board.
0330  *
0331  * Enumerated type to define the timer device's numbers.
0332  */
0333 typedef enum {
0334   LPC176X_TIMER_0,
0335   LPC176X_TIMER_1,
0336   LPC176X_TIMER_2,
0337   LPC176X_TIMER_3,
0338   LPC176X_TIMER_COUNT
0339 } lpc176x_timer_number;
0340 
0341 /**
0342  * @brief The index for the isr_funct_vector representing the functions
0343  *        that attends each possible interrupt source for a timer.
0344  *
0345  * Enumerated type to define the set of  isr timer functions .
0346  */
0347 typedef enum {
0348   LPC176X_MAT0_ISR_FUNCTION,
0349   LPC176X_MAT1_ISR_FUNCTION,
0350   LPC176X_MAT2_ISR_FUNCTION,
0351   LPC176X_MAT3_ISR_FUNCTION,
0352   LPC176X_CAP0_ISR_FUNCTION,
0353   LPC176X_CAP1_ISR_FUNCTION,
0354   LPC176X_ISR_FUNCTIONS_COUNT
0355 } lpc176x_isr_function;
0356 
0357 /**
0358  * @brief The possible functions at match. This options could be
0359  *        used together.
0360  *
0361  * Enumerated type to define the set of  functions at mach for a
0362  *     timer device.
0363  */
0364 typedef enum {
0365   LPC176X_TIMER_MATCH_FUNCTION_NONE = 0U,
0366   LPC176X_TIMER_MATCH_FUNCTION_INTERRUPT = 1U,
0367   LPC176X_TIMER_MATCH_FUNCTION_RESET = ( 1U << 1U ),
0368   LPC176X_TIMER_MATCH_FUNCTION_STOP = ( 1U << 2U )
0369 } lpc176x_match_function;
0370 
0371 /**
0372  * @brief The possible functions at capture. This options could
0373  *        be used together.
0374  *
0375  * Enumerated type to define the set of  functions at capture for
0376  *     a timer device.
0377  */
0378 typedef enum {
0379   LPC176X_TIMER_CAPTURE_FUNCTION_NONE = 0U,
0380   LPC176X_TIMER_CAPTURE_FUNCTION_RISING = 1U,
0381   LPC176X_TIMER_CAPTURE_FUNCTION_FALLING = ( 1U << 1U ),
0382   LPC176X_TIMER_CAPTURE_FUNCTION_INTERRUPT = ( 1U << 2U )
0383 } lpc176x_capture_function;
0384 
0385 /**
0386  * @brief The possible functions at match, for the external ports.
0387  *
0388  * Enumerated type to define the set of  functions at match, for external
0389  *     ports, for a timer device.
0390  */
0391 typedef enum {
0392   LPC176X_TIMER_EXTMATCH_FUNCTION_NONE,
0393   LPC176X_TIMER_EXTMATCH_FUNCTION_CLEAR,
0394   LPC176X_TIMER_EXTMATCH_FUNCTION_SET,
0395   LPC176X_TIMER_EXTMATCH_FUNCTION_TOGGLE
0396 } lpc176x_ext_match_function;
0397 
0398 /**
0399  * @brief A function that attends an interruption for a timer.
0400  *
0401  * @param  tnumber Timer number.
0402  * @return Pointer to the match function.
0403  */
0404 typedef void (*lpc176x_isr_funct) ( const lpc176x_timer_number tnumber );
0405 
0406 /**
0407  * @brief The vector of functions that attends each possible interrupt
0408  *        source for a timer.
0409  */
0410 typedef lpc176x_isr_funct const lpc176x_isr_funct_vector[
0411     LPC176X_ISR_FUNCTIONS_COUNT ];
0412 
0413 /**
0414  * @brief The Timer device representation.
0415  */
0416 typedef struct {
0417   /**
0418    * @brief The address of the controlling registers for the timer.
0419    */
0420   lpc176x_timer_device *const device;
0421   /**
0422    * @brief The module for the RTEMS module starting (power and clock).
0423    */
0424   const lpc176x_module module;
0425   /**
0426    * @brief The Pins for the Capture ports of this timer.
0427    */
0428   const lpc176x_pin_number pinselcap[ LPC176X_CAPTURE_PORTS_COUNT ];
0429   /**
0430    * @brief The Pins for the external match ports of this timer.
0431    */
0432   const lpc176x_pin_number pinselemat[ LPC176X_EMATCH_PORTS_COUNT ];
0433 } lpc176x_timer;
0434 
0435 /**
0436  * @brief The Timer functions.
0437  */
0438 typedef struct {
0439   /**
0440    * @brief The vector of isr functions for this timer.
0441    */
0442   const lpc176x_isr_funct_vector *funct_vector;
0443 } lpc176x_timer_functions;
0444 
0445 #ifdef __cplusplus
0446 }
0447 #endif /* __cplusplus */
0448 
0449 #endif /* LIBBSP_ARM_LPC176X_TIMER_DEFS_H */
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