include/bsp/lpc176x.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMLPC176X
0005  *
0006  * @brief Specific register definitions according to lpc176x family boards.
0007  */
0008
0009 /*
0010  * Copyright (c) 2014 Taller Technologies.
0011  *
0012  * @author  Boretto Martin    (martin.boretto@tallertechnologies.com)
0013  * @author  Diaz Marcos (marcos.diaz@tallertechnologies.com)
0014  * @author  Lenarduzzi Federico  (federico.lenarduzzi@tallertechnologies.com)
0015  * @author  Daniel Chicco  (daniel.chicco@tallertechnologies.com)
0016  *
0017  * The license and distribution terms for this file may be
0018  * found in the file LICENSE in this distribution or at
0019  * http://www.rtems.org/license/LICENSE.
0020  */
0021
0022 #ifndef LIBBSP_ARM_LPC176X_H
0023 #define LIBBSP_ARM_LPC176X_H
0024
0025 #include <bsp/lpc-i2s.h>
0026
0027 #define LPC176X_PLL_CON_PLLE BSP_BIT32( 0 )
0028 #define LPC176X_PLL_CON_PLLC BSP_BIT32( 1 )
0029 #define LPC176X_PLL_SEL_MSEL( val ) BSP_FLD32( val, 0, 14 )
0030 #define LPC176X_PLL_SEL_MSEL_GET( reg ) BSP_FLD32GET( reg, 0, 14 )
0031 #define LPC176X_PLL_SEL_MSEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 14 )
0032 #define LPC176X_PLL_SEL_PSEL( val ) BSP_FLD32( val, 16, 23 )
0033 #define LPC176X_PLL_SEL_PSEL_GET( reg ) BSP_FLD32GET( reg, 16, 23 )
0034 #define LPC176X_PLL_SEL_PSEL_SET( reg, val ) BSP_FLD32SET( reg, val, 16, 23 )
0035 #define LPC176X_PLL_STAT_PLLE BSP_BIT32( 24 )
0036 #define LPC176X_PLL_STAT_PLLC BSP_BIT32( 25 )
0037 #define LPC176X_PLL_STAT_PLOCK BSP_BIT32( 26 )
0038
0039 /**
0040  * @brief Phase-Locked Loop representation.
0041  */
0042 typedef struct {
0043   /**
0044    * @brief PLL Control Register.
0045    */
0046   uint32_t con;
0047   /**
0048    * @brief PLL Configuration Register.
0049    */
0050   uint32_t cfg;
0051   /**
0052    * @brief PLL Status Register.
0053    */
0054   uint32_t stat;
0055   /**
0056    * @brief PLL Feed Register.
0057    */
0058   uint32_t feed;
0059 } lpc176x_pll;
0060
0061 #define LPC176X_SCB_BASE_ADDR 0x400FC000U
0062 #define LPC176X_SCB_FLASHCFG_FLASHTIM( val ) BSP_FLD32( val, 12, 15 )
0063 #define LPC176X_SCB_FLASHCFG_FLASHTIM_GET( reg ) BSP_FLD32GET( reg, 12, 15 )
0064 #define LPC176X_SCB_FLASHCFG_FLASHTIM_SET( reg, val ) BSP_FLD32SET( reg, val, \
0065   12, 15 )
0066 #define LPC176X_SCB_MEMMAP_MAP BSP_BIT32( 0 )
0067 /* POWER MODE CONTROL REGISTER (PCON) */
0068 /* Power mode control bit 0 */
0069 #define LPC176X_SCB_PCON_PM0 BSP_BIT32( 0 )
0070 /* Power mode control bit 1 */
0071 #define LPC176X_SCB_PCON_PM1 BSP_BIT32( 1 )
0072 /* Brown-Out Reduced ower Down */
0073 #define LPC176X_SCB_PCON_BODRPM BSP_BIT32( 2 )
0074 /* Brown-Out Global Disable */
0075 #define LPC176X_SCB_PCON_BOGD BSP_BIT32( 3 )
0076 /* Brown-Out Reset Disable */
0077 #define LPC176X_SCB_PCON_BORD BSP_BIT32( 4 )
0078 /* Sleep Mode entry flag */
0079 #define LPC176X_SCB_PCON_SMFLAG BSP_BIT32( 8 )
0080 /* Deep Sleep entry flag */
0081 #define LPC176X_SCB_PCON_DSFLAG BSP_BIT32( 9 )
0082 /* Power-Down entry flag */
0083 #define LPC176X_SCB_PCON_PDFLAG BSP_BIT32( 10 )
0084 /* Deep Power-Down entry flag */
0085 #define LPC176X_SCB_PCON_DPDFLAG BSP_BIT32( 11 )
0086 /* POWER CONTROL for PERIPHERALS REGISTER (PCONP) */
0087 /* 0 - Reserved */
0088 /* Timer/Counter 0 power/clock control bit */
0089 #define LPC176X_SCB_PCONP_TIMER_0 BSP_BIT32( 1 )
0090 /* Timer/Counter 1 power/clock control bit */
0091 #define LPC176X_SCB_PCONP_TIMER_1 BSP_BIT32( 2 )
0092 /* UART 0 power/clock control bit */
0093 #define LPC176X_SCB_PCONP_UART_0 BSP_BIT32( 3 )
0094 /* UART 1 power/clock control bit */
0095 #define LPC176X_SCB_PCONP_UART_1 BSP_BIT32( 4 )
0096 /* 5 - Reserved */
0097 /* PWM 1 power/clock control bit */
0098 #define LPC176X_SCB_PCONP_PWM_0 BSP_BIT32( 6 )
0099 /* The I2C0 interface power/clock control bit */
0100 #define LPC176X_SCB_PCONP_I2C_0 BSP_BIT32( 7 )
0101 /* The SPI interface power/clock control bit */
0102 #define LPC176X_SCB_PCONP_SPI BSP_BIT32( 8 )
0103 /* The RTC power/clock control bit */
0104 #define LPC176X_SCB_PCONP_RTC BSP_BIT32( 9 )
0105 /* The SSP1 interface power/clock control bit */
0106 #define LPC176X_SCB_PCONP_SSP_1 BSP_BIT32( 10 )
0107 /* 11 - Reserved */
0108 /* A/D converter (ADC) power/clock control bit */
0109 #define LPC176X_SCB_PCONP_ADC BSP_BIT32( 12 )
0110 /* CAN Controller 1 power/clock control bit */
0111 #define LPC176X_SCB_PCONP_CAN_1 BSP_BIT32( 13 )
0112 /* CAN Controller 2 power/clock control bit */
0113 #define LPC176X_SCB_PCONP_CAN_2 BSP_BIT32( 14 )
0114 /* Power/clock control bit for IOCON, GPIO, and GPIO interrupts*/
0115 #define LPC176X_SCB_PCONP_GPIO BSP_BIT32( 15 )
0116 /* Repetitive Interrupt Timer power/clock control bit */
0117 #define LPC176X_SCB_PCONP_RIT BSP_BIT32( 16 )
0118 /* Motor Control PWM */
0119 #define LPC176X_SCB_PCONP_MCPWM BSP_BIT32( 17 )
0120 /* Quadrate Encoder Interface power/clock control bit */
0121 #define LPC176X_SCB_PCONP_QEI BSP_BIT32( 18 )
0122 /* The IC21 interface power/clock control bit */
0123 #define LPC176X_SCB_PCONP_I2C_1 BSP_BIT32( 19 )
0124 /* 20 - Reserved */
0125 /* The SSP0 interface power/clock control bit */
0126 #define LPC176X_SCB_PCONP_SSP_0 BSP_BIT32( 21 )
0127 /* Timer 2 power/clock control bit */
0128 #define LPC176X_SCB_PCONP_TIMER_2 BSP_BIT32( 22 )
0129 /* Timer 3 power/clock control bit */
0130 #define LPC176X_SCB_PCONP_TIMER_3 BSP_BIT32( 23 )
0131 /* UART 2 power/clock control bit */
0132 #define LPC176X_SCB_PCONP_UART_2 BSP_BIT32( 24 )
0133 /* UART 3 power/clock control bit */
0134 #define LPC176X_SCB_PCONP_UART_3 BSP_BIT32( 25 )
0135 /* I2C interface 2 power/clock control bit */
0136 #define LPC176X_SCB_PCONP_I2C_2 BSP_BIT32( 26 )
0137 /* I2S interface power/clock control bit */
0138 #define LPC176X_SCB_PCONP_I2S BSP_BIT32( 27 )
0139 /* 28 - Reserved */
0140 /* GPDMA function power/clock control bit */
0141 #define LPC176X_SCB_PCONP_GPDMA BSP_BIT32( 29 )
0142 /* Ethernet block power/clock control bit */
0143 #define LPC176X_SCB_PCONP_ENET BSP_BIT32( 30 )
0144 /* USB interface power/clock control bit */
0145 #define LPC176X_SCB_PCONP_USB BSP_BIT32( 31 )
0146 #define LPC176X_SCB_CCLKSEL_CCLKDIV( val ) BSP_FLD32( val, 0, 7 )
0147 #define LPC176X_SCB_CCLKSEL_CCLKDIV_GET( reg ) BSP_FLD32GET( reg, 0, 7 )
0148 #define LPC176X_SCB_CCLKSEL_CCLKDIV_SET( reg, val ) BSP_FLD32SET( reg, \
0149   val, \
0150   0, \
0151   7 )
0152 #define LPC176X_SCB_CCLKSEL_CCLKSEL BSP_BIT32( 8 )
0153 #define LPC176X_SCB_USBCLKSEL_USBDIV( val ) BSP_FLD32( val, 0, 4 )
0154 #define LPC176X_SCB_USBCLKSEL_USBDIV_GET( reg ) BSP_FLD32GET( reg, 0, 4 )
0155 #define LPC176X_SCB_USBCLKSEL_USBDIV_SET( reg, val ) BSP_FLD32SET( reg, \
0156   val, \
0157   0, \
0158   4 )
0159 #define LPC176X_SCB_USBCLKSEL_USBSEL( val ) BSP_FLD32( val, 8, 9 )
0160 #define LPC176X_SCB_USBCLKSEL_USBSEL_GET( reg ) BSP_FLD32GET( reg, 8, 9 )
0161 #define LPC176X_SCB_USBCLKSEL_USBSEL_SET( reg, val ) BSP_FLD32SET( reg, \
0162   val, \
0163   8, \
0164   9 )
0165 #define LPC176X_SCB_CLKSRCSEL_CLKSRC BSP_BIT32( 0 )
0166 #define LPC176X_SCB_SCS_MCIPWR BSP_BIT32( 3 )
0167 #define LPC176X_SCB_SCS_OSC_RANGE_SEL BSP_BIT32( 4 )
0168 #define LPC176X_SCB_SCS_OSC_ENABLE BSP_BIT32( 5 )
0169 #define LPC176X_SCB_SCS_OSC_STATUS BSP_BIT32( 6 )
0170 #define LPC176X_SCB_PCLKSEL_PCLKDIV( val ) BSP_FLD32( val, 0, 4 )
0171 #define LPC176X_SCB_PCLKSEL_PCLKDIV_GET( reg ) BSP_FLD32GET( reg, 0, 4 )
0172 #define LPC176X_SCB_PCLKSEL_PCLKDIV_SET( reg, val ) BSP_FLD32SET( reg, \
0173   val, \
0174   0, \
0175   4 )
0176 #define LPC176X_SCB_PBOOST_BOOST BSP_BIT32( 0 )
0177 #define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL( val ) BSP_FLD32( val, 3, 0 )
0178 #define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL_GET( reg ) BSP_FLD32GET( reg, 3, 0 )
0179 #define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL_SET( reg, val ) BSP_FLD32SET( reg, \
0180   val, 3, 0 )
0181 #define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV( val ) BSP_FLD32( val, 7, 4 )
0182 #define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV_GET( reg ) BSP_FLD32GET( reg, 7, 4 )
0183 #define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV_SET( reg, val ) BSP_FLD32SET( reg, \
0184   val, 7, 4 )
0185 #define LPC176X_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32( 8 )
0186 #define LPC176X_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32( 9 )
0187
0188 /**
0189  * @brief System Control Block representation.
0190  */
0191 typedef struct {
0192   /**
0193    * @brief Flash Accelerator Configuration Register.
0194    */
0195   uint32_t flashcfg;
0196   uint32_t reserved_04[ 15 ];
0197   /**
0198    * @brief Memopry Map Control.
0199    */
0200   uint32_t memmap;
0201   uint32_t reserved_44[ 15 ];
0202   /**
0203    * @brief Phase-Locked Loop 0.
0204    */
0205   lpc176x_pll pll_0;
0206   uint32_t reserved_90[ 4 ];
0207   /**
0208    * @brief Phase-Locked Loop 1.
0209    */
0210   lpc176x_pll pll_1;
0211   uint32_t reserved_b0[ 4 ];
0212   /**
0213    * @brief Power Mode Control register.
0214    */
0215   uint32_t pcon;
0216   /**
0217    * @brief Power Control for Peripherals register.
0218    */
0219   uint32_t pconp;
0220   uint32_t reserved_c8[ 15 ];
0221   /**
0222    *@brief Selects the divide valuefor creating the CPU clock from the
0223    *       PPL0 output.
0224    */
0225   uint32_t cclksel;
0226   /**
0227    * @brief Selects the divide value for creating the USB clock from the
0228    *        PPL0 output.
0229    */
0230   uint32_t usbclksel;
0231   /**
0232    * @brief Clock Source Select register.
0233    */
0234   uint32_t clksrcsel;
0235   uint32_t reserved_110[ 12 ];
0236   /**
0237    * @brief External Interrupt flag register.
0238    */
0239   uint32_t extint;
0240   uint32_t reserved_144;
0241   /**
0242    * @brief  External Interrupt Mode register.
0243    */
0244   uint32_t extmode;
0245   /**
0246    * @brief  External Interrupt Polarity register.
0247    */
0248   uint32_t extpolar;
0249   uint32_t reserved_150[ 12 ];
0250   /**
0251    * @brief Reset Source Identification Register.
0252    */
0253   uint32_t rsid;
0254   uint32_t reserved_184[ 7 ];
0255   /**
0256    * @brief System Controls and Status Register.
0257    */
0258   uint32_t scs;
0259   uint32_t reserved_1a4;
0260   /**
0261    * @brief Peripheral Clock Selection registers 0 and 1.
0262    */
0263   uint32_t pclksel[ 2 ];
0264   /**
0265    * @brief Peripheral boost.
0266    */
0267   uint32_t pboost;
0268   uint32_t reserved_1b4[ 5 ];
0269   /**
0270    * @brief Clock Output Configuration Register.
0271    */
0272   uint32_t clkoutcfg;
0273   /**
0274    * @brief Reset Control bit 0 and 1.
0275    */
0276   uint32_t rstcon[ 2 ];
0277   uint32_t reserved_1d4[ 4 ];
0278 } lpc176x_scb;
0279
0280 #define LPC176X_BASE 0x00u
0281 #define LPC176X_SCB ( *(volatile lpc176x_scb *) ( LPC176X_SCB_BASE_ADDR ) )
0282
0283 /* Fast I/O setup */
0284 #define LPC176X_FIO_BASE_ADDR 0x2009C000U
0285 #define LPC176X_FIO ( (volatile lpc176x_fio *) LPC176X_FIO_BASE_ADDR )
0286
0287 #define FIO0DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) )
0288 #define FIO0MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) )
0289 #define FIO0PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) )
0290 #define FIO0SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) )
0291 #define FIO0CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) )
0292
0293 #define FIO1DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) )
0294 #define FIO1MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) )
0295 #define FIO1PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) )
0296 #define FIO1SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) )
0297 #define FIO1CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) )
0298
0299 #define FIO2DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) )
0300 #define FIO2MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) )
0301 #define FIO2PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) )
0302 #define FIO2SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) )
0303 #define FIO2CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) )
0304
0305 #define FIO3DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) )
0306 #define FIO3MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) )
0307 #define FIO3PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) )
0308 #define FIO3SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) )
0309 #define FIO3CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) )
0310
0311 #define FIO4DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) )
0312 #define FIO4MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) )
0313 #define FIO4PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) )
0314 #define FIO4SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) )
0315 #define FIO4CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) )
0316
0317 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
0318 #define FIO0DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) )
0319 #define FIO1DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) )
0320 #define FIO2DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) )
0321 #define FIO3DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) )
0322 #define FIO4DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) )
0323
0324 #define FIO0DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x01U ) )
0325 #define FIO1DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x21U ) )
0326 #define FIO2DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x41U ) )
0327 #define FIO3DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x61U ) )
0328 #define FIO4DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x81U ) )
0329
0330 #define FIO0DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x02U ) )
0331 #define FIO1DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x22U ) )
0332 #define FIO2DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x42U ) )
0333 #define FIO3DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x62U ) )
0334 #define FIO4DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x82U ) )
0335
0336 #define FIO0DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x03U ) )
0337 #define FIO1DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x23U ) )
0338 #define FIO2DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x43U ) )
0339 #define FIO3DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x63U ) )
0340 #define FIO4DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x83U ) )
0341
0342 #define FIO0DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) )
0343 #define FIO1DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) )
0344 #define FIO2DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) )
0345 #define FIO3DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) )
0346 #define FIO4DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) )
0347
0348 #define FIO0DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x02U ) )
0349 #define FIO1DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x22U ) )
0350 #define FIO2DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x42U ) )
0351 #define FIO3DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x62U ) )
0352 #define FIO4DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x82U ) )
0353
0354 #define FIO0MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) )
0355 #define FIO1MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) )
0356 #define FIO2MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) )
0357 #define FIO3MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) )
0358 #define FIO4MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) )
0359
0360 #define FIO0MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x11U ) )
0361 #define FIO1MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x21U ) )
0362 #define FIO2MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x51U ) )
0363 #define FIO3MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x71U ) )
0364 #define FIO4MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x91U ) )
0365
0366 #define FIO0MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x12U ) )
0367 #define FIO1MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x32U ) )
0368 #define FIO2MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x52U ) )
0369 #define FIO3MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x72U ) )
0370 #define FIO4MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x92U ) )
0371
0372 #define FIO0MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x13U ) )
0373 #define FIO1MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x33U ) )
0374 #define FIO2MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x53U ) )
0375 #define FIO3MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x73U ) )
0376 #define FIO4MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x93U ) )
0377
0378 #define FIO0MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) )
0379 #define FIO1MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) )
0380 #define FIO2MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) )
0381 #define FIO3MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) )
0382 #define FIO4MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) )
0383
0384 #define FIO0MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x12U ) )
0385 #define FIO1MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x32U ) )
0386 #define FIO2MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x52U ) )
0387 #define FIO3MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x72U ) )
0388 #define FIO4MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x92U ) )
0389
0390 #define FIO0PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) )
0391 #define FIO1PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) )
0392 #define FIO2PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) )
0393 #define FIO3PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) )
0394 #define FIO4PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) )
0395
0396 #define FIO0PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x15U ) )
0397 #define FIO1PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x25U ) )
0398 #define FIO2PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x55U ) )
0399 #define FIO3PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x75U ) )
0400 #define FIO4PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x95U ) )
0401
0402 #define FIO0PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x16U ) )
0403 #define FIO1PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x36U ) )
0404 #define FIO2PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x56U ) )
0405 #define FIO3PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x76U ) )
0406 #define FIO4PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x96U ) )
0407
0408 #define FIO0PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x17U ) )
0409 #define FIO1PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x37U ) )
0410 #define FIO2PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x57U ) )
0411 #define FIO3PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x77U ) )
0412 #define FIO4PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x97U ) )
0413
0414 #define FIO0PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) )
0415 #define FIO1PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) )
0416 #define FIO2PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) )
0417 #define FIO3PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) )
0418 #define FIO4PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) )
0419
0420 #define FIO0PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x16U ) )
0421 #define FIO1PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x36U ) )
0422 #define FIO2PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x56U ) )
0423 #define FIO3PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x76U ) )
0424 #define FIO4PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x96U ) )
0425
0426 #define FIO0SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) )
0427 #define FIO1SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) )
0428 #define FIO2SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) )
0429 #define FIO3SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) )
0430 #define FIO4SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) )
0431
0432 #define FIO0SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x19U ) )
0433 #define FIO1SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x29U ) )
0434 #define FIO2SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x59U ) )
0435 #define FIO3SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x79U ) )
0436 #define FIO4SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x99U ) )
0437
0438 #define FIO0SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1AU ) )
0439 #define FIO1SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3AU ) )
0440 #define FIO2SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5AU ) )
0441 #define FIO3SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7AU ) )
0442 #define FIO4SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9AU ) )
0443
0444 #define FIO0SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1BU ) )
0445 #define FIO1SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3BU ) )
0446 #define FIO2SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5BU ) )
0447 #define FIO3SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7BU ) )
0448 #define FIO4SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9BU ) )
0449
0450 #define FIO0SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) )
0451 #define FIO1SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) )
0452 #define FIO2SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) )
0453 #define FIO3SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) )
0454 #define FIO4SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) )
0455
0456 #define FIO0SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1AU ) )
0457 #define FIO1SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3AU ) )
0458 #define FIO2SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5AU ) )
0459 #define FIO3SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7AU ) )
0460 #define FIO4SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x9AU ) )
0461
0462 #define FIO0CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) )
0463 #define FIO1CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) )
0464 #define FIO2CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) )
0465 #define FIO3CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) )
0466 #define FIO4CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) )
0467
0468 #define FIO0CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1DU ) )
0469 #define FIO1CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x2DU ) )
0470 #define FIO2CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5DU ) )
0471 #define FIO3CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7DU ) )
0472 #define FIO4CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9DU ) )
0473
0474 #define FIO0CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1EU ) )
0475 #define FIO1CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3EU ) )
0476 #define FIO2CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5EU ) )
0477 #define FIO3CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7EU ) )
0478 #define FIO4CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9EU ) )
0479
0480 #define FIO0CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1FU ) )
0481 #define FIO1CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3FU ) )
0482 #define FIO2CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5FU ) )
0483 #define FIO3CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7FU ) )
0484 #define FIO4CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9FU ) )
0485
0486 #define FIO0CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) )
0487 #define FIO1CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) )
0488 #define FIO2CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) )
0489 #define FIO3CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) )
0490 #define FIO4CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) )
0491
0492 #define FIO0CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1EU ) )
0493 #define FIO1CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3EU ) )
0494 #define FIO2CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5EU ) )
0495 #define FIO3CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7EU ) )
0496 #define FIO4CLRU ( *(volatile uint16_t *) ( FIO_BASE_ADDR + 0x9EU ) )
0497
0498 #define LPC176X_USB_CLOCK 48000000U
0499 #define LPC176X_MODULE_CLOCK_MASK 0x3U
0500
0501 /* Pin Connect Block */
0502 #define PINSEL_BASE_ADDR 0x4002C000U
0503
0504 #define PINSEL0 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x00U ) )
0505 #define PINSEL1 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x04U ) )
0506 #define PINSEL2 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x08U ) )
0507 #define PINSEL3 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x0CU ) )
0508 #define PINSEL4 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x10U ) )
0509 #define PINSEL5 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x14U ) )
0510 #define PINSEL6 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x18U ) )
0511 #define PINSEL7 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x1CU ) )
0512 #define PINSEL8 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x20U ) )
0513 #define PINSEL9 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x24U ) )
0514 #define PINSEL10 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x28U ) )
0515 #define PINSEL11 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x2CU ) )
0516
0517 #define PINMODE0 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x40U ) )
0518 #define PINMODE1 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x44U ) )
0519 #define PINMODE2 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x48U ) )
0520 #define PINMODE3 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x4CU ) )
0521 #define PINMODE4 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x50U ) )
0522 #define PINMODE5 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x54U ) )
0523 #define PINMODE6 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x58U ) )
0524 #define PINMODE7 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x5CU ) )
0525 #define PINMODE8 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x60U ) )
0526 #define PINMODE9 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x64U ) )
0527
0528 /* Pulse Width Modulator (PWM) */
0529 #define PWM0_BASE_ADDR 0x40014000
0530
0531 #define PWM0IR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x00 ) )
0532 #define PWM0TCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x04 ) )
0533 #define PWM0TC ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x08 ) )
0534 #define PWM0PR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x0C ) )
0535 #define PWM0PC ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x10 ) )
0536 #define PWM0MCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x14 ) )
0537 #define PWM0MR0 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x18 ) )
0538 #define PWM0MR1 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x1C ) )
0539 #define PWM0MR2 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x20 ) )
0540 #define PWM0MR3 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x24 ) )
0541 #define PWM0CCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x28 ) )
0542 #define PWM0CR0 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x2C ) )
0543 #define PWM0CR1 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x30 ) )
0544 #define PWM0CR2 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x34 ) )
0545 #define PWM0CR3 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x38 ) )
0546 #define PWM0EMR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x3C ) )
0547 #define PWM0MR4 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x40 ) )
0548 #define PWM0MR5 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x44 ) )
0549 #define PWM0MR6 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x48 ) )
0550 #define PWM0PCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x4C ) )
0551 #define PWM0LER ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x50 ) )
0552 #define PWM0CTCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x70 ) )
0553
0554 #define PWM1_BASE_ADDR 0x40018000
0555
0556 #define PWM1IR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x00 ) )
0557 #define PWM1TCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x04 ) )
0558 #define PWM1TC ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x08 ) )
0559 #define PWM1PR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x0C ) )
0560 #define PWM1PC ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x10 ) )
0561 #define PWM1MCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x14 ) )
0562 #define PWM1MR0 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x18 ) )
0563 #define PWM1MR1 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x1C ) )
0564 #define PWM1MR2 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x20 ) )
0565 #define PWM1MR3 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x24 ) )
0566 #define PWM1CCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x28 ) )
0567 #define PWM1CR0 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x2C ) )
0568 #define PWM1CR1 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x30 ) )
0569 #define PWM1CR2 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x34 ) )
0570 #define PWM1CR3 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x38 ) )
0571 #define PWM1EMR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x3C ) )
0572 #define PWM1MR4 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x40 ) )
0573 #define PWM1MR5 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x44 ) )
0574 #define PWM1MR6 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x48 ) )
0575 #define PWM1PCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x4C ) )
0576 #define PWM1LER ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x50 ) )
0577 #define PWM1CTCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x70 ) )
0578
0579 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
0580 #define UART0_BASE_ADDR 0x4000C000
0581
0582 #define U0RBR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) )
0583 #define U0THR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) )
0584 #define U0DLL ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) )
0585 #define U0DLM ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x04 ) )
0586 #define U0IER ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x04 ) )
0587 #define U0IIR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x08 ) )
0588 #define U0FCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x08 ) )
0589 #define U0LCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x0C ) )
0590 #define U0LSR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x14 ) )
0591 #define U0SCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x1C ) )
0592 #define U0ACR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x20 ) )
0593 #define U0ICR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x24 ) )
0594 #define U0FDR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x28 ) )
0595 #define U0TER ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x30 ) )
0596
0597 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
0598 #define UART1_BASE_ADDR 0x40010000
0599
0600 #define U1RBR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) )
0601 #define U1THR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) )
0602 #define U1DLL ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) )
0603 #define U1DLM ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x04 ) )
0604 #define U1IER ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x04 ) )
0605 #define U1IIR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x08 ) )
0606 #define U1FCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x08 ) )
0607 #define U1LCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x0C ) )
0608 #define U1MCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x10 ) )
0609 #define U1LSR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x14 ) )
0610 #define U1MSR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x18 ) )
0611 #define U1SCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x1C ) )
0612 #define U1ACR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x20 ) )
0613 #define U1FDR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x28 ) )
0614 #define U1TER ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x30 ) )
0615
0616 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
0617 #define UART2_BASE_ADDR 0x40098000
0618
0619 #define U2RBR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) )
0620 #define U2THR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) )
0621 #define U2DLL ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) )
0622 #define U2DLM ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x04 ) )
0623 #define U2IER ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x04 ) )
0624 #define U2IIR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x08 ) )
0625 #define U2FCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x08 ) )
0626 #define U2LCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x0C ) )
0627 #define U2LSR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x14 ) )
0628 #define U2SCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x1C ) )
0629 #define U2ACR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x20 ) )
0630 #define U2ICR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x24 ) )
0631 #define U2FDR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x28 ) )
0632 #define U2TER ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x30 ) )
0633
0634 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
0635 #define UART3_BASE_ADDR 0x4009C000
0636
0637 #define U3RBR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) )
0638 #define U3THR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) )
0639 #define U3DLL ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) )
0640 #define U3DLM ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x04 ) )
0641 #define U3IER ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x04 ) )
0642 #define U3IIR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x08 ) )
0643 #define U3FCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x08 ) )
0644 #define U3LCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x0C ) )
0645 #define U3LSR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x14 ) )
0646 #define U3SCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x1C ) )
0647 #define U3ACR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x20 ) )
0648 #define U3ICR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x24 ) )
0649 #define U3FDR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x28 ) )
0650 #define U3TER ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x30 ) )
0651
0652 /* SPI0 (Serial Peripheral Interface 0) */
0653 #define SPI0_BASE_ADDR 0xE0020000
0654 #define S0SPCR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x00 ) )
0655 #define S0SPSR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x04 ) )
0656 #define S0SPDR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x08 ) )
0657 #define S0SPCCR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x0C ) )
0658 #define S0SPINT ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x1C ) )
0659
0660 /* Real Time Clock */
0661 #define RTC_BASE_ADDR 0x40024000
0662
0663 #define RTC_ILR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x00 ) )
0664 #define RTC_CTC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x04 ) )
0665 #define RTC_CCR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x08 ) )
0666 #define RTC_CIIR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x0C ) )
0667 #define RTC_AMR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x10 ) )
0668 #define RTC_CTIME0 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x14 ) )
0669 #define RTC_CTIME1 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x18 ) )
0670 #define RTC_CTIME2 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x1C ) )
0671 #define RTC_SEC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x20 ) )
0672 #define RTC_MIN ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x24 ) )
0673 #define RTC_HOUR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x28 ) )
0674 #define RTC_DOM ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x2C ) )
0675 #define RTC_DOW ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x30 ) )
0676 #define RTC_DOY ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x34 ) )
0677 #define RTC_MONTH ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x38 ) )
0678 #define RTC_YEAR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x3C ) )
0679 #define RTC_CISS ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x40 ) )
0680 #define RTC_ALSEC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x60 ) )
0681 #define RTC_ALMIN ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x64 ) )
0682 #define RTC_ALHOUR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x68 ) )
0683 #define RTC_ALDOM ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x6C ) )
0684 #define RTC_ALDOW ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x70 ) )
0685 #define RTC_ALDOY ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x74 ) )
0686 #define RTC_ALMON ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x78 ) )
0687 #define RTC_ALYEAR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x7C ) )
0688 #define RTC_PREINT ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x80 ) )
0689 #define RTC_PREFRAC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x84 ) )
0690
0691 /* A/D Converter 0 (AD0) */
0692 #define AD0_BASE_ADDR 0x40034000
0693
0694 #define AD0CR ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x00 ) )
0695 #define AD0GDR ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x04 ) )
0696 #define AD0INTEN ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x0C ) )
0697 #define AD0_DATA_START ( (volatile uint32_t *) ( AD0_BASE_ADDR + 0x10 ) )
0698 #define AD0DR0 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x10 ) )
0699 #define AD0DR1 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x14 ) )
0700 #define AD0DR2 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x18 ) )
0701 #define AD0DR3 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x1C ) )
0702 #define AD0DR4 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x20 ) )
0703 #define AD0DR5 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x24 ) )
0704 #define AD0DR6 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x28 ) )
0705 #define AD0DR7 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x2C ) )
0706 #define AD0STAT ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x30 ) )
0707
0708 /* D/A Converter */
0709 #define DAC_BASE_ADDR 0x4008C000
0710
0711 #define DACR ( *(volatile uint32_t *) ( DAC_BASE_ADDR + 0x00 ) )
0712
0713 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
0714 #define CAN_ACCEPT_BASE_ADDR 0x4003C000
0715
0716 #define CAN_AFMR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x00 ) )
0717 #define CAN_SFF_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x04 ) )
0718 #define CAN_SFF_GRP_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \
0719                                                   0x08 ) )
0720 #define CAN_EFF_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x0C ) )
0721 #define CAN_EFF_GRP_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \
0722                                                   0x10 ) )
0723 #define CAN_EOT ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x14 ) )
0724 #define CAN_LUT_ERR_ADR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \
0725                                                    0x18 ) )
0726 #define CAN_LUT_ERR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x1C ) )
0727
0728 #define CAN_CENTRAL_BASE_ADDR 0x40040000
0729
0730 #define CAN_TX_SR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x00 ) )
0731 #define CAN_RX_SR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x04 ) )
0732 #define CAN_MSR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x08 ) )
0733
0734 #define CAN1_BASE_ADDR 0x40044000
0735
0736 #define CAN1MOD ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x00 ) )
0737 #define CAN1CMR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x04 ) )
0738 #define CAN1GSR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x08 ) )
0739 #define CAN1ICR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x0C ) )
0740 #define CAN1IER ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x10 ) )
0741 #define CAN1BTR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x14 ) )
0742 #define CAN1EWL ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x18 ) )
0743 #define CAN1SR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x1C ) )
0744 #define CAN1RFS ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x20 ) )
0745 #define CAN1RID ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x24 ) )
0746 #define CAN1RDA ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x28 ) )
0747 #define CAN1RDB ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x2C ) )
0748
0749 #define CAN1TFI1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x30 ) )
0750 #define CAN1TID1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x34 ) )
0751 #define CAN1TDA1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x38 ) )
0752 #define CAN1TDB1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x3C ) )
0753 #define CAN1TFI2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x40 ) )
0754 #define CAN1TID2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x44 ) )
0755 #define CAN1TDA2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x48 ) )
0756 #define CAN1TDB2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x4C ) )
0757 #define CAN1TFI3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x50 ) )
0758 #define CAN1TID3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x54 ) )
0759 #define CAN1TDA3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x58 ) )
0760 #define CAN1TDB3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x5C ) )
0761
0762 #define CAN2_BASE_ADDR 0x40048000
0763
0764 #define CAN2MOD ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x00 ) )
0765 #define CAN2CMR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x04 ) )
0766 #define CAN2GSR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x08 ) )
0767 #define CAN2ICR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x0C ) )
0768 #define CAN2IER ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x10 ) )
0769 #define CAN2BTR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x14 ) )
0770 #define CAN2EWL ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x18 ) )
0771 #define CAN2SR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x1C ) )
0772 #define CAN2RFS ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x20 ) )
0773 #define CAN2RID ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x24 ) )
0774 #define CAN2RDA ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x28 ) )
0775 #define CAN2RDB ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x2C ) )
0776
0777 #define CAN2TFI1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x30 ) )
0778 #define CAN2TID1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x34 ) )
0779 #define CAN2TDA1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x38 ) )
0780 #define CAN2TDB1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x3C ) )
0781 #define CAN2TFI2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x40 ) )
0782 #define CAN2TID2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x44 ) )
0783 #define CAN2TDA2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x48 ) )
0784 #define CAN2TDB2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x4C ) )
0785 #define CAN2TFI3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x50 ) )
0786 #define CAN2TID3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x54 ) )
0787 #define CAN2TDA3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x58 ) )
0788 #define CAN2TDB3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x5C ) )
0789
0790 /* MultiMedia Card Interface(MCI) Controller */
0791 #define MCI_BASE_ADDR 0x400c0000
0792
0793 #define MCI_POWER ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x00 ) )
0794 #define MCI_CLOCK ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x04 ) )
0795 #define MCI_ARGUMENT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x08 ) )
0796 #define MCI_COMMAND ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x0C ) )
0797 #define MCI_RESP_CMD ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x10 ) )
0798 #define MCI_RESP0 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x14 ) )
0799 #define MCI_RESP1 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x18 ) )
0800 #define MCI_RESP2 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x1C ) )
0801 #define MCI_RESP3 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x20 ) )
0802 #define MCI_DATA_TMR ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x24 ) )
0803 #define MCI_DATA_LEN ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x28 ) )
0804 #define MCI_DATA_CTRL ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x2C ) )
0805 #define MCI_DATA_CNT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x30 ) )
0806 #define MCI_STATUS ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x34 ) )
0807 #define MCI_CLEAR ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x38 ) )
0808 #define MCI_MASK0 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x3C ) )
0809 #define MCI_MASK1 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x40 ) )
0810 #define MCI_FIFO_CNT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x48 ) )
0811 #define MCI_FIFO ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x80 ) )
0812
0813 /* I2S Interface Controller (I2S) */
0814 #define I2S_BASE_ADDR 0x400a8000
0815
0816 #define I2S_DAO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x00 ) )
0817 #define I2S_DAI ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x04 ) )
0818 #define I2S_TX_FIFO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x08 ) )
0819 #define I2S_RX_FIFO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x0C ) )
0820 #define I2S_STATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x10 ) )
0821 #define I2S_DMA1 ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x14 ) )
0822 #define I2S_DMA2 ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x18 ) )
0823 #define I2S_IRQ ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x1C ) )
0824 #define I2S_TXRATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x20 ) )
0825 #define I2S_RXRATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x24 ) )
0826
0827 /* General-purpose DMA Controller */
0828 #define DMA_BASE_ADDR 0x50004000
0829
0830 #define GPDMA_INT_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x000 ) )
0831 #define GPDMA_INT_TCSTAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x004 ) )
0832 #define GPDMA_INT_TCCLR ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x008 ) )
0833 #define GPDMA_INT_ERR_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x00C ) )
0834 #define GPDMA_INT_ERR_CLR ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x010 ) )
0835 #define GPDMA_RAW_INT_TCSTAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + \
0836                                                         0x014 ) )
0837 #define GPDMA_RAW_INT_ERR_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + \
0838                                                           0x018 ) )
0839 #define GPDMA_ENABLED_CHNS ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x01C ) )
0840 #define GPDMA_SOFT_BREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x020 ) )
0841 #define GPDMA_SOFT_SREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x024 ) )
0842 #define GPDMA_SOFT_LBREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x028 ) )
0843 #define GPDMA_SOFT_LSREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x02C ) )
0844 #define GPDMA_CONFIG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x030 ) )
0845 #define GPDMA_SYNC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x034 ) )
0846
0847 /* DMA channel 0 registers */
0848 #define GPDMA_CH0_BASE_ADDR ( DMA_BASE_ADDR + 0x100 )
0849 #define GPDMA_CH0_SRC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x100 ) )
0850 #define GPDMA_CH0_DEST ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x104 ) )
0851 #define GPDMA_CH0_LLI ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x108 ) )
0852 #define GPDMA_CH0_CTRL ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x10C ) )
0853 #define GPDMA_CH0_CFG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x110 ) )
0854
0855 /* DMA channel 1 registers */
0856 #define GPDMA_CH1_BASE_ADDR ( DMA_BASE_ADDR + 0x120 )
0857 #define GPDMA_CH1_SRC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x120 ) )
0858 #define GPDMA_CH1_DEST ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x124 ) )
0859 #define GPDMA_CH1_LLI ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x128 ) )
0860 #define GPDMA_CH1_CTRL ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x12C ) )
0861 #define GPDMA_CH1_CFG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x130 ) )
0862
0863 /* USB Controller */
0864 #define USB_INT_BASE_ADDR 0x400fc1c0
0865 #define USB_BASE_ADDR 0x2008c200
0866
0867 #define USB_INT_STAT ( *(volatile uint32_t *) ( USB_INT_BASE_ADDR + 0x00 ) )
0868
0869 /* USB Device Interrupt Registers */
0870 #define DEV_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x00 ) )
0871 #define DEV_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x04 ) )
0872 #define DEV_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x08 ) )
0873 #define DEV_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x0C ) )
0874 #define DEV_INT_PRIO ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x2C ) )
0875
0876 /* USB Device Endpoint Interrupt Registers */
0877 #define EP_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x30 ) )
0878 #define EP_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x34 ) )
0879 #define EP_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x38 ) )
0880 #define EP_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x3C ) )
0881 #define EP_INT_PRIO ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x40 ) )
0882
0883 /* USB Device Endpoint Realization Registers */
0884 #define REALIZE_EP ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x44 ) )
0885 #define EP_INDEX ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x48 ) )
0886 #define MAXPACKET_SIZE ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x4C ) )
0887
0888 /* USB Device Command Reagisters */
0889 #define CMD_CODE ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x10 ) )
0890 #define CMD_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x14 ) )
0891
0892 /* USB Device Data Transfer Registers */
0893 #define RX_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x18 ) )
0894 #define TX_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x1C ) )
0895 #define RX_PLENGTH ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x20 ) )
0896 #define TX_PLENGTH ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x24 ) )
0897 #define USB_CTRL ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x28 ) )
0898
0899 /* USB Device DMA Registers */
0900 #define DMA_REQ_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x50 ) )
0901 #define DMA_REQ_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x54 ) )
0902 #define DMA_REQ_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x58 ) )
0903 #define UDCA_HEAD ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x80 ) )
0904 #define EP_DMA_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x84 ) )
0905 #define EP_DMA_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x88 ) )
0906 #define EP_DMA_DIS ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x8C ) )
0907 #define DMA_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x90 ) )
0908 #define DMA_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x94 ) )
0909 #define EOT_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA0 ) )
0910 #define EOT_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA4 ) )
0911 #define EOT_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA8 ) )
0912 #define NDD_REQ_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xAC ) )
0913 #define NDD_REQ_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB0 ) )
0914 #define NDD_REQ_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB4 ) )
0915 #define SYS_ERR_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB8 ) )
0916 #define SYS_ERR_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xBC ) )
0917 #define SYS_ERR_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xC0 ) )
0918
0919 /* USB Host Controller */
0920 #define USBHC_BASE_ADDR 0x2008c000
0921
0922 #define HC_REVISION ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x00 ) )
0923 #define HC_CONTROL ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x04 ) )
0924 #define HC_CMD_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x08 ) )
0925 #define HC_INT_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x0C ) )
0926 #define HC_INT_EN ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x10 ) )
0927 #define HC_INT_DIS ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x14 ) )
0928 #define HC_HCCA ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x18 ) )
0929 #define HC_PERIOD_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x1C ) )
0930 #define HC_CTRL_HEAD_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x20 ) )
0931 #define HC_CTRL_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x24 ) )
0932 #define HC_BULK_HEAD_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x28 ) )
0933 #define HC_BULK_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x2C ) )
0934 #define HC_DONE_HEAD ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x30 ) )
0935 #define HC_FM_INTERVAL ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x34 ) )
0936 #define HC_FM_REMAINING ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x38 ) )
0937 #define HC_FM_NUMBER ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x3C ) )
0938 #define HC_PERIOD_START ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x40 ) )
0939 #define HC_LS_THRHLD ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x44 ) )
0940 #define HC_RH_DESCA ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x48 ) )
0941 #define HC_RH_DESCB ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x4C ) )
0942 #define HC_RH_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x50 ) )
0943 #define HC_RH_PORT_STAT1 ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x54 ) )
0944 #define HC_RH_PORT_STAT2 ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x58 ) )
0945
0946 /* USB OTG Controller */
0947 #define USBOTG_BASE_ADDR 0x2008c100
0948
0949 #define OTG_INT_STAT ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x00 ) )
0950 #define OTG_INT_EN ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x04 ) )
0951 #define OTG_INT_SET ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x08 ) )
0952 #define OTG_INT_CLR ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x0C ) )
0953 #define OTG_STAT_CTRL ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x10 ) )
0954 #define OTG_TIMER ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x14 ) )
0955
0956 #define USBOTG_I2C_BASE_ADDR 0x2008c300
0957
0958 #define OTG_I2C_RX ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x00 ) )
0959 #define OTG_I2C_TX ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x00 ) )
0960 #define OTG_I2C_STS ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x04 ) )
0961 #define OTG_I2C_CTL ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x08 ) )
0962 #define OTG_I2C_CLKHI ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + \
0963                                                  0x0C ) )
0964 #define OTG_I2C_CLKLO ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + \
0965                                                  0x10 ) )
0966
0967 #define USBOTG_CLK_BASE_ADDR 0x2008CFF0U
0968
0969 #define OTG_CLK_CTRL ( *(volatile uint32_t *) ( USBOTG_CLK_BASE_ADDR + \
0970                                                 0x04U ) )
0971 #define OTG_CLK_STAT ( *(volatile uint32_t *) ( USBOTG_CLK_BASE_ADDR + \
0972                                                 0x08U ) )
0973
0974 /* Register Fields */
0975 #define GET_FIELD( val, mask, shift ) \
0976   ( ( ( val ) & ( mask ) ) >> ( shift ) )
0977
0978 #define SET_FIELD( val, field, mask, shift ) \
0979   ( ( ( val ) & ~( mask ) ) | ( ( ( field ) << ( shift ) ) & ( mask ) ) )
0980
0981 /* CLKSRCSEL */
0982 #define CLKSRCSEL_CLKSRC_MASK 0x00000003U
0983
0984 #define GET_CLKSRCSEL_CLKSRC( reg ) \
0985   GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0 )
0986
0987 #define SET_CLKSRCSEL_CLKSRC( reg, val ) \
0988   SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0 )
0989
0990 /* PLLCON */
0991 #define PLLCON_PLLE 0x00000001U
0992
0993 #define PLLCON_PLLC 0x00000002U
0994
0995 /* PLLCFG */
0996 #define PLLCFG_MSEL_MASK 0x00007fffU
0997
0998 #define GET_PLLCFG_MSEL( reg ) \
0999   GET_FIELD( reg, PLLCFG_MSEL_MASK, 0 )
1000
1001 #define SET_PLLCFG_MSEL( reg, val ) \
1002   SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0 )
1003
1004 #define PLLCFG_NSEL_MASK 0x00ff0000U
1005
1006 #define GET_PLLCFG_NSEL( reg ) \
1007   GET_FIELD( reg, PLLCFG_NSEL_MASK, 16 )
1008
1009 #define SET_PLLCFG_NSEL( reg, val ) \
1010   SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16 )
1011
1012 /* PLLSTAT */
1013 #define PLLSTAT_MSEL_MASK 0x00007fffU
1014
1015 #define GET_PLLSTAT_MSEL( reg ) \
1016   GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0 )
1017
1018 #define SET_PLLSTAT_MSEL( reg, val ) \
1019   SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0 )
1020
1021 #define PLLSTAT_NSEL_MASK 0x00ff0000U
1022
1023 #define GET_PLLSTAT_NSEL( reg ) \
1024   GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16 )
1025
1026 #define SET_PLLSTAT_NSEL( reg, val ) \
1027   SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16 )
1028
1029 #define PLLSTAT_PLLE 0x01000000U
1030
1031 #define PLLSTAT_PLLC 0x02000000U
1032
1033 #define PLLSTAT_PLOCK 0x04000000U
1034
1035 /* CCLKCFG */
1036 #define CCLKCFG_CCLKSEL_MASK 0x000000ffU
1037
1038 #define GET_CCLKCFG_CCLKSEL( reg ) \
1039   GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0 )
1040
1041 #define SET_CCLKCFG_CCLKSEL( reg, val ) \
1042   SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0 )
1043
1044 /* MEMMAP */
1045 #define MEMMAP_MAP_MASK 0x00000003U
1046
1047 #define GET_MEMMAP_MAP( reg ) \
1048   GET_FIELD( reg, MEMMAP_MAP_MASK, 0 )
1049
1050 #define SET_MEMMAP_MAP( reg, val ) \
1051   SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0 )
1052
1053 /* TIR */
1054 #define TIR_MR0 0x00000001U
1055 #define TIR_MR1 0x00000002U
1056 #define TIR_MR2 0x00000004U
1057 #define TIR_MR3 0x00000008U
1058 #define TIR_CR0 0x00000010U
1059 #define TIR_CR1 0x00000020U
1060 #define TIR_CR2 0x00000040U
1061 #define TIR_CR3 0x00000080U
1062
1063 /* TCR */
1064 #define TCR_EN 0x00000001U
1065 #define TCR_RST 0x00000002U
1066
1067 /* TMCR */
1068 #define TMCR_MR0I 0x00000001U
1069 #define TMCR_MR0R 0x00000002U
1070 #define TMCR_MR0S 0x00000004U
1071 #define TMCR_MR1I 0x00000008U
1072 #define TMCR_MR1R 0x00000010U
1073 #define TMCR_MR1S 0x00000020U
1074 #define TMCR_MR2I 0x00000040U
1075 #define TMCR_MR2R 0x00000080U
1076 #define TMCR_MR2S 0x00000100U
1077 #define TMCR_MR3I 0x00000200U
1078 #define TMCR_MR3R 0x00000400U
1079 #define TMCR_MR3S 0x00000800U
1080
1081 /* PCLKSEL0 */
1082 #define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
1083
1084 #define GET_PCLKSEL0_PCLK_WDT( reg ) \
1085   GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0 )
1086
1087 #define SET_PCLKSEL0_PCLK_WDT( reg, val ) \
1088   SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0 )
1089
1090 #define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
1091
1092 #define GET_PCLKSEL0_PCLK_TIMER0( reg ) \
1093   GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2 )
1094
1095 #define SET_PCLKSEL0_PCLK_TIMER0( reg, val ) \
1096   SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2 )
1097
1098 #define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
1099
1100 #define GET_PCLKSEL0_PCLK_TIMER1( reg ) \
1101   GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4 )
1102
1103 #define SET_PCLKSEL0_PCLK_TIMER1( reg, val ) \
1104   SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4 )
1105
1106 #define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
1107
1108 #define GET_PCLKSEL0_PCLK_UART0( reg ) \
1109   GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6 )
1110
1111 #define SET_PCLKSEL0_PCLK_UART0( reg, val ) \
1112   SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6 )
1113
1114 #define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
1115
1116 #define GET_PCLKSEL0_PCLK_UART1( reg ) \
1117   GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8 )
1118
1119 #define SET_PCLKSEL0_PCLK_UART1( reg, val ) \
1120   SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8 )
1121
1122 #define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
1123
1124 #define GET_PCLKSEL0_PCLK_PWM0( reg ) \
1125   GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10 )
1126
1127 #define SET_PCLKSEL0_PCLK_PWM0( reg, val ) \
1128   SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10 )
1129
1130 #define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
1131
1132 #define GET_PCLKSEL0_PCLK_PWM1( reg ) \
1133   GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12 )
1134
1135 #define SET_PCLKSEL0_PCLK_PWM1( reg, val ) \
1136   SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12 )
1137
1138 #define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
1139
1140 #define GET_PCLKSEL0_PCLK_I2C0( reg ) \
1141   GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14 )
1142
1143 #define SET_PCLKSEL0_PCLK_I2C0( reg, val ) \
1144   SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14 )
1145
1146 #define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
1147
1148 #define GET_PCLKSEL0_PCLK_SPI( reg ) \
1149   GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16 )
1150
1151 #define SET_PCLKSEL0_PCLK_SPI( reg, val ) \
1152   SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16 )
1153
1154 #define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
1155
1156 #define GET_PCLKSEL0_PCLK_RTC( reg ) \
1157   GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18 )
1158
1159 #define SET_PCLKSEL0_PCLK_RTC( reg, val ) \
1160   SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18 )
1161
1162 #define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
1163
1164 #define GET_PCLKSEL0_PCLK_SSP1( reg ) \
1165   GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20 )
1166
1167 #define SET_PCLKSEL0_PCLK_SSP1( reg, val ) \
1168   SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20 )
1169
1170 #define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
1171
1172 #define GET_PCLKSEL0_PCLK_DAC( reg ) \
1173   GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22 )
1174
1175 #define SET_PCLKSEL0_PCLK_DAC( reg, val ) \
1176   SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22 )
1177
1178 #define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
1179
1180 #define GET_PCLKSEL0_PCLK_ADC( reg ) \
1181   GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24 )
1182
1183 #define SET_PCLKSEL0_PCLK_ADC( reg, val ) \
1184   SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24 )
1185
1186 #define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
1187
1188 #define GET_PCLKSEL0_PCLK_CAN1( reg ) \
1189   GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26 )
1190
1191 #define SET_PCLKSEL0_PCLK_CAN1( reg, val ) \
1192   SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26 )
1193
1194 #define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
1195
1196 #define GET_PCLKSEL0_PCLK_CAN2( reg ) \
1197   GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28 )
1198
1199 #define SET_PCLKSEL0_PCLK_CAN2( reg, val ) \
1200   SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28 )
1201
1202 /* PCLKSEL1 */
1203 #define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
1204
1205 #define GET_PCLKSEL1_PCLK_BAT_RAM( reg ) \
1206   GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0 )
1207
1208 #define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val ) \
1209   SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0 )
1210
1211 #define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
1212
1213 #define GET_PCLKSEL1_PCLK_GPIO( reg ) \
1214   GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2 )
1215
1216 #define SET_PCLKSEL1_PCLK_GPIO( reg, val ) \
1217   SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2 )
1218
1219 #define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
1220
1221 #define GET_PCLKSEL1_PCLK_PCB( reg ) \
1222   GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4 )
1223
1224 #define SET_PCLKSEL1_PCLK_PCB( reg, val ) \
1225   SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4 )
1226
1227 #define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
1228
1229 #define GET_PCLKSEL1_PCLK_I2C1( reg ) \
1230   GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6 )
1231
1232 #define SET_PCLKSEL1_PCLK_I2C1( reg, val ) \
1233   SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6 )
1234
1235 #define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
1236
1237 #define GET_PCLKSEL1_PCLK_SSP0( reg ) \
1238   GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10 )
1239
1240 #define SET_PCLKSEL1_PCLK_SSP0( reg, val ) \
1241   SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10 )
1242
1243 #define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
1244
1245 #define GET_PCLKSEL1_PCLK_TIMER2( reg ) \
1246   GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12 )
1247
1248 #define SET_PCLKSEL1_PCLK_TIMER2( reg, val ) \
1249   SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12 )
1250
1251 #define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
1252
1253 #define GET_PCLKSEL1_PCLK_TIMER3( reg ) \
1254   GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14 )
1255
1256 #define SET_PCLKSEL1_PCLK_TIMER3( reg, val ) \
1257   SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14 )
1258
1259 #define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
1260
1261 #define GET_PCLKSEL1_PCLK_UART2( reg ) \
1262   GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16 )
1263
1264 #define SET_PCLKSEL1_PCLK_UART2( reg, val ) \
1265   SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16 )
1266
1267 #define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
1268
1269 #define GET_PCLKSEL1_PCLK_UART3( reg ) \
1270   GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18 )
1271
1272 #define SET_PCLKSEL1_PCLK_UART3( reg, val ) \
1273   SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18 )
1274
1275 #define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
1276
1277 #define GET_PCLKSEL1_PCLK_I2C2( reg ) \
1278   GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20 )
1279
1280 #define SET_PCLKSEL1_PCLK_I2C2( reg, val ) \
1281   SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20 )
1282
1283 #define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
1284
1285 #define GET_PCLKSEL1_PCLK_I2S( reg ) \
1286   GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22 )
1287
1288 #define SET_PCLKSEL1_PCLK_I2S( reg, val ) \
1289   SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22 )
1290
1291 #define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
1292
1293 #define GET_PCLKSEL1_PCLK_MCI( reg ) \
1294   GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24 )
1295
1296 #define SET_PCLKSEL1_PCLK_MCI( reg, val ) \
1297   SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24 )
1298
1299 #define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
1300
1301 #define GET_PCLKSEL1_PCLK_SYSCON( reg ) \
1302   GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28 )
1303
1304 #define SET_PCLKSEL1_PCLK_SYSCON( reg, val ) \
1305   SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28 )
1306
1307 /* RTC_ILR */
1308 #define RTC_ILR_RTCCIF 0x00000001U
1309 #define RTC_ILR_RTCALF 0x00000002U
1310 #define RTC_ILR_RTSSF 0x00000004U
1311
1312 /* RTC_CCR */
1313 #define RTC_CCR_CLKEN 0x00000001U
1314 #define RTC_CCR_CTCRST 0x00000002U
1315 #define RTC_CCR_CLKSRC 0x00000010U
1316
1317 /* GPDMA */
1318 typedef struct {
1319   uint32_t src;
1320   uint32_t dest;
1321   uint32_t lli;
1322   uint32_t ctrl;
1323 } lpc176x_dma_descriptor;
1324
1325 typedef struct {
1326   lpc176x_dma_descriptor desc;
1327   uint32_t cfg;
1328 } lpc176x_dma_channel;
1329
1330 #define GPDMA_CH_NUMBER 2
1331 #define GPDMA_STATUS_CH_0 0x00000001U
1332 #define GPDMA_STATUS_CH_1 0x00000002U
1333 #define GPDMA_CH_BASE_ADDR( i ) \
1334   ( (volatile lpc176x_dma_channel *) \
1335     ( ( i ) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR ) )
1336
1337 /* GPDMA_CONFIG */
1338 #define GPDMA_CONFIG_EN 0x00000001U
1339 #define GPDMA_CONFIG_MODE 0x00000002U
1340
1341 /* GPDMA_ENABLED_CHNS */
1342 #define GPDMA_ENABLED_CHNS_CH0 0x00000001U
1343 #define GPDMA_ENABLED_CHNS_CH1 0x00000002U
1344
1345 /* GPDMA_CH_CTRL */
1346 #define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
1347
1348 #define GET_GPDMA_CH_CTRL_TSZ( reg ) \
1349   GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0 )
1350
1351 #define SET_GPDMA_CH_CTRL_TSZ( reg, val ) \
1352   SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0 )
1353
1354 #define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
1355
1356 #define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
1357
1358 #define GET_GPDMA_CH_CTRL_SBSZ( reg ) \
1359   GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12 )
1360
1361 #define SET_GPDMA_CH_CTRL_SBSZ( reg, val ) \
1362   SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12 )
1363
1364 #define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
1365
1366 #define GET_GPDMA_CH_CTRL_DBSZ( reg ) \
1367   GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15 )
1368
1369 #define SET_GPDMA_CH_CTRL_DBSZ( reg, val ) \
1370   SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15 )
1371
1372 #define GPDMA_CH_CTRL_BSZ_1 0x00000000U
1373
1374 #define GPDMA_CH_CTRL_BSZ_4 0x00000001U
1375
1376 #define GPDMA_CH_CTRL_BSZ_8 0x00000002U
1377
1378 #define GPDMA_CH_CTRL_BSZ_16 0x00000003U
1379
1380 #define GPDMA_CH_CTRL_BSZ_32 0x00000004U
1381
1382 #define GPDMA_CH_CTRL_BSZ_64 0x00000005U
1383
1384 #define GPDMA_CH_CTRL_BSZ_128 0x00000006U
1385
1386 #define GPDMA_CH_CTRL_BSZ_256 0x00000007U
1387
1388 #define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
1389
1390 #define GET_GPDMA_CH_CTRL_SW( reg ) \
1391   GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18 )
1392
1393 #define SET_GPDMA_CH_CTRL_SW( reg, val ) \
1394   SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18 )
1395
1396 #define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
1397
1398 #define GET_GPDMA_CH_CTRL_DW( reg ) \
1399   GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21 )
1400
1401 #define SET_GPDMA_CH_CTRL_DW( reg, val ) \
1402   SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21 )
1403
1404 #define GPDMA_CH_CTRL_W_8 0x00000000U
1405
1406 #define GPDMA_CH_CTRL_W_16 0x00000001U
1407
1408 #define GPDMA_CH_CTRL_W_32 0x00000002U
1409
1410 #define GPDMA_CH_CTRL_SI 0x04000000U
1411
1412 #define GPDMA_CH_CTRL_DI 0x08000000U
1413
1414 #define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
1415
1416 #define GET_GPDMA_CH_CTRL_PROT( reg ) \
1417   GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28 )
1418
1419 #define SET_GPDMA_CH_CTRL_PROT( reg, val ) \
1420   SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28 )
1421
1422 #define GPDMA_CH_CTRL_ITC 0x80000000U
1423
1424 /* GPDMA_CH_CFG */
1425 #define GPDMA_CH_CFG_EN 0x00000001U
1426
1427 #define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
1428
1429 #define GET_GPDMA_CH_CFG_SRCPER( reg ) \
1430   GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1 )
1431
1432 #define SET_GPDMA_CH_CFG_SRCPER( reg, val ) \
1433   SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1 )
1434
1435 #define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
1436
1437 #define GET_GPDMA_CH_CFG_DESTPER( reg ) \
1438   GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6 )
1439
1440 #define SET_GPDMA_CH_CFG_DESTPER( reg, val ) \
1441   SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6 )
1442
1443 #define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
1444
1445 #define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U
1446
1447 #define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U
1448
1449 #define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U
1450
1451 #define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U
1452
1453 #define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U
1454
1455 #define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U
1456
1457 #define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
1458
1459 #define GET_GPDMA_CH_CFG_FLOW( reg ) \
1460   GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11 )
1461
1462 #define SET_GPDMA_CH_CFG_FLOW( reg, val ) \
1463   SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11 )
1464
1465 #define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
1466
1467 #define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U
1468
1469 #define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U
1470
1471 #define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U
1472
1473 #define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U
1474
1475 #define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U
1476
1477 #define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U
1478
1479 #define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U
1480
1481 #define GPDMA_CH_CFG_IE 0x00004000U
1482
1483 #define GPDMA_CH_CFG_ITC 0x00008000U
1484
1485 #define GPDMA_CH_CFG_LOCK 0x00010000U
1486
1487 #define GPDMA_CH_CFG_ACTIVE 0x00020000U
1488
1489 #define GPDMA_CH_CFG_HALT 0x00040000U
1490
1491 /* AHBCFG */
1492 #define AHBCFG_SCHEDULER_UNIFORM 0x00000001U
1493
1494 #define AHBCFG_BREAK_BURST_MASK 0x00000006U
1495
1496 #define GET_AHBCFG_BREAK_BURST( reg ) \
1497   GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1 )
1498
1499 #define SET_AHBCFG_BREAK_BURST( reg, val ) \
1500   SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1 )
1501
1502 #define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
1503
1504 #define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
1505
1506 #define GET_AHBCFG_QUANTUM_SIZE( reg ) \
1507   GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4 )
1508
1509 #define SET_AHBCFG_QUANTUM_SIZE( reg, val ) \
1510   SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4 )
1511
1512 #define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
1513
1514 #define GET_AHBCFG_DEFAULT_MASTER( reg ) \
1515   GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8 )
1516
1517 #define SET_AHBCFG_DEFAULT_MASTER( reg, val ) \
1518   SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8 )
1519
1520 #define AHBCFG_EP1_MASK 0x00007000U
1521
1522 #define GET_AHBCFG_EP1( reg ) \
1523   GET_FIELD( reg, AHBCFG_EP1_MASK, 12 )
1524
1525 #define SET_AHBCFG_EP1( reg, val ) \
1526   SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12 )
1527
1528 #define AHBCFG_EP2_MASK 0x00070000U
1529
1530 #define GET_AHBCFG_EP2( reg ) \
1531   GET_FIELD( reg, AHBCFG_EP2_MASK, 16 )
1532
1533 #define SET_AHBCFG_EP2( reg, val ) \
1534   SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16 )
1535
1536 #define AHBCFG_EP3_MASK 0x00700000U
1537
1538 #define GET_AHBCFG_EP3( reg ) \
1539   GET_FIELD( reg, AHBCFG_EP3_MASK, 20 )
1540
1541 #define SET_AHBCFG_EP3( reg, val ) \
1542   SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20 )
1543
1544 #define AHBCFG_EP4_MASK 0x07000000U
1545
1546 #define GET_AHBCFG_EP4( reg ) \
1547   GET_FIELD( reg, AHBCFG_EP4_MASK, 24 )
1548
1549 #define SET_AHBCFG_EP4( reg, val ) \
1550   SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24 )
1551
1552 #define AHBCFG_EP5_MASK 0x70000000U
1553
1554 #define GET_AHBCFG_EP5( reg ) \
1555   GET_FIELD( reg, AHBCFG_EP5_MASK, 28 )
1556
1557 #define SET_AHBCFG_EP5( reg, val ) \
1558   SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28 )
1559
1560 /* I2S */
1561 static volatile lpc_i2s * const lpc176x_i2s = (lpc_i2s *) I2S_BASE_ADDR;
1562
1563 /* ADC */
1564 #define ADC_CR_SEL( val ) BSP_FLD32( val, 0, 7 )
1565 #define ADC_CR_SEL_GET( val ) BSP_FLD32GET( val, 0, 7 )
1566 #define ADC_CR_SEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 7 )
1567 #define ADC_CR_CLKDIV( val ) BSP_FLD32( val, 8, 15 )
1568 #define ADC_CR_CLKDIV_GET( reg ) BSP_FLD32GET( reg, 8, 15 )
1569 #define ADC_CR_CLKDIV_SET( reg, val ) BSP_FLD32SET( reg, val, 8, 15 )
1570 #define ADC_CR_BURST BSP_BIT32( 16 )
1571 #define ADC_CR_CLKS( val ) BSP_FLD32( val, 17, 19 )
1572 #define ADC_CR_PDN BSP_BIT32( 21 )
1573 #define ADC_CR_START( val ) BSP_FLD32( val, 24, 26 )
1574 #define ADC_CR_EDGE BSP_BIT32( 27 )
1575
1576 #define ADC_DR_VALUE( reg ) BSP_FLD32GET( reg, 6, 15 )
1577 #define ADC_DR_OVERRUN BSP_BIT32( 30 )
1578 #define ADC_DR_DONE BSP_BIT32( 31 )
1579
1580 /* DAC */
1581 #define DAC_STEPS 1024
1582 #define DAC_VALUE( val ) BSP_FLD32( val, 6, 15 )
1583 #define DAC_BIAS BSP_BIT32( 16 )
1584
1585 #endif /* LIBBSP_ARM_LPC176X_H */