include/bsp/gpio-defs.h

0001 /**
0002  * @file
0003  *
0004  * @ingroup RTEMSBSPsARMLPC176X
0005  *
0006  * @brief API definitions of the GPIO driver for the lpc176x bsp in RTEMS.
0007  */
0008
0009 /*
0010  * Copyright (c) 2014 Taller Technologies.
0011  *
0012  * @author  Boretto Martin    (martin.boretto@tallertechnologies.com)
0013  * @author  Diaz Marcos (marcos.diaz@tallertechnologies.com)
0014  * @author  Lenarduzzi Federico  (federico.lenarduzzi@tallertechnologies.com)
0015  * @author  Daniel Chicco  (daniel.chicco@tallertechnologies.com)
0016  *
0017  * The license and distribution terms for this file may be
0018  * found in the file LICENSE in this distribution or at
0019  * http://www.rtems.org/license/LICENSE.
0020  */
0021
0022 #ifndef LIBBSP_ARM_LPC176X_GPIO_DEFS_H
0023 #define LIBBSP_ARM_LPC176X_GPIO_DEFS_H
0024
0025 #include <bsp/common-types.h>
0026
0027 #ifdef __cplusplus
0028 extern "C" {
0029 #endif /* __cplusplus */
0030
0031 /* General Purpose Input/Output (GPIO) */
0032 #define LPC176X_GPIO_BASE_ADDR 0x40028000U
0033 #define LPC176X_GPIO_INTERRUPT_STATUS 0x40028080U
0034
0035 #define LPC176X_IOPIN0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
0036                                                   0x00U ) )
0037 #define LPC176X_IOSET0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
0038                                                   0x04U ) )
0039 #define LPC176X_IODIR0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
0040                                                   0x08U ) )
0041 #define LPC176X_IOCLR0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
0042                                                   0x0CU ) )
0043 #define LPC176X_IOPIN1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
0044                                                   0x10U ) )
0045 #define LPC176X_IOSET1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
0046                                                   0x14U ) )
0047 #define LPC176X_IODIR1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
0048                                                   0x18U ) )
0049 #define LPC176X_IOCLR1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \
0050                                                   0x1CU ) )
0051
0052 /* GPIO Interrupt Registers */
0053 #define LPC176X_IO0_INT_EN_R ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
0054                                                         + 0x90U ) )
0055 #define LPC176X_IO0_INT_EN_F ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
0056                                                         + 0x94U ) )
0057 #define LPC176X_IO0_INT_STAT_R ( *(volatile uint32_t *) ( \
0058                                    LPC176X_GPIO_BASE_ADDR \
0059                                    + 0x84U ) )
0060 #define LPC176X_IO0_INT_STAT_F ( *(volatile uint32_t *) ( \
0061                                    LPC176X_GPIO_BASE_ADDR \
0062                                    + 0x88U ) )
0063 #define LPC176X_IO0_INT_CLR ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
0064                                                        + 0x8CU ) )
0065 #define LPC176X_IO2_INT_EN_R ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
0066                                                         + 0xB0U ) )
0067 #define LPC176X_IO2_INT_EN_F ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
0068                                                         + 0xB4U ) )
0069 #define LPC176X_IO2_INT_STAT_R ( *(volatile uint32_t *) ( \
0070                                    LPC176X_GPIO_BASE_ADDR \
0071                                    + 0xA4U ) )
0072 #define LPC176X_IO2_INT_STAT_F ( *(volatile uint32_t *) ( \
0073                                    LPC176X_GPIO_BASE_ADDR \
0074                                    + 0xA8U ) )
0075 #define LPC176X_IO2_INT_CLR ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
0076                                                        + 0xACU ) )
0077 #define LPC176X_IO_INT_STAT ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \
0078                                                        + 0x80U ) )
0079
0080 #define LPC176X_RESERVED_ISR_FUNCT_SIZE 2U
0081 #define LPC176X_RESERVED_ISR_FUNCT_MAX_SIZE 5U
0082
0083 #define LPC176X_MAX_PORT_NUMBER 160U
0084 #define LPC176X_SET_BIT( reg, pin, value ) \
0085   reg = ( reg & ~( 1U << pin ) ) | ( ( value & 1U ) << pin )
0086
0087 #define LPC176X_INT_STATUS ( *(volatile uint32_t *) \
0088                              ( LPC176X_GPIO_INTERRUPT_STATUS ) )
0089 #define LPC176X_INT_STATUS_P0 1U
0090 #define LPC176X_INT_STATUS_P2 ( 1U << 2U )
0091 #define LPC176X_INT_ENABLE 1U
0092 #define LPC176X_INT_DISABLE 0U
0093
0094 #define LPC176X_IRQ_EINT_3 21U
0095
0096 #define LPC176X_PIN_BIT( pin ) ( 1U << pin )
0097
0098 /**
0099  * @brief The direction of the GPIO port (input or output).
0100  *
0101  * Enumerated type to define the set of function types for a gpio device.
0102  */
0103 typedef enum {
0104   LPC176X_GPIO_FUNCTION_INPUT,
0105   LPC176X_GPIO_FUNCTION_OUTPUT,
0106   LPC176X_GPIO_FUNCTION_COUNT
0107 }
0108 lpc176x_gpio_direction;
0109
0110 /**
0111  * @brief The interrupt sources edge for a GPIO.
0112  *
0113  * Enumerated type to define the set of interrupt types for a gpio device.
0114  */
0115 typedef enum {
0116   LPC176X_GPIO_INTERRUPT_DISABLE,
0117   LPC176X_GPIO_INTERRUPT_RISING,
0118   LPC176X_GPIO_INTERRUPT_FALLING,
0119   LPC176X_GPIO_INTERRUPT_BOTH,
0120   LPC176X_GPIO_INTERRUPT_COUNT
0121 } lpc176x_gpio_interrupt;
0122
0123 /**
0124  * @brief The ports for a GPIO.
0125  *
0126  * Enumerated type to define the set of ports for a gpio device.
0127  */
0128 typedef enum {
0129   LPC176X_GPIO_PORT_0,
0130   LPC176X_GPIO_PORT_1,
0131   LPC176X_GPIO_PORT_2,
0132   LPC176X_GPIO_PORT_3,
0133   LPC176X_GPIO_PORT_4,
0134   LPC176X_GPIO_PORTS_COUNT
0135 } lpc176x_gpio_ports;
0136
0137 /**
0138  * @brief Addresses for a GPIO.
0139  *
0140  * Enumerated type to define the set of fio bases addresses
0141  *     for a gpio device.
0142  */
0143 typedef enum {
0144   LPC176X_FIO0_BASE_ADDRESS = 0x2009C000U,
0145   LPC176X_FIO1_BASE_ADDRESS = 0x2009C020U,
0146   LPC176X_FIO2_BASE_ADDRESS = 0x2009C040U,
0147   LPC176X_FIO3_BASE_ADDRESS = 0x2009C060U,
0148   LPC176X_FIO4_BASE_ADDRESS = 0x2009C080U,
0149 } lpc176x_gpio_address;
0150
0151 /**
0152  * @brief Addresses for the two interrupts.
0153  *
0154  * Enumerated type to define the set of interrupt addresses
0155  *     for a gpio device.
0156  */
0157 typedef enum {
0158   LPC176X_IO0_INT_BASE_ADDRESS = 0x40028084U,
0159   LPC176X_IO2_INT_BASE_ADDRESS = 0x400280A4U,
0160 } lpc176x_interrupt_address;
0161
0162 /**
0163  * @brief GPIO Interrupt register map.
0164  */
0165 typedef struct {
0166   /**
0167    * @brief Interrupt Enable for Rising edge.
0168    */
0169   volatile uint32_t StatR;
0170   /**
0171    * @brief Interrupt Enable for Falling edge.
0172    */
0173   volatile uint32_t StatF;
0174   /**
0175    * @brief Interrupt Clear.
0176    */
0177   volatile uint32_t Clr;
0178   /**
0179    * @brief Interrupt Enable for Rising edge.
0180    */
0181   volatile uint32_t EnR;
0182   /**
0183    * @brief Interrupt Enable for Falling edge.
0184    */
0185   volatile uint32_t EnF;
0186 } lpc176x_interrupt_control;
0187
0188 /**
0189  * @brief A function that attends an interrupt for GPIO.
0190  *
0191  * @param  pin Pin number.
0192  * @param edge Interrupt.
0193  * @return Pointer to the interrupt function.
0194  */
0195 typedef void (*lpc176x_gpio_interrupt_function) (
0196   const lpc176x_pin_number     pin,
0197   const lpc176x_gpio_interrupt edge
0198 );
0199
0200 /**
0201  * @brief A registered interrupt function for the pin 'pin'.
0202  */
0203 typedef struct {
0204   /**
0205    * @brief Pin board.
0206    */
0207   lpc176x_pin_number pin;
0208   /**
0209    * @brief A function that attends an interrupt for 'pin'.
0210    */
0211   lpc176x_gpio_interrupt_function function;
0212 } lpc176x_registered_interrupt_function;
0213
0214 #ifdef __cplusplus
0215 }
0216 #endif /* __cplusplus */
0217
0218 #endif /* LIBBSP_ARM_LPC176X_GPIO_DEFS_H */