lm3s69xx/start/syscon.c

0001 /*
0002  * Copyright (c) 2013 Eugeniy Meshcheryakov <eugen@debian.org>
0003  *
0004  * The license and distribution terms for this file may be
0005  * found in the file LICENSE in this distribution or at
0006  * http://www.rtems.org/license/LICENSE.
0007  */
0008
0009 #include <bsp/syscon.h>
0010 #include <bsp/lm3s69xx.h>
0011 #include <rtems.h>
0012
0013 static void delay_3_clocks(void)
0014 {
0015   asm volatile(
0016       "nop\n\t"
0017       "nop\n\t"
0018       "nop");
0019 }
0020
0021 void __attribute__((naked)) lm3s69xx_syscon_delay_3x_clocks(unsigned long x_count)
0022 {
0023     asm volatile(
0024                  "subs  r0, #1\n\t"
0025                  "bne   lm3s69xx_syscon_delay_3x_clocks\n\t"
0026                  "bx    lr"
0027                  );
0028 }
0029
0030 void lm3s69xx_syscon_enable_gpio_clock(unsigned int port, bool enable)
0031 {
0032   volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
0033   uint32_t mask = 1 << port;
0034   rtems_interrupt_level level;
0035
0036   rtems_interrupt_disable(level);
0037
0038   if (enable)
0039     syscon->rcgc2 |= mask;
0040   else
0041     syscon->rcgc2 &= ~mask;
0042
0043   delay_3_clocks();
0044
0045   rtems_interrupt_enable(level);
0046 }
0047
0048 void lm3s69xx_syscon_enable_uart_clock(unsigned int port, bool enable)
0049 {
0050   volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
0051   uint32_t mask = 1 << port;
0052   rtems_interrupt_level level;
0053
0054   rtems_interrupt_disable(level);
0055
0056   if (enable)
0057     syscon->rcgc1 |= mask;
0058   else
0059     syscon->rcgc1 &= ~mask;
0060
0061   delay_3_clocks();
0062
0063   rtems_interrupt_enable(level);
0064 }
0065
0066 void lm3s69xx_syscon_enable_ssi_clock(unsigned int port, bool enable)
0067 {
0068   volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
0069   uint32_t mask = 1 << (port + 4);
0070   rtems_interrupt_level level;
0071
0072   rtems_interrupt_disable(level);
0073
0074   if (enable)
0075     syscon->rcgc1 |= mask;
0076   else
0077     syscon->rcgc1 &= ~mask;
0078
0079   delay_3_clocks();
0080
0081   rtems_interrupt_enable(level);
0082 }
0083
0084 void lm3s69xx_syscon_enable_pwm_clock(bool enable)
0085 {
0086   volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
0087   rtems_interrupt_level level;
0088
0089   rtems_interrupt_disable(level);
0090
0091   if (enable)
0092     syscon->rcgc0 |= SYSCONRCGC0_PWM;
0093   else
0094     syscon->rcgc0 &= ~SYSCONRCGC0_PWM;
0095
0096   delay_3_clocks();
0097
0098   rtems_interrupt_enable(level);
0099 }
0100
0101 /**
0102  * Sets PWMDIV field in the RCC register.
0103  *
0104  * @note div should be one of SCRCC_PWMDIV_DIV?_VAL constants.
0105  */
0106 void lm3s69xx_syscon_set_pwmdiv(unsigned int div)
0107 {
0108   volatile lm3s69xx_syscon *syscon = LM3S69XX_SYSCON;
0109   rtems_interrupt_level level;
0110
0111   rtems_interrupt_disable(level);
0112   syscon->rcc = (syscon->rcc & ~SYSCONRCC_PWMDIV_MSK) | SYSCONRCC_PWMDIV(div)
0113       | SYSCONRCC_USEPWMDIV;
0114   rtems_interrupt_enable(level);
0115 }