Back to home page

LXR

 
 

    


Warning, /bsps/arm/lm3s69xx/0003-target-arm-Evil-hack-for-BASEPRI-and-BASEPRI_MAX.patch is written in an unsupported language. File is not indexed.

0001 From 78e85bb79c02b14170c3f39d9bb9cccd4d625890 Mon Sep 17 00:00:00 2001
0002 From: Sebastian Huber <sebastian.huber@embedded-brains.de>
0003 Date: Fri, 16 Dec 2011 20:12:29 +0100
0004 Subject: [PATCH 3/4] target-arm: Evil hack for BASEPRI and BASEPRI_MAX
0005 
0006 This is only a quick and dirty fix to get the ARMv7-M BASEPRI and
0007 BASEPRI_MAX feature working.
0008 
0009 Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
0010 ---
0011  cpu-exec.c          |    4 ++--
0012  target-arm/helper.c |   12 +++++-------
0013  2 files changed, 7 insertions(+), 9 deletions(-)
0014 
0015 diff --git a/cpu-exec.c b/cpu-exec.c
0016 index a9fa608..6ca9aab 100644
0017 --- a/cpu-exec.c
0018 +++ b/cpu-exec.c
0019 @@ -408,8 +408,8 @@ int cpu_exec(CPUState *env)
0020                         We avoid this by disabling interrupts when
0021                         pc contains a magic address.  */
0022                      if (interrupt_request & CPU_INTERRUPT_HARD
0023 -                        && ((IS_M(env) && env->regs[15] < 0xfffffff0)
0024 -                            || !(env->uncached_cpsr & CPSR_I))) {
0025 +                        && !(env->uncached_cpsr & CPSR_I)
0026 +                        && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
0027                          env->exception_index = EXCP_IRQ;
0028                          do_interrupt(env);
0029                          next_tb = 0;
0030 diff --git a/target-arm/helper.c b/target-arm/helper.c
0031 index 65f4fbf..be2e6db 100644
0032 --- a/target-arm/helper.c
0033 +++ b/target-arm/helper.c
0034 @@ -2163,7 +2163,7 @@ uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
0035          return (env->uncached_cpsr & CPSR_I) != 0;
0036      case 17: /* BASEPRI */
0037      case 18: /* BASEPRI_MAX */
0038 -        return env->v7m.basepri;
0039 +        return (env->uncached_cpsr & CPSR_I) != 0;
0040      case 19: /* FAULTMASK */
0041          return (env->uncached_cpsr & CPSR_F) != 0;
0042      case 20: /* CONTROL */
0043 @@ -2218,13 +2218,11 @@ void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
0044              env->uncached_cpsr &= ~CPSR_I;
0045          break;
0046      case 17: /* BASEPRI */
0047 -        env->v7m.basepri = val & 0xff;
0048 -        break;
0049      case 18: /* BASEPRI_MAX */
0050 -        val &= 0xff;
0051 -        if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
0052 -            env->v7m.basepri = val;
0053 -        break;
0054 +        if (val)
0055 +            env->uncached_cpsr |= CPSR_I;
0056 +        else
0057 +            env->uncached_cpsr &= ~CPSR_I;
0058      case 19: /* FAULTMASK */
0059          if (val & 1)
0060              env->uncached_cpsr |= CPSR_F;
0061 -- 
0062 1.7.1
0063