Warning, /bsps/arm/lm3s69xx/0001-target-arm-Fixed-ARMv7-M-SHPR-access.patch is written in an unsupported language. File is not indexed.
0001 From 0c8e700376cec0c7b5a70f999b5e286efc321423 Mon Sep 17 00:00:00 2001
0002 From: Sebastian Huber <sebastian.huber@embedded-brains.de>
0003 Date: Fri, 16 Dec 2011 19:46:40 +0100
0004 Subject: [PATCH 1/4] target-arm: Fixed ARMv7-M SHPR access
0005
0006 According to "ARMv7-M Architecture Reference Manual" issue D section
0007 "B3.2.10 System Handler Prioriy Register 1, SHPR1", "B3.2.11 System
0008 Handler Prioriy Register 2, SHPR2", and "B3.2.12 System Handler Prioriy
0009 Register 3, SHPR3".
0010
0011 Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
0012 ---
0013 hw/arm_gic.c | 16 ++++++++++++++--
0014 hw/armv7m_nvic.c | 19 -------------------
0015 2 files changed, 14 insertions(+), 21 deletions(-)
0016
0017 diff --git a/hw/arm_gic.c b/hw/arm_gic.c
0018 index 9b52119..5139d95 100644
0019 --- a/hw/arm_gic.c
0020 +++ b/hw/arm_gic.c
0021 @@ -356,6 +356,11 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
0022 if (GIC_TEST_TRIGGER(irq + i))
0023 res |= (2 << (i * 2));
0024 }
0025 +#else
0026 + } else if (0xd18 <= offset && offset < 0xd24) {
0027 + /* System Handler Priority. */
0028 + irq = offset - 0xd14;
0029 + res = GIC_GET_PRIORITY(irq, cpu);
0030 #endif
0031 } else if (offset < 0xfe0) {
0032 goto bad_reg;
0033 @@ -387,7 +392,8 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
0034 gic_state *s = (gic_state *)opaque;
0035 uint32_t addr;
0036 addr = offset;
0037 - if (addr < 0x100 || addr > 0xd00)
0038 + if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
0039 + && addr != 0xd20))
0040 return nvic_readl(s, addr);
0041 #endif
0042 val = gic_dist_readw(opaque, offset);
0043 @@ -528,6 +534,11 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
0044 GIC_CLEAR_TRIGGER(irq + i);
0045 }
0046 }
0047 +#else
0048 + } else if (0xd18 <= offset && offset < 0xd24) {
0049 + /* System Handler Priority. */
0050 + irq = offset - 0xd14;
0051 + s->priority1[irq][0] = value & 0xff;
0052 #endif
0053 } else {
0054 /* 0xf00 is only handled for 32-bit writes. */
0055 @@ -553,7 +564,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
0056 #ifdef NVIC
0057 uint32_t addr;
0058 addr = offset;
0059 - if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
0060 + if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
0061 + && addr != 0xd20 && addr != 0xf00)) {
0062 nvic_writel(s, addr, value);
0063 return;
0064 }
0065 diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
0066 index bf8c3c5..65b575e 100644
0067 --- a/hw/armv7m_nvic.c
0068 +++ b/hw/armv7m_nvic.c
0069 @@ -195,14 +195,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
0070 case 0xd14: /* Configuration Control. */
0071 /* TODO: Implement Configuration Control bits. */
0072 return 0;
0073 - case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */
0074 - irq = offset - 0xd14;
0075 - val = 0;
0076 - val |= s->gic.priority1[irq++][0];
0077 - val |= s->gic.priority1[irq++][0] << 8;
0078 - val |= s->gic.priority1[irq++][0] << 16;
0079 - val |= s->gic.priority1[irq][0] << 24;
0080 - return val;
0081 case 0xd24: /* System Handler Status. */
0082 val = 0;
0083 if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
0084 @@ -335,17 +327,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
0085 case 0xd14: /* Configuration Control. */
0086 /* TODO: Implement control registers. */
0087 goto bad_reg;
0088 - case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */
0089 - {
0090 - int irq;
0091 - irq = offset - 0xd14;
0092 - s->gic.priority1[irq++][0] = value & 0xff;
0093 - s->gic.priority1[irq++][0] = (value >> 8) & 0xff;
0094 - s->gic.priority1[irq++][0] = (value >> 16) & 0xff;
0095 - s->gic.priority1[irq][0] = (value >> 24) & 0xff;
0096 - gic_update(&s->gic);
0097 - }
0098 - break;
0099 case 0xd24: /* System Handler Control. */
0100 /* TODO: Real hardware allows you to set/clear the active bits
0101 under some circumstances. We don't implement this. */
0102 --
0103 1.7.1
0104
