include/libcpu/omap3.h

0001 /*
0002  * Copyright (c) 2012 Claas Ziemke. All rights reserved.
0003  *
0004  *  Claas Ziemke
0005  *  Kernerstrasse 11
0006  *  70182 Stuttgart
0007  *  Germany
0008  *  <claas.ziemke@gmx.net>
0009  *
0010  * The license and distribution terms for this file may be
0011  * found in the file LICENSE in this distribution or at
0012  * http://www.rtems.org/license/LICENSE.
0013  *
0014  * Modified by Ben Gras <beng@shrike-systems.com> to add lots
0015  * of beagleboard/beaglebone definitions, delete lpc32xx specific
0016  * ones, and merge with some other header files.
0017  */
0018
0019 /* Interrupt controller memory map */
0020 #define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
0021
0022 /* Interrupt controller memory map */
0023 #define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
0024
0025 /* Interrupt controller registers */
0026 #define OMAP3_INTCPS_REVISION     0x000 /* IP revision code */
0027 #define OMAP3_INTCPS_SYSCONFIG    0x010 /* Controls params */
0028 #define OMAP3_INTCPS_SYSSTATUS    0x014 /* Status */
0029 #define OMAP3_INTCPS_SIR_IRQ      0x040 /* Active IRQ number */
0030 #define OMAP3_INTCPS_SIR_FIQ      0x044 /* Active FIQ number */
0031 #define OMAP3_INTCPS_CONTROL      0x048 /* New int agreement bits */
0032 #define OMAP3_INTCPS_PROTECTION   0x04C /* Protection for other regs */
0033 #define OMAP3_INTCPS_IDLE         0x050 /* Clock auto-idle/gating */
0034 #define OMAP3_INTCPS_IRQ_PRIORITY 0x060 /* Active IRQ priority level */
0035 #define OMAP3_INTCPS_FIQ_PRIORITY 0x064 /* Active FIQ priority level */
0036 #define OMAP3_INTCPS_THRESHOLD    0x068 /* Priority threshold */
0037 #define OMAP3_INTCPS_ITR0         0x080 /* Raw pre-masking interrupt status */
0038 #define OMAP3_INTCPS_MIR0         0x084 /* Interrupt mask */
0039 #define OMAP3_INTCPS_MIR1         0x0A4 /* Interrupt mask */
0040 #define OMAP3_INTCPS_MIR2         0x0C4 /* Interrupt mask */
0041 #define OMAP3_INTCPS_MIR3         0x0E4 /* Interrupt mask */
0042 #define OMAP3_INTCPS_MIR_CLEAR0   0x088 /* Clear interrupt mask bits */
0043 #define OMAP3_INTCPS_MIR_SET0     0x08C /* Set interrupt mask bits */
0044 #define OMAP3_INTCPS_ISR_SET0     0x090 /* Set software int bits */
0045 #define OMAP3_INTCPS_ISR_CLEAR0   0x094 /* Clear software int bits */
0046 #define OMAP3_INTCPS_PENDING_IRQ0 0x098 /* IRQ status post-masking */
0047 #define OMAP3_INTCPS_PENDING_IRQ1 0x0b8 /* IRQ status post-masking */
0048 #define OMAP3_INTCPS_PENDING_IRQ2 0x0d8 /* IRQ status post-masking */
0049 #define OMAP3_INTCPS_PENDING_IRQ3 0x0f8 /* IRQ status post-masking */
0050 #define OMAP3_INTCPS_PENDING_FIQ0 0x09C /* FIQ status post-masking */
0051 #define OMAP3_INTCPS_ILR0         0x100 /* Priority for interrupts */
0052
0053 /* SYSCONFIG */
0054 #define OMAP3_SYSCONFIG_AUTOIDLE    0x01    /* SYSCONFIG.AUTOIDLE bit */
0055
0056 #define OMAP3_INTR_ITR(base,n) \
0057     (base + OMAP3_INTCPS_ITR0 + 0x20 * (n))
0058 #define OMAP3_INTR_MIR(base,n) \
0059     (base + OMAP3_INTCPS_MIR0 + 0x20 * (n))
0060 #define OMAP3_INTR_MIR_CLEAR(base,n)    \
0061     (base + OMAP3_INTCPS_MIR_CLEAR0 + 0x20 * (n))
0062 #define OMAP3_INTR_MIR_SET(base,n) \
0063     (base + OMAP3_INTCPS_MIR_SET0 + 0x20 * (n))
0064 #define OMAP3_INTR_ISR_SET(base,n) \
0065     (base + OMAP3_INTCPS_ISR_SET0 + 0x20 * (n))
0066 #define OMAP3_INTR_ISR_CLEAR(base,n) \
0067     (base + OMAP3_INTCPS_ISR_CLEAR0 + 0x20 * (n))
0068 #define OMAP3_INTR_PENDING_IRQ(base,n) \
0069     (base + OMAP3_INTCPS_PENDING_IRQ0 + 0x20 * (n))
0070 #define OMAP3_INTR_PENDING_FIQ(base,n) \
0071     (base + OMAP3_INTCPS_PENDING_FIQ0 + 0x20 * (n))
0072 #define OMAP3_INTR_ILR(base,m) \
0073     (base + OMAP3_INTCPS_ILR0 + 0x4 * (m))
0074
0075 #define OMAP3_INTR_SPURIOUSIRQ_MASK (0x1FFFFFF << 7) /* Spurious IRQ mask for SIR_IRQ */
0076 #define OMAP3_INTR_ACTIVEIRQ_MASK 0x7F /* Active IRQ mask for SIR_IRQ */
0077 #define OMAP3_INTR_NEWIRQAGR      0x1  /* New IRQ Generation */
0078
0079 #define OMAP3_DM337X_NR_IRQ_VECTORS    96
0080
0081 /* Interrupt mappings */
0082 #define OMAP3_MCBSP2_ST_IRQ  4  /* Sidestone McBSP2 overflow */
0083 #define OMAP3_MCBSP3_ST_IRQ  5  /* Sidestone McBSP3 overflow */
0084 #define OMAP3_SYS_NIRQ       7  /* External source (active low) */
0085 #define OMAP3_SMX_DBG_IRQ    9  /* L3 interconnect error for debug */
0086 #define OMAP3_SMX_APP_IRQ   10  /* L3 interconnect error for application */
0087 #define OMAP3_PRCM_IRQ      11  /* PRCM module */
0088 #define OMAP3_SDMA0_IRQ     12  /* System DMA request 0 */
0089 #define OMAP3_SDMA1_IRQ     13  /* System DMA request 1 */
0090 #define OMAP3_SDMA2_IRQ     14  /* System DMA request 2 */
0091 #define OMAP3_SDMA3_IRQ     15  /* System DMA request 3 */
0092 #define OMAP3_MCBSP1_IRQ    16  /* McBSP module 1 */
0093 #define OMAP3_MCBSP2_IRQ    17  /* McBSP module 2 */
0094 #define OMAP3_GPMC_IRQ      20  /* General-purpose memory controller */
0095 #define OMAP3_SGX_IRQ       21  /* 2D/3D graphics module */
0096 #define OMAP3_MCBSP3_IRQ    22  /* McBSP module 3 */
0097 #define OMAP3_MCBSP4_IRQ    23  /* McBSP module 4 */
0098 #define OMAP3_CAM0_IRQ      24  /* Camera interface request 0 */
0099 #define OMAP3_DSS_IRQ       25  /* Display subsystem module */
0100 #define OMAP3_MAIL_U0_IRQ   26  /* Mailbox user 0 request */
0101 #define OMAP3_MCBSP5_IRQ    27  /* McBSP module 5 */
0102 #define OMAP3_IVA2_MMU_IRQ  28  /* IVA2 MMU */
0103 #define OMAP3_GPIO1_IRQ     29  /* GPIO module 1 */
0104 #define OMAP3_GPIO2_IRQ     30  /* GPIO module 2 */
0105 #define OMAP3_GPIO3_IRQ     31  /* GPIO module 3 */
0106 #define OMAP3_GPIO4_IRQ     32  /* GPIO module 4 */
0107 #define OMAP3_GPIO5_IRQ     33  /* GPIO module 5 */
0108 #define OMAP3_GPIO6_IRQ     34  /* GPIO module 6 */
0109 #define OMAP3_WDT3_IRQ      36  /* Watchdog timer module 3 overflow */
0110 #define OMAP3_GPT1_IRQ      37  /* General-purpose timer module 1 */
0111 #define OMAP3_GPT2_IRQ      38  /* General-purpose timer module 2 */
0112 #define OMAP3_GPT3_IRQ      39  /* General-purpose timer module 3 */
0113 #define OMAP3_GPT4_IRQ      40  /* General-purpose timer module 4 */
0114 #define OMAP3_GPT5_IRQ      41  /* General-purpose timer module 5 */
0115 #define OMAP3_GPT6_IRQ      42  /* General-purpose timer module 6 */
0116 #define OMAP3_GPT7_IRQ      43  /* General-purpose timer module 7 */
0117 #define OMAP3_GPT8_IRQ      44  /* General-purpose timer module 8 */
0118 #define OMAP3_GPT9_IRQ      45  /* General-purpose timer module 9 */
0119 #define OMAP3_GPT10_IRQ     46  /* General-purpose timer module 10 */
0120 #define OMAP3_GPT11_IRQ     47  /* General-purpose timer module 11 */
0121 #define OMAP3_SPI4_IRQ      48  /* McSPI module 4 */
0122 #define OMAP3_MCBSP4_TX_IRQ 54  /* McBSP module 4 transmit */
0123 #define OMAP3_MCBSP4_RX_IRQ 55  /* McBSP module 4 receive */
0124 #define OMAP3_I2C1_IRQ      56  /* I2C module 1 */
0125 #define OMAP3_I2C2_IRQ      57  /* I2C module 2 */
0126 #define OMAP3_HDQ_IRQ       58  /* HDQ/1-Wire */
0127 #define OMAP3_MCBSP1_TX_IRQ 59  /* McBSP module 1 transmit */
0128 #define OMAP3_MCBSP1_RX_IRQ 60  /* McBSP module 1 receive */
0129 #define OMAP3_I2C3_IRQ      61  /* I2C module 3 */
0130 #define OMAP3_MCBSP2_TX_IRQ 62  /* McBSP module 2 transmit */
0131 #define OMAP3_MCBSP2_RX_IRQ 63  /* McBSP module 2 receive */
0132 #define OMAP3_SPI1_IRQ      65  /* McSPI module 1 */
0133 #define OMAP3_SPI2_IRQ      66  /* McSPI module 2 */
0134 #define OMAP3_UART1_IRQ     72  /* UART module 1 */
0135 #define OMAP3_UART2_IRQ     73  /* UART module 2 */
0136 #define OMAP3_UART3_IRQ     74  /* UART module 3 */
0137 #define OMAP3_PBIAS_IRQ     75  /* Merged interrupt for PBIASlite 1/2 */
0138 #define OMAP3_OHCI_IRQ      76  /* OHCI HSUSB MP Host Interrupt */
0139 #define OMAP3_EHCI_IRQ      77  /* EHCI HSUSB MP Host Interrupt */
0140 #define OMAP3_TLL_IRQ       78  /* HSUSB MP TLL Interrupt */
0141 #define OMAP3_MCBSP5_TX_IRQ 81  /* McBSP module 5 transmit */
0142 #define OMAP3_MCBSP5_RX_IRQ 82  /* McBSP module 5 receive */
0143 #define OMAP3_MMC1_IRQ      83  /* MMC/SD module 1 */
0144 #define OMAP3_MMC2_IRQ      86  /* MMC/SD module 2 */
0145 #define OMAP3_ICR_IRQ       87  /* MPU ICR */
0146 #define OMAP3_D2DFRINT_IRQ  88  /* 3G coproc (in stacked modem config) */
0147 #define OMAP3_MCBSP3_TX_IRQ 89  /* McBSP module 3 transmit */
0148 #define OMAP3_MCBSP3_RX_IRQ 90  /* McBSP module 3 receive */
0149 #define OMAP3_SPI3_IRQ      91  /* McSPI module 3 */
0150 #define OMAP3_HSUSB_MC_IRQ  92  /* High-speed USB OTG */
0151 #define OMAP3_HSUSB_DMA_IRQ 93  /* High-speed USB OTG DMA */
0152 #define OMAP3_MMC3_IRQ      94  /* MMC/SD module 3 */
0153
0154 /* General-purpose timer register map */
0155 #define OMAP3_GPTIMER1_BASE  0x48318000
0156     /* GPTIMER1 physical address */
0157 #define OMAP3_GPTIMER2_BASE  0x49032000
0158     /* GPTIMER2 physical address */
0159 #define OMAP3_GPTIMER3_BASE  0x49034000
0160     /* GPTIMER3 physical address */
0161 #define OMAP3_GPTIMER4_BASE  0x49036000
0162     /* GPTIMER4 physical address */
0163 #define OMAP3_GPTIMER5_BASE  0x49038000
0164     /* GPTIMER5 physical address */
0165 #define OMAP3_GPTIMER6_BASE  0x4903A000
0166     /* GPTIMER6 physical address */
0167 #define OMAP3_GPTIMER7_BASE  0x4903C000
0168     /* GPTIMER7 physical address */
0169 #define OMAP3_GPTIMER8_BASE  0x4903E000
0170     /* GPTIMER8 physical address */
0171 #define OMAP3_GPTIMER9_BASE  0x49040000
0172     /* GPTIMER9 physical address */
0173 #define OMAP3_GPTIMER10_BASE 0x48086000
0174     /* GPTIMER10 physical address */
0175 #define OMAP3_GPTIMER11_BASE 0x48088000
0176     /* GPTIMER11 physical address */
0177
0178
0179 /* General-purpose timer registers */
0180 #define OMAP3_TIMER_TIDR      0x000
0181     /* IP revision code */
0182 #define OMAP3_TIMER_TIOCP_CFG 0x010
0183     /* Controls params for GP timer L4 iface */
0184 #define OMAP3_TIMER_TISTAT    0x014
0185     /* Status (excl. interrupt status) */
0186 #define OMAP3_TIMER_TISR      0x018
0187     /* Pending interrupt status */
0188 #define OMAP3_TIMER_TIER      0x01C
0189     /* Interrupt enable */
0190 #define OMAP3_TIMER_TWER      0x020
0191     /* Wakeup enable */
0192 #define OMAP3_TIMER_TCLR      0x024
0193     /* Controls optional features */
0194 #define OMAP3_TIMER_TCRR      0x028
0195     /* Internal counter value */
0196 #define OMAP3_TIMER_TLDR      0x02C
0197     /* Timer load value */
0198 #define OMAP3_TIMER_TTGR      0x030
0199     /* Triggers counter reload */
0200 #define OMAP3_TIMER_TWPS      0x034
0201     /* Indicates if Write-Posted pending */
0202 #define OMAP3_TIMER_TMAR      0x038
0203     /* Value to be compared with counter */
0204 #define OMAP3_TIMER_TCAR1     0x03C
0205     /* First captured value of counter reg */
0206 #define OMAP3_TIMER_TSICR     0x040
0207     /* Control posted mode and functional SW rst */
0208 #define OMAP3_TIMER_TCAR2     0x044
0209     /* Second captured value of counter register */
0210 #define OMAP3_TIMER_TPIR      0x048
0211     /* Positive increment (1 ms tick) */
0212 #define OMAP3_TIMER_TNIR      0x04C
0213     /* Negative increment (1 ms tick) */
0214 #define OMAP3_TIMER_TCVR      0x050
0215     /* Defines TCRR is sub/over-period (1 ms tick) */
0216 #define OMAP3_TIMER_TOCR      0x054
0217     /* Masks tick interrupt */
0218 #define OMAP3_TIMER_TOWR      0x058
0219     /* Number of masked overflow interrupts */
0220
0221 /* Interrupt status register fields */
0222 #define OMAP3_TISR_MAT_IT_FLAG  (1 << 0) /* Pending match interrupt status */
0223 #define OMAP3_TISR_OVF_IT_FLAG  (1 << 1) /* Pending overflow interrupt status */
0224 #define OMAP3_TISR_TCAR_IT_FLAG (1 << 2) /* Pending capture interrupt status */
0225
0226 /* Interrupt enable register fields */
0227 #define OMAP3_TIER_MAT_IT_ENA  (1 << 0) /* Enable match interrupt */
0228 #define OMAP3_TIER_OVF_IT_ENA  (1 << 1) /* Enable overflow interrupt */
0229 #define OMAP3_TIER_TCAR_IT_ENA (1 << 2) /* Enable capture interrupt */
0230
0231 /* Timer control fields */
0232 #define OMAP3_TCLR_ST       (1 << 0)  /* Start/stop timer */
0233 #define OMAP3_TCLR_AR       (1 << 1)  /* Autoreload or one-shot mode */
0234 #define OMAP3_TCLR_PRE      (1 << 5)  /* Prescaler on */
0235 #define OMAP3_TCLR_PTV      (1 << 1)  /* looks like "bleed" from Minix */
0236 #define OMAP3_TCLR_OVF_TRG  (1 << 10) /* Overflow trigger */
0237
0238
0239 #define OMAP3_CM_CLKSEL_GFX     0x48004b40
0240 #define OMAP3_CM_CLKEN_PLL      0x48004d00
0241 #define OMAP3_CM_FCLKEN1_CORE   0x48004A00
0242 #define OMAP3_CM_CLKSEL_CORE    0x48004A40 /* GPT10 src clock sel. */
0243 #define OMAP3_CM_FCLKEN_PER     0x48005000
0244 #define OMAP3_CM_CLKSEL_PER     0x48005040
0245 #define OMAP3_CM_CLKSEL_WKUP    0x48004c40 /* GPT1 source clock selection */
0246
0247
0248 #define CM_MODULEMODE_MASK        (0x3 << 0)
0249 #define CM_MODULEMODE_ENABLE      (0x2 << 0)
0250 #define CM_MODULEMODE_DISABLED    (0x0 << 0)
0251
0252 #define CM_CLKCTRL_IDLEST         (0x3 << 16)
0253 #define CM_CLKCTRL_IDLEST_FUNC    (0x0 << 16)
0254 #define CM_CLKCTRL_IDLEST_TRANS   (0x1 << 16)
0255 #define CM_CLKCTRL_IDLEST_IDLE    (0x2 << 16)
0256 #define CM_CLKCTRL_IDLEST_DISABLE (0x3 << 16)
0257
0258 #define CM_WKUP_BASE 0x44E00400 /* Clock Module Wakeup Registers */
0259
0260 #define CM_WKUP_TIMER1_CLKCTRL  (CM_WKUP_BASE + 0xC4)
0261     /* This register manages the TIMER1 clocks. [Memory Mapped] */
0262
0263 #define CM_PER_BASE 0x44E00000 /* Clock Module Peripheral Registers */
0264 #define CM_PER_TIMER7_CLKCTRL   (CM_PER_BASE + 0x7C)
0265     /* This register manages the TIMER7 clocks. [Memory Mapped] */
0266
0267 /* CM_DPLL registers */
0268
0269 #define CM_DPLL_BASE    0x44E00500 /* Clock Module PLL Registers */
0270
0271 #define CLKSEL_TIMER1MS_CLK (CM_DPLL_BASE + 0x28)
0272
0273 #define CLKSEL_TIMER1MS_CLK_SEL_MASK (0x7 << 0)
0274 #define CLKSEL_TIMER1MS_CLK_SEL_SEL1 (0x0 << 0)
0275     /* Select CLK_M_OSC clock */
0276 #define CLKSEL_TIMER1MS_CLK_SEL_SEL2 (0x1 << 0)
0277     /* Select CLK_32KHZ clock */
0278 #define CLKSEL_TIMER1MS_CLK_SEL_SEL3 (0x2 << 0)
0279     /* Select TCLKIN clock */
0280 #define CLKSEL_TIMER1MS_CLK_SEL_SEL4 (0x3 << 0)
0281     /* Select CLK_RC32K clock */
0282 #define CLKSEL_TIMER1MS_CLK_SEL_SEL5 (0x4 << 0)
0283     /* Selects the CLK_32768 from 32KHz Crystal Osc */
0284
0285 #define CLKSEL_TIMER7_CLK   (CM_DPLL_BASE + 0x04)
0286 #define CLKSEL_TIMER7_CLK_SEL_MASK (0x3 << 0)
0287 #define CLKSEL_TIMER7_CLK_SEL_SEL1 (0x0 << 0) /* Select TCLKIN clock */
0288 #define CLKSEL_TIMER7_CLK_SEL_SEL2 (0x1 << 0) /* Select CLK_M_OSC clock */
0289 #define CLKSEL_TIMER7_CLK_SEL_SEL3 (0x2 << 0) /* Select CLK_32KHZ clock */
0290 #define CLKSEL_TIMER7_CLK_SEL_SEL4 (0x3 << 0) /* Reserved */
0291
0292 /*RTC CLOCK BASE & Registers*/
0293 #define CM_RTC_BASE            0x44E00800
0294 #define CM_RTC_RTC_CLKCTRL     0x0
0295 #define CM_RTC_CLKSTCTRL       0x4
0296
0297
0298 #define OMAP3_CLKSEL_GPT1    (1 << 0)
0299 #define OMAP3_CLKSEL_GPT10   (1 << 6)
0300 #define OMAP3_CLKSEL_GPT11   (1 << 7)
0301
0302 #define OMAP34XX_CORE_L4_IO_BASE  0x48000000
0303
0304 #define ARM_TTBR_ADDR_MASK (0xffffc000)
0305 #define ARM_TTBR_OUTER_NC    (0x0 << 3) /* Non-cacheable*/
0306 #define ARM_TTBR_OUTER_WBWA  (0x1 << 3) /* Outer Write-Back */
0307 #define ARM_TTBR_OUTER_WT    (0x2 << 3) /* Outer Write-Through */
0308 #define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back */
0309 #define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA
0310
0311 /* cpu control flags */
0312 /* CPU control register (CP15 register 1) */
0313 #define CPU_CONTROL_MMU_ENABLE  0x00000001 /* M: MMU/Protection unit enable */
0314 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
0315 #define CPU_CONTROL_DC_ENABLE   0x00000004 /* C: IDC/DC enable */
0316 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
0317 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
0318 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
0319 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
0320 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
0321 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
0322 #define CPU_CONTROL_ROM_ENABLE  0x00000200 /* R: ROM protection bit */
0323 #define CPU_CONTROL_CPCLK       0x00000400 /* F: Implementation defined */
0324 #define CPU_CONTROL_SWP_ENABLE  0x00000400 /* SW: SWP{B} perform normally. */
0325 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
0326 #define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */
0327 #define CPU_CONTROL_VECRELOC    0x00002000 /* V: Vector relocation */
0328 #define CPU_CONTROL_ROUNDROBIN  0x00004000 /* RR: Predictable replacement */
0329 #define CPU_CONTROL_V4COMPAT    0x00008000 /* L4: ARMv4 compat LDR R15 etc */
0330 #define CPU_CONTROL_FI_ENABLE   0x00200000 /* FI: Low interrupt latency */
0331 #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
0332 #define CPU_CONTROL_XP_ENABLE   0x00800000 /* XP: extended page table */
0333 #define CPU_CONTROL_V_ENABLE    0x01000000 /* VE: Interrupt vectors enable */
0334 #define CPU_CONTROL_EX_BEND     0x02000000 /* EE: exception endianness */
0335 #define CPU_CONTROL_NMFI        0x08000000 /* NMFI: Non maskable FIQ */
0336 #define CPU_CONTROL_TR_ENABLE   0x10000000 /* TRE: */
0337 #define CPU_CONTROL_AF_ENABLE   0x20000000 /* AFE: Access flag enable */
0338 #define CPU_CONTROL_TE_ENABLE   0x40000000 /* TE: Thumb Exception enable */
0339
0340 #define CPU_CONTROL_IDC_ENABLE  CPU_CONTROL_DC_ENABLE
0341
0342 /* VM bits */
0343
0344 /* Big page (1MB section) specific flags. */
0345 #define ARM_VM_SECTION                  (1 << 1)
0346     /* 1MB section */
0347 #define ARM_VM_SECTION_PRESENT          (1 << 1)
0348     /* Section is present */
0349 #define ARM_VM_SECTION_B                (1 << 2)
0350     /* B Bit */
0351 #define ARM_VM_SECTION_C                (1 << 3)
0352     /* C Bit */
0353 #define ARM_VM_SECTION_DOMAIN           (0xF << 5)
0354     /* Domain Number */
0355 #define ARM_VM_SECTION_SUPER            (0x1 << 10)
0356     /* Super access only AP[1:0] */
0357 #define ARM_VM_SECTION_USER             (0x3 << 10)
0358     /* Super/User access AP[1:0] */
0359 #define ARM_VM_SECTION_TEX0             (1 << 12)
0360     /* TEX[0] */
0361 #define ARM_VM_SECTION_TEX1             (1 << 13)
0362     /* TEX[1] */
0363 #define ARM_VM_SECTION_TEX2             (1 << 14)
0364     /* TEX[2] */
0365 #define ARM_VM_SECTION_RO               (1 << 15)
0366     /* Read only access AP[2] */
0367 #define ARM_VM_SECTION_SHAREABLE        (1 << 16)
0368     /* Shareable */
0369 #define ARM_VM_SECTION_NOTGLOBAL        (1 << 17)
0370     /* Not Global */
0371
0372 #define ARM_VM_SECTION_WB \
0373     (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_B )
0374 /* inner and outer write-back, write-allocate */
0375 #define ARM_VM_SECTION_WT \
0376     (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX1 | ARM_VM_SECTION_C )
0377 /* inner and outer write-through, no write-allocate */
0378 #define ARM_VM_SECTION_WTWB \
0379     (ARM_VM_SECTION_TEX2 | ARM_VM_SECTION_TEX0 | ARM_VM_SECTION_C )
0380 /* Inner , Write through, No Write Allocate Outer - Write Back, Write Allocate */
0381
0382 /* shareable device */
0383 #define ARM_VM_SECTION_CACHED   ARM_VM_SECTION_WTWB
0384 #define ARM_VM_SECTION_DEVICE   (ARM_VM_SECTION_B)