dev/cache/arm-data-cache-loop-set-way.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMShared
0007  *
0008  * @brief This header file provides an assember macro to loop through the data
0009  *   cache by set and way.
0010  */
0011
0012 /*
0013  * SPDX-License-Identifier: BSD-2-Clause
0014  *
0015  * Copyright (C) 2018 embedded brains GmbH & Co. KG
0016  *
0017  * Redistribution and use in source and binary forms, with or without
0018  * modification, are permitted provided that the following conditions
0019  * are met:
0020  * 1. Redistributions of source code must retain the above copyright
0021  *    notice, this list of conditions and the following disclaimer.
0022  * 2. Redistributions in binary form must reproduce the above copyright
0023  *    notice, this list of conditions and the following disclaimer in the
0024  *    documentation and/or other materials provided with the distribution.
0025  *
0026  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0027  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0028  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0029  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0030  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0031  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0032  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0033  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0034  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0035  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0036  * POSSIBILITY OF SUCH DAMAGE.
0037  */
0038
0039 .macro  ARM_DATA_CACHE_LOOP_SET_WAY CRM
0040
0041     /* Get cache levels (LoC) from CLIDR */
0042     mrc p15, 1, r1, c0, c0, 1
0043     mov r2, r1, lsr #24
0044     ands    r2, r2, #0x7
0045     beq 5f
0046
0047     /* Start with level 0 */
0048     mov r3, #0
0049
0050     /* Flush level specified by r3 */
0051 1:
0052
0053     /* Check cache type and skip this level if there is no data cache */
0054     add r4, r3, r3, lsl #1
0055     lsr r5, r1, r4
0056     and r5, r5, #0x7
0057     cmp r5, #2
0058     blt 4f
0059
0060     /* Read CCSIDR */
0061     lsl r4, r3, #1
0062     mcr p15, 2, r4, c0, c0, 0
0063     isb
0064     mrc p15, 1, r5, c0, c0, 0
0065
0066     /* Get cache line power */
0067     and r6, r5, #0x7
0068     add r6, r6, #4
0069
0070     /* Get ways minus one */
0071     mov r7, #0x3ff
0072     ands    r7, r7, r5, lsr #3
0073
0074     /* Get way shift */
0075     clz r8, r7
0076
0077     /* Get sets minus one */
0078     mov r9, #0x7fff
0079     ands    r9, r9, r5, lsr #13
0080
0081     /* Loop over ways */
0082 2:
0083     mov r10, r9
0084
0085     /* Loop over sets */
0086 3:
0087     orr r11, r4, r7, lsl r8
0088     orr r11, r11, r10, lsl r6
0089
0090     /* Cache operation by set and way */
0091     mcr p15, 0, r11, c7, \CRM, 2
0092
0093     subs    r10, r10, #1
0094     bge 3b
0095     subs    r7, r7, #1
0096     bge 2b
0097
0098     /* Next level */
0099 4:
0100     add r3, r3, #1
0101     cmp r2, r3
0102     bgt 1b
0103
0104     /* Done */
0105 5:
0106
0107 .endm