arm/include/core_cm7.h

0001 /**************************************************************************//**
0002  * @file     core_cm7.h
0003  * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
0004  * @version  V5.2.0
0005  * @date     04. April 2023
0006  ******************************************************************************/
0007 /*
0008  * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
0009  *
0010  * SPDX-License-Identifier: Apache-2.0
0011  *
0012  * Licensed under the Apache License, Version 2.0 (the License); you may
0013  * not use this file except in compliance with the License.
0014  * You may obtain a copy of the License at
0015  *
0016  * www.apache.org/licenses/LICENSE-2.0
0017  *
0018  * Unless required by applicable law or agreed to in writing, software
0019  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
0020  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
0021  * See the License for the specific language governing permissions and
0022  * limitations under the License.
0023  */
0024
0025 #if   defined ( __ICCARM__ )
0026   #pragma system_include         /* treat file as system include file for MISRA check */
0027 #elif defined (__clang__)
0028   #pragma clang system_header   /* treat file as system include file */
0029 #endif
0030
0031 #ifndef __CORE_CM7_H_GENERIC
0032 #define __CORE_CM7_H_GENERIC
0033
0034 #include <stdint.h>
0035
0036 #ifdef __cplusplus
0037  extern "C" {
0038 #endif
0039
0040 /**
0041   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
0042   CMSIS violates the following MISRA-C:2004 rules:
0043
0044    \li Required Rule 8.5, object/function definition in header file.<br>
0045      Function definitions in header files are used to allow 'inlining'.
0046
0047    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
0048      Unions are used for effective representation of core registers.
0049
0050    \li Advisory Rule 19.7, Function-like macro defined.<br>
0051      Function-like macros are used to allow more efficient code.
0052  */
0053
0054
0055 /*******************************************************************************
0056  *                 CMSIS definitions
0057  ******************************************************************************/
0058 /**
0059   \ingroup Cortex_M7
0060   @{
0061  */
0062
0063 #include "cmsis_version.h"
0064
0065 /* CMSIS CM7 definitions */
0066 #define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
0067 #define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
0068 #define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
0069                                     __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
0070
0071 #define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
0072
0073 /** __FPU_USED indicates whether an FPU is used or not.
0074     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
0075 */
0076 #if defined ( __CC_ARM )
0077   #if defined __TARGET_FPU_VFP
0078     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0079       #define __FPU_USED       1U
0080     #else
0081       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0082       #define __FPU_USED       0U
0083     #endif
0084   #else
0085     #define __FPU_USED         0U
0086   #endif
0087
0088 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
0089   #if defined __ARM_FP
0090     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0091       #define __FPU_USED       1U
0092     #else
0093       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0094       #define __FPU_USED       0U
0095     #endif
0096   #else
0097     #define __FPU_USED         0U
0098   #endif
0099
0100 #elif defined (__ti__)
0101   #if defined (__ARM_FP)
0102     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0103       #define __FPU_USED       1U
0104     #else
0105       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0106       #define __FPU_USED       0U
0107     #endif
0108   #else
0109     #define __FPU_USED         0U
0110   #endif
0111
0112 #elif defined ( __GNUC__ )
0113   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
0114     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0115       #define __FPU_USED       1U
0116     #else
0117       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0118       #define __FPU_USED       0U
0119     #endif
0120   #else
0121     #define __FPU_USED         0U
0122   #endif
0123
0124 #elif defined ( __ICCARM__ )
0125   #if defined __ARMVFP__
0126     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0127       #define __FPU_USED       1U
0128     #else
0129       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0130       #define __FPU_USED       0U
0131     #endif
0132   #else
0133     #define __FPU_USED         0U
0134   #endif
0135
0136 #elif defined ( __TI_ARM__ )
0137   #if defined __TI_VFP_SUPPORT__
0138     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0139       #define __FPU_USED       1U
0140     #else
0141       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0142       #define __FPU_USED       0U
0143     #endif
0144   #else
0145     #define __FPU_USED         0U
0146   #endif
0147
0148 #elif defined ( __TASKING__ )
0149   #if defined __FPU_VFP__
0150     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0151       #define __FPU_USED       1U
0152     #else
0153       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0154       #define __FPU_USED       0U
0155     #endif
0156   #else
0157     #define __FPU_USED         0U
0158   #endif
0159
0160 #elif defined ( __CSMC__ )
0161   #if ( __CSMC__ & 0x400U)
0162     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0163       #define __FPU_USED       1U
0164     #else
0165       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0166       #define __FPU_USED       0U
0167     #endif
0168   #else
0169     #define __FPU_USED         0U
0170   #endif
0171
0172 #endif
0173
0174 #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
0175
0176
0177 #ifdef __cplusplus
0178 }
0179 #endif
0180
0181 #endif /* __CORE_CM7_H_GENERIC */
0182
0183 #ifndef __CMSIS_GENERIC
0184
0185 #ifndef __CORE_CM7_H_DEPENDANT
0186 #define __CORE_CM7_H_DEPENDANT
0187
0188 #ifdef __cplusplus
0189  extern "C" {
0190 #endif
0191
0192 /* check device defines and use defaults */
0193 #if defined __CHECK_DEVICE_DEFINES
0194   #ifndef __CM7_REV
0195     #define __CM7_REV               0x0000U
0196     #warning "__CM7_REV not defined in device header file; using default!"
0197   #endif
0198
0199   #ifndef __FPU_PRESENT
0200     #define __FPU_PRESENT             0U
0201     #warning "__FPU_PRESENT not defined in device header file; using default!"
0202   #endif
0203
0204   #ifndef __MPU_PRESENT
0205     #define __MPU_PRESENT             0U
0206     #warning "__MPU_PRESENT not defined in device header file; using default!"
0207   #endif
0208
0209   #ifndef __ICACHE_PRESENT
0210     #define __ICACHE_PRESENT          0U
0211     #warning "__ICACHE_PRESENT not defined in device header file; using default!"
0212   #endif
0213
0214   #ifndef __DCACHE_PRESENT
0215     #define __DCACHE_PRESENT          0U
0216     #warning "__DCACHE_PRESENT not defined in device header file; using default!"
0217   #endif
0218
0219   #ifndef __DTCM_PRESENT
0220     #define __DTCM_PRESENT            0U
0221     #warning "__DTCM_PRESENT        not defined in device header file; using default!"
0222   #endif
0223
0224   #ifndef __VTOR_PRESENT
0225     #define __VTOR_PRESENT             1U
0226     #warning "__VTOR_PRESENT not defined in device header file; using default!"
0227   #endif
0228
0229   #ifndef __NVIC_PRIO_BITS
0230     #define __NVIC_PRIO_BITS          3U
0231     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
0232   #endif
0233
0234   #ifndef __Vendor_SysTickConfig
0235     #define __Vendor_SysTickConfig    0U
0236     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
0237   #endif
0238 #endif
0239
0240 /* IO definitions (access restrictions to peripheral registers) */
0241 /**
0242     \defgroup CMSIS_glob_defs CMSIS Global Defines
0243
0244     <strong>IO Type Qualifiers</strong> are used
0245     \li to specify the access to peripheral variables.
0246     \li for automatic generation of peripheral register debug information.
0247 */
0248 #ifdef __cplusplus
0249   #define   __I     volatile             /*!< Defines 'read only' permissions */
0250 #else
0251   #define   __I     volatile const       /*!< Defines 'read only' permissions */
0252 #endif
0253 #define     __O     volatile             /*!< Defines 'write only' permissions */
0254 #define     __IO    volatile             /*!< Defines 'read / write' permissions */
0255
0256 /* following defines should be used for structure members */
0257 #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
0258 #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
0259 #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
0260
0261 /*@} end of group Cortex_M7 */
0262
0263
0264
0265 /*******************************************************************************
0266  *                 Register Abstraction
0267   Core Register contain:
0268   - Core Register
0269   - Core NVIC Register
0270   - Core SCB Register
0271   - Core SysTick Register
0272   - Core Debug Register
0273   - Core MPU Register
0274   - Core FPU Register
0275  ******************************************************************************/
0276 /**
0277   \defgroup CMSIS_core_register Defines and Type Definitions
0278   \brief Type definitions and defines for Cortex-M processor based devices.
0279 */
0280
0281 /**
0282   \ingroup    CMSIS_core_register
0283   \defgroup   CMSIS_CORE  Status and Control Registers
0284   \brief      Core Register type definitions.
0285   @{
0286  */
0287
0288 /**
0289   \brief  Union type to access the Application Program Status Register (APSR).
0290  */
0291 typedef union
0292 {
0293   struct
0294   {
0295     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
0296     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
0297     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
0298     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
0299     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
0300     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
0301     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
0302     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
0303   } b;                                   /*!< Structure used for bit  access */
0304   uint32_t w;                            /*!< Type      used for word access */
0305 } APSR_Type;
0306
0307 /* APSR Register Definitions */
0308 #define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
0309 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
0310
0311 #define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
0312 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
0313
0314 #define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
0315 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
0316
0317 #define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
0318 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
0319
0320 #define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
0321 #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
0322
0323 #define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
0324 #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
0325
0326
0327 /**
0328   \brief  Union type to access the Interrupt Program Status Register (IPSR).
0329  */
0330 typedef union
0331 {
0332   struct
0333   {
0334     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
0335     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
0336   } b;                                   /*!< Structure used for bit  access */
0337   uint32_t w;                            /*!< Type      used for word access */
0338 } IPSR_Type;
0339
0340 /* IPSR Register Definitions */
0341 #define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
0342 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
0343
0344
0345 /**
0346   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
0347  */
0348 typedef union
0349 {
0350   struct
0351   {
0352     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
0353     uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
0354     uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
0355     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
0356     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
0357     uint32_t T:1;                        /*!< bit:     24  Thumb bit */
0358     uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
0359     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
0360     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
0361     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
0362     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
0363     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
0364   } b;                                   /*!< Structure used for bit  access */
0365   uint32_t w;                            /*!< Type      used for word access */
0366 } xPSR_Type;
0367
0368 /* xPSR Register Definitions */
0369 #define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
0370 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
0371
0372 #define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
0373 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
0374
0375 #define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
0376 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
0377
0378 #define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
0379 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
0380
0381 #define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
0382 #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
0383
0384 #define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
0385 #define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
0386
0387 #define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
0388 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
0389
0390 #define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
0391 #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
0392
0393 #define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
0394 #define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
0395
0396 #define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
0397 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
0398
0399
0400 /**
0401   \brief  Union type to access the Control Registers (CONTROL).
0402  */
0403 typedef union
0404 {
0405   struct
0406   {
0407     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
0408     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
0409     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
0410     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
0411   } b;                                   /*!< Structure used for bit  access */
0412   uint32_t w;                            /*!< Type      used for word access */
0413 } CONTROL_Type;
0414
0415 /* CONTROL Register Definitions */
0416 #define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
0417 #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
0418
0419 #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
0420 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
0421
0422 #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
0423 #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
0424
0425 /*@} end of group CMSIS_CORE */
0426
0427
0428 /**
0429   \ingroup    CMSIS_core_register
0430   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
0431   \brief      Type definitions for the NVIC Registers
0432   @{
0433  */
0434
0435 /**
0436   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
0437  */
0438 typedef struct
0439 {
0440   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
0441         uint32_t RESERVED0[24U];
0442   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
0443         uint32_t RESERVED1[24U];
0444   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
0445         uint32_t RESERVED2[24U];
0446   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
0447         uint32_t RESERVED3[24U];
0448   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
0449         uint32_t RESERVED4[56U];
0450   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
0451         uint32_t RESERVED5[644U];
0452   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
0453 }  NVIC_Type;
0454
0455 /* Software Triggered Interrupt Register Definitions */
0456 #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
0457 #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
0458
0459 /*@} end of group CMSIS_NVIC */
0460
0461
0462 /**
0463   \ingroup  CMSIS_core_register
0464   \defgroup CMSIS_SCB     System Control Block (SCB)
0465   \brief    Type definitions for the System Control Block Registers
0466   @{
0467  */
0468
0469 /**
0470   \brief  Structure type to access the System Control Block (SCB).
0471  */
0472 typedef struct
0473 {
0474   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
0475   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
0476   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
0477   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
0478   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
0479   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
0480   __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
0481   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
0482   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
0483   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
0484   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
0485   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
0486   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
0487   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
0488   __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
0489   __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
0490   __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
0491   __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
0492   __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
0493         uint32_t RESERVED0[1U];
0494   __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
0495   __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
0496   __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
0497   __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
0498   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
0499         uint32_t RESERVED3[93U];
0500   __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
0501         uint32_t RESERVED4[15U];
0502   __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
0503   __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
0504   __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
0505         uint32_t RESERVED5[1U];
0506   __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
0507         uint32_t RESERVED6[1U];
0508   __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
0509   __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
0510   __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
0511   __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
0512   __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
0513   __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
0514   __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
0515   __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
0516   __OM  uint32_t BPIALL;                 /*!< Offset: 0x278 ( /W)  Branch Predictor Invalidate All */
0517         uint32_t RESERVED7[5U];
0518   __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
0519   __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
0520   __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
0521   __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
0522   __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
0523         uint32_t RESERVED8[1U];
0524   __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
0525 } SCB_Type;
0526
0527 /* SCB CPUID Register Definitions */
0528 #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
0529 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
0530
0531 #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
0532 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
0533
0534 #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
0535 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
0536
0537 #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
0538 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
0539
0540 #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
0541 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
0542
0543 /* SCB Interrupt Control State Register Definitions */
0544 #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
0545 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
0546
0547 #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
0548 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
0549
0550 #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
0551 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
0552
0553 #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
0554 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
0555
0556 #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
0557 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
0558
0559 #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
0560 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
0561
0562 #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
0563 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
0564
0565 #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
0566 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
0567
0568 #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
0569 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
0570
0571 #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
0572 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
0573
0574 /* SCB Vector Table Offset Register Definitions */
0575 #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
0576 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
0577
0578 /* SCB Application Interrupt and Reset Control Register Definitions */
0579 #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
0580 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
0581
0582 #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
0583 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
0584
0585 #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
0586 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
0587
0588 #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
0589 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
0590
0591 #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
0592 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
0593
0594 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
0595 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
0596
0597 #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
0598 #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
0599
0600 /* SCB System Control Register Definitions */
0601 #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
0602 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
0603
0604 #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
0605 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
0606
0607 #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
0608 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
0609
0610 /* SCB Configuration Control Register Definitions */
0611 #define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
0612 #define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
0613
0614 #define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
0615 #define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
0616
0617 #define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
0618 #define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
0619
0620 #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
0621 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
0622
0623 #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
0624 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
0625
0626 #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
0627 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
0628
0629 #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
0630 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
0631
0632 #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
0633 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
0634
0635 #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
0636 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
0637
0638 /* SCB System Handler Control and State Register Definitions */
0639 #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
0640 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
0641
0642 #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
0643 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
0644
0645 #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
0646 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
0647
0648 #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
0649 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
0650
0651 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
0652 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
0653
0654 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
0655 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
0656
0657 #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
0658 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
0659
0660 #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
0661 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
0662
0663 #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
0664 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
0665
0666 #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
0667 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
0668
0669 #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
0670 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
0671
0672 #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
0673 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
0674
0675 #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
0676 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
0677
0678 #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
0679 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
0680
0681 /* SCB Configurable Fault Status Register Definitions */
0682 #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
0683 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
0684
0685 #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
0686 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
0687
0688 #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
0689 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
0690
0691 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
0692 #define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */
0693 #define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
0694
0695 #define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */
0696 #define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
0697
0698 #define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */
0699 #define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
0700
0701 #define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
0702 #define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
0703
0704 #define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */
0705 #define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
0706
0707 #define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */
0708 #define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
0709
0710 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
0711 #define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
0712 #define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
0713
0714 #define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
0715 #define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
0716
0717 #define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
0718 #define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
0719
0720 #define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
0721 #define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
0722
0723 #define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
0724 #define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
0725
0726 #define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
0727 #define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
0728
0729 #define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
0730 #define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
0731
0732 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
0733 #define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
0734 #define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
0735
0736 #define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
0737 #define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
0738
0739 #define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
0740 #define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
0741
0742 #define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
0743 #define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
0744
0745 #define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
0746 #define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
0747
0748 #define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
0749 #define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
0750
0751 /* SCB Hard Fault Status Register Definitions */
0752 #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
0753 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
0754
0755 #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
0756 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
0757
0758 #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
0759 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
0760
0761 /* SCB Debug Fault Status Register Definitions */
0762 #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
0763 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
0764
0765 #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
0766 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
0767
0768 #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
0769 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
0770
0771 #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
0772 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
0773
0774 #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
0775 #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
0776
0777 /* SCB Cache Level ID Register Definitions */
0778 #define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
0779 #define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
0780
0781 #define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
0782 #define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
0783
0784 /* SCB Cache Type Register Definitions */
0785 #define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
0786 #define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
0787
0788 #define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
0789 #define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
0790
0791 #define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
0792 #define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
0793
0794 #define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
0795 #define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
0796
0797 #define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
0798 #define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
0799
0800 /* SCB Cache Size ID Register Definitions */
0801 #define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
0802 #define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
0803
0804 #define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
0805 #define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
0806
0807 #define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
0808 #define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
0809
0810 #define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
0811 #define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
0812
0813 #define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
0814 #define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
0815
0816 #define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
0817 #define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
0818
0819 #define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
0820 #define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
0821
0822 /* SCB Cache Size Selection Register Definitions */
0823 #define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
0824 #define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
0825
0826 #define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
0827 #define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
0828
0829 /* SCB Software Triggered Interrupt Register Definitions */
0830 #define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
0831 #define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
0832
0833 /* SCB D-Cache Invalidate by Set-way Register Definitions */
0834 #define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
0835 #define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
0836
0837 #define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
0838 #define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
0839
0840 /* SCB D-Cache Clean by Set-way Register Definitions */
0841 #define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
0842 #define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
0843
0844 #define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
0845 #define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
0846
0847 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
0848 #define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
0849 #define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
0850
0851 #define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
0852 #define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
0853
0854 /* Instruction Tightly-Coupled Memory Control Register Definitions */
0855 #define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
0856 #define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
0857
0858 #define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
0859 #define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
0860
0861 #define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
0862 #define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
0863
0864 #define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
0865 #define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
0866
0867 /* Data Tightly-Coupled Memory Control Register Definitions */
0868 #define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
0869 #define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
0870
0871 #define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
0872 #define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
0873
0874 #define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
0875 #define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
0876
0877 #define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
0878 #define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
0879
0880 /* AHBP Control Register Definitions */
0881 #define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
0882 #define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
0883
0884 #define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
0885 #define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
0886
0887 /* L1 Cache Control Register Definitions */
0888 #define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
0889 #define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
0890
0891 #define SCB_CACR_ECCEN_Pos                  1U                                            /*!< \deprecated SCB CACR: ECCEN Position */
0892 #define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< \deprecated SCB CACR: ECCEN Mask */
0893
0894 #define SCB_CACR_ECCDIS_Pos                 1U                                            /*!< SCB CACR: ECCDIS Position */
0895 #define SCB_CACR_ECCDIS_Msk                (1UL << SCB_CACR_ECCDIS_Pos)                   /*!< SCB CACR: ECCDIS Mask */
0896
0897 #define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
0898 #define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
0899
0900 /* AHBS Control Register Definitions */
0901 #define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
0902 #define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
0903
0904 #define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
0905 #define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBSCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
0906
0907 #define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
0908 #define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBSCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
0909
0910 /* Auxiliary Bus Fault Status Register Definitions */
0911 #define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
0912 #define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
0913
0914 #define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
0915 #define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
0916
0917 #define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
0918 #define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
0919
0920 #define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
0921 #define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
0922
0923 #define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
0924 #define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
0925
0926 #define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
0927 #define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
0928
0929 /*@} end of group CMSIS_SCB */
0930
0931
0932 /**
0933   \ingroup  CMSIS_core_register
0934   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
0935   \brief    Type definitions for the System Control and ID Register not in the SCB
0936   @{
0937  */
0938
0939 /**
0940   \brief  Structure type to access the System Control and ID Register not in the SCB.
0941  */
0942 typedef struct
0943 {
0944         uint32_t RESERVED0[1U];
0945   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
0946   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
0947 } SCnSCB_Type;
0948
0949 /* Interrupt Controller Type Register Definitions */
0950 #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
0951 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
0952
0953 /* Auxiliary Control Register Definitions */
0954 #define SCnSCB_ACTLR_DISDYNADD_Pos         26U                                         /*!< ACTLR: DISDYNADD Position */
0955 #define SCnSCB_ACTLR_DISDYNADD_Msk         (1UL << SCnSCB_ACTLR_DISDYNADD_Pos)         /*!< ACTLR: DISDYNADD Mask */
0956
0957 #define SCnSCB_ACTLR_DISISSCH1_Pos         21U                                         /*!< ACTLR: DISISSCH1 Position */
0958 #define SCnSCB_ACTLR_DISISSCH1_Msk         (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos)      /*!< ACTLR: DISISSCH1 Mask */
0959
0960 #define SCnSCB_ACTLR_DISDI_Pos             16U                                         /*!< ACTLR: DISDI Position */
0961 #define SCnSCB_ACTLR_DISDI_Msk             (0x1FUL << SCnSCB_ACTLR_DISDI_Pos)          /*!< ACTLR: DISDI Mask */
0962
0963 #define SCnSCB_ACTLR_DISCRITAXIRUR_Pos     15U                                         /*!< ACTLR: DISCRITAXIRUR Position */
0964 #define SCnSCB_ACTLR_DISCRITAXIRUR_Msk     (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos)     /*!< ACTLR: DISCRITAXIRUR Mask */
0965
0966 #define SCnSCB_ACTLR_DISBTACALLOC_Pos      14U                                         /*!< ACTLR: DISBTACALLOC Position */
0967 #define SCnSCB_ACTLR_DISBTACALLOC_Msk      (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos)      /*!< ACTLR: DISBTACALLOC Mask */
0968
0969 #define SCnSCB_ACTLR_DISBTACREAD_Pos       13U                                         /*!< ACTLR: DISBTACREAD Position */
0970 #define SCnSCB_ACTLR_DISBTACREAD_Msk       (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos)       /*!< ACTLR: DISBTACREAD Mask */
0971
0972 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
0973 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
0974
0975 #define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
0976 #define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
0977
0978 #define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
0979 #define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
0980
0981 #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
0982 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
0983
0984 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
0985 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
0986
0987 /*@} end of group CMSIS_SCnotSCB */
0988
0989
0990 /**
0991   \ingroup  CMSIS_core_register
0992   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
0993   \brief    Type definitions for the System Timer Registers.
0994   @{
0995  */
0996
0997 /**
0998   \brief  Structure type to access the System Timer (SysTick).
0999  */
1000 typedef struct
1001 {
1002   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
1003   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
1004   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
1005   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
1006 } SysTick_Type;
1007
1008 /* SysTick Control / Status Register Definitions */
1009 #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
1010 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
1011
1012 #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
1013 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
1014
1015 #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
1016 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
1017
1018 #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
1019 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
1020
1021 /* SysTick Reload Register Definitions */
1022 #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
1023 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
1024
1025 /* SysTick Current Register Definitions */
1026 #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
1027 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
1028
1029 /* SysTick Calibration Register Definitions */
1030 #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
1031 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
1032
1033 #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
1034 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
1035
1036 #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
1037 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
1038
1039 /*@} end of group CMSIS_SysTick */
1040
1041
1042 /**
1043   \ingroup  CMSIS_core_register
1044   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
1045   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
1046   @{
1047  */
1048
1049 /**
1050   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1051  */
1052 typedef struct
1053 {
1054   __OM  union
1055   {
1056     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
1057     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
1058     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
1059   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
1060         uint32_t RESERVED0[864U];
1061   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
1062         uint32_t RESERVED1[15U];
1063   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
1064         uint32_t RESERVED2[15U];
1065   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
1066         uint32_t RESERVED3[32U];
1067         uint32_t RESERVED4[43U];
1068   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
1069   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
1070         uint32_t RESERVED5[6U];
1071   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
1072   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
1073   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
1074   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
1075   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
1076   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
1077   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
1078   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
1079   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
1080   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
1081   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
1082   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
1083 } ITM_Type;
1084
1085 /* ITM Trace Privilege Register Definitions */
1086 #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
1087 #define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
1088
1089 /* ITM Trace Control Register Definitions */
1090 #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
1091 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
1092
1093 #define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
1094 #define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
1095
1096 #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
1097 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
1098
1099 #define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
1100 #define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPrescale Mask */
1101
1102 #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
1103 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
1104
1105 #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
1106 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
1107
1108 #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
1109 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
1110
1111 #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
1112 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
1113
1114 #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
1115 #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
1116
1117 /* ITM Lock Status Register Definitions */
1118 #define ITM_LSR_BYTEACC_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
1119 #define ITM_LSR_BYTEACC_Msk                (1UL << ITM_LSR_BYTEACC_Pos)                   /*!< ITM LSR: ByteAcc Mask */
1120
1121 #define ITM_LSR_ACCESS_Pos                  1U                                            /*!< ITM LSR: Access Position */
1122 #define ITM_LSR_ACCESS_Msk                 (1UL << ITM_LSR_ACCESS_Pos)                    /*!< ITM LSR: Access Mask */
1123
1124 #define ITM_LSR_PRESENT_Pos                 0U                                            /*!< ITM LSR: Present Position */
1125 #define ITM_LSR_PRESENT_Msk                (1UL /*<< ITM_LSR_PRESENT_Pos*/)               /*!< ITM LSR: Present Mask */
1126
1127 /*@}*/ /* end of group CMSIS_ITM */
1128
1129
1130 /**
1131   \ingroup  CMSIS_core_register
1132   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
1133   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
1134   @{
1135  */
1136
1137 /**
1138   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
1139  */
1140 typedef struct
1141 {
1142   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
1143   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
1144   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
1145   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
1146   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
1147   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
1148   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
1149   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
1150   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
1151   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
1152   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
1153         uint32_t RESERVED0[1U];
1154   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
1155   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
1156   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
1157         uint32_t RESERVED1[1U];
1158   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
1159   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
1160   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
1161         uint32_t RESERVED2[1U];
1162   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
1163   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
1164   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
1165         uint32_t RESERVED3[981U];
1166   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
1167   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
1168 } DWT_Type;
1169
1170 /* DWT Control Register Definitions */
1171 #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
1172 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
1173
1174 #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
1175 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
1176
1177 #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
1178 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
1179
1180 #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
1181 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
1182
1183 #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
1184 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
1185
1186 #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
1187 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
1188
1189 #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
1190 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
1191
1192 #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
1193 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
1194
1195 #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
1196 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
1197
1198 #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
1199 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
1200
1201 #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
1202 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
1203
1204 #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
1205 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
1206
1207 #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
1208 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
1209
1210 #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
1211 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
1212
1213 #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
1214 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
1215
1216 #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
1217 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
1218
1219 #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
1220 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
1221
1222 #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
1223 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
1224
1225 /* DWT CPI Count Register Definitions */
1226 #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
1227 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
1228
1229 /* DWT Exception Overhead Count Register Definitions */
1230 #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
1231 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
1232
1233 /* DWT Sleep Count Register Definitions */
1234 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
1235 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1236
1237 /* DWT LSU Count Register Definitions */
1238 #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
1239 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
1240
1241 /* DWT Folded-instruction Count Register Definitions */
1242 #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
1243 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
1244
1245 /* DWT Comparator Mask Register Definitions */
1246 #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
1247 #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
1248
1249 /* DWT Comparator Function Register Definitions */
1250 #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
1251 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
1252
1253 #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
1254 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
1255
1256 #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
1257 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
1258
1259 #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
1260 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
1261
1262 #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
1263 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
1264
1265 #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
1266 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
1267
1268 #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
1269 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
1270
1271 #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
1272 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
1273
1274 #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
1275 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
1276
1277 /*@}*/ /* end of group CMSIS_DWT */
1278
1279
1280 /**
1281   \ingroup  CMSIS_core_register
1282   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
1283   \brief    Type definitions for the Trace Port Interface (TPI)
1284   @{
1285  */
1286
1287 /**
1288   \brief  Structure type to access the Trace Port Interface Register (TPI).
1289  */
1290 typedef struct
1291 {
1292   __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
1293   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
1294         uint32_t RESERVED0[2U];
1295   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
1296         uint32_t RESERVED1[55U];
1297   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
1298         uint32_t RESERVED2[131U];
1299   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
1300   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
1301   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
1302         uint32_t RESERVED3[759U];
1303   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
1304   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
1305   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
1306         uint32_t RESERVED4[1U];
1307   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
1308   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
1309   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
1310         uint32_t RESERVED5[39U];
1311   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
1312   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
1313         uint32_t RESERVED7[8U];
1314   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
1315   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
1316 } TPI_Type;
1317
1318 /* TPI Asynchronous Clock Prescaler Register Definitions */
1319 #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
1320 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
1321
1322 /* TPI Selected Pin Protocol Register Definitions */
1323 #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
1324 #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
1325
1326 /* TPI Formatter and Flush Status Register Definitions */
1327 #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
1328 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
1329
1330 #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
1331 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
1332
1333 #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
1334 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
1335
1336 #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
1337 #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
1338
1339 /* TPI Formatter and Flush Control Register Definitions */
1340 #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
1341 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
1342
1343 #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
1344 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
1345
1346 /* TPI TRIGGER Register Definitions */
1347 #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
1348 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
1349
1350 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1351 #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
1352 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
1353
1354 #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
1355 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
1356
1357 #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
1358 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
1359
1360 #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
1361 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
1362
1363 #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
1364 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
1365
1366 #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
1367 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
1368
1369 #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
1370 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
1371
1372 /* TPI ITATBCTR2 Register Definitions */
1373 #define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
1374 #define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
1375
1376 #define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
1377 #define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
1378
1379 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1380 #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
1381 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
1382
1383 #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
1384 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
1385
1386 #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
1387 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
1388
1389 #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
1390 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
1391
1392 #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
1393 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
1394
1395 #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
1396 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
1397
1398 #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
1399 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
1400
1401 /* TPI ITATBCTR0 Register Definitions */
1402 #define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
1403 #define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
1404
1405 #define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
1406 #define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
1407
1408 /* TPI Integration Mode Control Register Definitions */
1409 #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
1410 #define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
1411
1412 /* TPI DEVID Register Definitions */
1413 #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
1414 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
1415
1416 #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
1417 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
1418
1419 #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
1420 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
1421
1422 #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
1423 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
1424
1425 #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
1426 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
1427
1428 #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
1429 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
1430
1431 /* TPI DEVTYPE Register Definitions */
1432 #define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
1433 #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
1434
1435 #define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
1436 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
1437
1438 /*@}*/ /* end of group CMSIS_TPI */
1439
1440
1441 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1442 /**
1443   \ingroup  CMSIS_core_register
1444   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
1445   \brief    Type definitions for the Memory Protection Unit (MPU)
1446   @{
1447  */
1448
1449 /**
1450   \brief  Structure type to access the Memory Protection Unit (MPU).
1451  */
1452 typedef struct
1453 {
1454   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
1455   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
1456   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
1457   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
1458   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
1459   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
1460   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
1461   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
1462   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
1463   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
1464   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
1465 } MPU_Type;
1466
1467 #define MPU_TYPE_RALIASES                  4U
1468
1469 /* MPU Type Register Definitions */
1470 #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
1471 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
1472
1473 #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
1474 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
1475
1476 #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
1477 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
1478
1479 /* MPU Control Register Definitions */
1480 #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
1481 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
1482
1483 #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
1484 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
1485
1486 #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
1487 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
1488
1489 /* MPU Region Number Register Definitions */
1490 #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
1491 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
1492
1493 /* MPU Region Base Address Register Definitions */
1494 #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
1495 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
1496
1497 #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
1498 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
1499
1500 #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
1501 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
1502
1503 /* MPU Region Attribute and Size Register Definitions */
1504 #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
1505 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
1506
1507 #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
1508 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
1509
1510 #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
1511 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
1512
1513 #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
1514 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
1515
1516 #define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
1517 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
1518
1519 #define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
1520 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
1521
1522 #define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
1523 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
1524
1525 #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
1526 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
1527
1528 #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
1529 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
1530
1531 #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
1532 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
1533
1534 /*@} end of group CMSIS_MPU */
1535 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1536
1537
1538 /**
1539   \ingroup  CMSIS_core_register
1540   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
1541   \brief    Type definitions for the Floating Point Unit (FPU)
1542   @{
1543  */
1544
1545 /**
1546   \brief  Structure type to access the Floating Point Unit (FPU).
1547  */
1548 typedef struct
1549 {
1550         uint32_t RESERVED0[1U];
1551   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
1552   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
1553   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
1554   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
1555   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
1556   __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
1557 } FPU_Type;
1558
1559 /* Floating-Point Context Control Register Definitions */
1560 #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
1561 #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
1562
1563 #define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
1564 #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
1565
1566 #define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
1567 #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
1568
1569 #define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
1570 #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
1571
1572 #define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
1573 #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
1574
1575 #define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
1576 #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
1577
1578 #define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
1579 #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
1580
1581 #define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
1582 #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
1583
1584 #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
1585 #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
1586
1587 /* Floating-Point Context Address Register Definitions */
1588 #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
1589 #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
1590
1591 /* Floating-Point Default Status Control Register Definitions */
1592 #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
1593 #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
1594
1595 #define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
1596 #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
1597
1598 #define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
1599 #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
1600
1601 #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
1602 #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
1603
1604 /* Media and FP Feature Register 0 Definitions */
1605 #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
1606 #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
1607
1608 #define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
1609 #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
1610
1611 #define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
1612 #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
1613
1614 #define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
1615 #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
1616
1617 #define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
1618 #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
1619
1620 #define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
1621 #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
1622
1623 #define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
1624 #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
1625
1626 #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
1627 #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
1628
1629 /* Media and FP Feature Register 1 Definitions */
1630 #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
1631 #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
1632
1633 #define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
1634 #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
1635
1636 #define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
1637 #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
1638
1639 #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
1640 #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
1641
1642 /* Media and FP Feature Register 2 Definitions */
1643
1644 #define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */
1645 #define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */
1646
1647 /*@} end of group CMSIS_FPU */
1648
1649
1650 /**
1651   \ingroup  CMSIS_core_register
1652   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
1653   \brief    Type definitions for the Core Debug Registers
1654   @{
1655  */
1656
1657 /**
1658   \brief  Structure type to access the Core Debug Register (CoreDebug).
1659  */
1660 typedef struct
1661 {
1662   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
1663   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
1664   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
1665   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
1666 } CoreDebug_Type;
1667
1668 /* Debug Halting Control and Status Register Definitions */
1669 #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
1670 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
1671
1672 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
1673 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1674
1675 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1676 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1677
1678 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
1679 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1680
1681 #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
1682 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
1683
1684 #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
1685 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
1686
1687 #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
1688 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
1689
1690 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1691 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1692
1693 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
1694 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1695
1696 #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
1697 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
1698
1699 #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
1700 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
1701
1702 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1703 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1704
1705 /* Debug Core Register Selector Register Definitions */
1706 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
1707 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
1708
1709 #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
1710 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
1711
1712 /* Debug Exception and Monitor Control Register Definitions */
1713 #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
1714 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
1715
1716 #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
1717 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
1718
1719 #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
1720 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
1721
1722 #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
1723 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
1724
1725 #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
1726 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
1727
1728 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
1729 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1730
1731 #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
1732 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
1733
1734 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
1735 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1736
1737 #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
1738 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
1739
1740 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
1741 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1742
1743 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1744 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1745
1746 #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
1747 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
1748
1749 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
1750 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1751
1752 /*@} end of group CMSIS_CoreDebug */
1753
1754
1755 /**
1756   \ingroup    CMSIS_core_register
1757   \defgroup   CMSIS_core_bitfield     Core register bit field macros
1758   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1759   @{
1760  */
1761
1762 /**
1763   \brief   Mask and shift a bit field value for use in a register bit range.
1764   \param[in] field  Name of the register bit field.
1765   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
1766   \return           Masked and shifted value.
1767 */
1768 #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1769
1770 /**
1771   \brief     Mask and shift a register value to extract a bit filed value.
1772   \param[in] field  Name of the register bit field.
1773   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
1774   \return           Masked and shifted bit field value.
1775 */
1776 #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1777
1778 /*@} end of group CMSIS_core_bitfield */
1779
1780
1781 /**
1782   \ingroup    CMSIS_core_register
1783   \defgroup   CMSIS_core_base     Core Definitions
1784   \brief      Definitions for base addresses, unions, and structures.
1785   @{
1786  */
1787
1788 /* Memory mapping of Core Hardware */
1789 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
1790 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
1791 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
1792 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
1793 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
1794 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
1795 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
1796 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
1797
1798 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
1799 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
1800 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
1801 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
1802 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
1803 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
1804 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
1805 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
1806
1807 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1808   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
1809   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
1810 #endif
1811
1812 #define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
1813 #define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
1814
1815 /*@} */
1816
1817
1818 /**
1819   \ingroup    CMSIS_core_register
1820   \defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases
1821   \brief      Register alias definitions for backwards compatibility.
1822   @{
1823  */
1824
1825 /* Capitalize ITM_TCR Register Definitions */
1826
1827 /* ITM Trace Control Register Definitions */
1828 #define ITM_TCR_TraceBusID_Pos           (ITM_TCR_TRACEBUSID_Pos)     /*!< \deprecated ITM_TCR_TraceBusID_Pos */
1829 #define ITM_TCR_TraceBusID_Msk           (ITM_TCR_TRACEBUSID_Msk)     /*!< \deprecated ITM_TCR_TraceBusID_Msk */
1830
1831 #define ITM_TCR_TSPrescale_Pos           (ITM_TCR_TSPRESCALE_Pos)     /*!< \deprecated ITM_TCR_TSPrescale_Pos */
1832 #define ITM_TCR_TSPrescale_Msk           (ITM_TCR_TSPRESCALE_Msk)     /*!< \deprecated ITM_TCR_TSPrescale_Msk */
1833
1834 /* ITM Lock Status Register Definitions */
1835 #define ITM_LSR_ByteAcc_Pos              (ITM_LSR_BYTEACC_Pos)        /*!< \deprecated ITM_LSR_ByteAcc_Pos */
1836 #define ITM_LSR_ByteAcc_Msk              (ITM_LSR_BYTEACC_Msk)        /*!< \deprecated ITM_LSR_ByteAcc_Msk */
1837
1838 #define ITM_LSR_Access_Pos               (ITM_LSR_ACCESS_Pos)         /*!< \deprecated ITM_LSR_Access_Pos */
1839 #define ITM_LSR_Access_Msk               (ITM_LSR_ACCESS_Msk)         /*!< \deprecated ITM_LSR_Access_Msk */
1840
1841 #define ITM_LSR_Present_Pos              (ITM_LSR_PRESENT_Pos)        /*!< \deprecated ITM_LSR_Present_Pos */
1842 #define ITM_LSR_Present_Msk              (ITM_LSR_PRESENT_Msk)        /*!< \deprecated ITM_LSR_Present_Msk */
1843
1844 /*@} */
1845
1846
1847
1848 /*******************************************************************************
1849  *                Hardware Abstraction Layer
1850   Core Function Interface contains:
1851   - Core NVIC Functions
1852   - Core SysTick Functions
1853   - Core Debug Functions
1854   - Core Register Access Functions
1855  ******************************************************************************/
1856 /**
1857   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1858 */
1859
1860
1861
1862 /* ##########################   NVIC functions  #################################### */
1863 /**
1864   \ingroup  CMSIS_Core_FunctionInterface
1865   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1866   \brief    Functions that manage interrupts and exceptions via the NVIC.
1867   @{
1868  */
1869
1870 #ifdef CMSIS_NVIC_VIRTUAL
1871   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1872     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1873   #endif
1874   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1875 #else
1876   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
1877   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
1878   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
1879   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
1880   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
1881   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
1882   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
1883   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
1884   #define NVIC_GetActive              __NVIC_GetActive
1885   #define NVIC_SetPriority            __NVIC_SetPriority
1886   #define NVIC_GetPriority            __NVIC_GetPriority
1887   #define NVIC_SystemReset            __NVIC_SystemReset
1888 #endif /* CMSIS_NVIC_VIRTUAL */
1889
1890 #ifdef CMSIS_VECTAB_VIRTUAL
1891   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1892     #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1893   #endif
1894   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1895 #else
1896   #define NVIC_SetVector              __NVIC_SetVector
1897   #define NVIC_GetVector              __NVIC_GetVector
1898 #endif  /* (CMSIS_VECTAB_VIRTUAL) */
1899
1900 #define NVIC_USER_IRQ_OFFSET          16
1901
1902
1903 /* The following EXC_RETURN values are saved the LR on exception entry */
1904 #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
1905 #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
1906 #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
1907 #define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
1908 #define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
1909 #define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
1910
1911
1912 /**
1913   \brief   Set Priority Grouping
1914   \details Sets the priority grouping field using the required unlock sequence.
1915            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1916            Only values from 0..7 are used.
1917            In case of a conflict between priority grouping and available
1918            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1919   \param [in]      PriorityGroup  Priority grouping field.
1920  */
1921 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1922 {
1923   uint32_t reg_value;
1924   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
1925
1926   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
1927   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
1928   reg_value  =  (reg_value                                   |
1929                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1930                 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
1931   SCB->AIRCR =  reg_value;
1932 }
1933
1934
1935 /**
1936   \brief   Get Priority Grouping
1937   \details Reads the priority grouping field from the NVIC Interrupt Controller.
1938   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1939  */
1940 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1941 {
1942   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1943 }
1944
1945
1946 /**
1947   \brief   Enable Interrupt
1948   \details Enables a device specific interrupt in the NVIC interrupt controller.
1949   \param [in]      IRQn  Device specific interrupt number.
1950   \note    IRQn must not be negative.
1951  */
1952 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1953 {
1954   if ((int32_t)(IRQn) >= 0)
1955   {
1956     __COMPILER_BARRIER();
1957     NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1958     __COMPILER_BARRIER();
1959   }
1960 }
1961
1962
1963 /**
1964   \brief   Get Interrupt Enable status
1965   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1966   \param [in]      IRQn  Device specific interrupt number.
1967   \return             0  Interrupt is not enabled.
1968   \return             1  Interrupt is enabled.
1969   \note    IRQn must not be negative.
1970  */
1971 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1972 {
1973   if ((int32_t)(IRQn) >= 0)
1974   {
1975     return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1976   }
1977   else
1978   {
1979     return(0U);
1980   }
1981 }
1982
1983
1984 /**
1985   \brief   Disable Interrupt
1986   \details Disables a device specific interrupt in the NVIC interrupt controller.
1987   \param [in]      IRQn  Device specific interrupt number.
1988   \note    IRQn must not be negative.
1989  */
1990 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1991 {
1992   if ((int32_t)(IRQn) >= 0)
1993   {
1994     NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1995     __DSB();
1996     __ISB();
1997   }
1998 }
1999
2000
2001 /**
2002   \brief   Get Pending Interrupt
2003   \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2004   \param [in]      IRQn  Device specific interrupt number.
2005   \return             0  Interrupt status is not pending.
2006   \return             1  Interrupt status is pending.
2007   \note    IRQn must not be negative.
2008  */
2009 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2010 {
2011   if ((int32_t)(IRQn) >= 0)
2012   {
2013     return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2014   }
2015   else
2016   {
2017     return(0U);
2018   }
2019 }
2020
2021
2022 /**
2023   \brief   Set Pending Interrupt
2024   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2025   \param [in]      IRQn  Device specific interrupt number.
2026   \note    IRQn must not be negative.
2027  */
2028 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2029 {
2030   if ((int32_t)(IRQn) >= 0)
2031   {
2032     NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2033   }
2034 }
2035
2036
2037 /**
2038   \brief   Clear Pending Interrupt
2039   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2040   \param [in]      IRQn  Device specific interrupt number.
2041   \note    IRQn must not be negative.
2042  */
2043 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2044 {
2045   if ((int32_t)(IRQn) >= 0)
2046   {
2047     NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2048   }
2049 }
2050
2051
2052 /**
2053   \brief   Get Active Interrupt
2054   \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2055   \param [in]      IRQn  Device specific interrupt number.
2056   \return             0  Interrupt status is not active.
2057   \return             1  Interrupt status is active.
2058   \note    IRQn must not be negative.
2059  */
2060 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2061 {
2062   if ((int32_t)(IRQn) >= 0)
2063   {
2064     return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2065   }
2066   else
2067   {
2068     return(0U);
2069   }
2070 }
2071
2072
2073 /**
2074   \brief   Set Interrupt Priority
2075   \details Sets the priority of a device specific interrupt or a processor exception.
2076            The interrupt number can be positive to specify a device specific interrupt,
2077            or negative to specify a processor exception.
2078   \param [in]      IRQn  Interrupt number.
2079   \param [in]  priority  Priority to set.
2080   \note    The priority cannot be set for every processor exception.
2081  */
2082 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2083 {
2084   if ((int32_t)(IRQn) >= 0)
2085   {
2086     NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2087   }
2088   else
2089   {
2090     SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2091   }
2092 }
2093
2094
2095 /**
2096   \brief   Get Interrupt Priority
2097   \details Reads the priority of a device specific interrupt or a processor exception.
2098            The interrupt number can be positive to specify a device specific interrupt,
2099            or negative to specify a processor exception.
2100   \param [in]   IRQn  Interrupt number.
2101   \return             Interrupt Priority.
2102                       Value is aligned automatically to the implemented priority bits of the microcontroller.
2103  */
2104 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2105 {
2106
2107   if ((int32_t)(IRQn) >= 0)
2108   {
2109     return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
2110   }
2111   else
2112   {
2113     return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2114   }
2115 }
2116
2117
2118 /**
2119   \brief   Encode Priority
2120   \details Encodes the priority for an interrupt with the given priority group,
2121            preemptive priority value, and subpriority value.
2122            In case of a conflict between priority grouping and available
2123            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2124   \param [in]     PriorityGroup  Used priority group.
2125   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
2126   \param [in]       SubPriority  Subpriority value (starting from 0).
2127   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2128  */
2129 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2130 {
2131   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
2132   uint32_t PreemptPriorityBits;
2133   uint32_t SubPriorityBits;
2134
2135   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2136   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2137
2138   return (
2139            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2140            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
2141          );
2142 }
2143
2144
2145 /**
2146   \brief   Decode Priority
2147   \details Decodes an interrupt priority value with a given priority group to
2148            preemptive priority value and subpriority value.
2149            In case of a conflict between priority grouping and available
2150            priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2151   \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2152   \param [in]     PriorityGroup  Used priority group.
2153   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
2154   \param [out]     pSubPriority  Subpriority value (starting from 0).
2155  */
2156 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2157 {
2158   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
2159   uint32_t PreemptPriorityBits;
2160   uint32_t SubPriorityBits;
2161
2162   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2163   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2164
2165   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2166   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
2167 }
2168
2169
2170 /**
2171   \brief   Set Interrupt Vector
2172   \details Sets an interrupt vector in SRAM based interrupt vector table.
2173            The interrupt number can be positive to specify a device specific interrupt,
2174            or negative to specify a processor exception.
2175            VTOR must been relocated to SRAM before.
2176   \param [in]   IRQn      Interrupt number
2177   \param [in]   vector    Address of interrupt handler function
2178  */
2179 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2180 {
2181   uint32_t *vectors = (uint32_t *)SCB->VTOR;
2182   vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2183   __DSB();
2184 }
2185
2186
2187 /**
2188   \brief   Get Interrupt Vector
2189   \details Reads an interrupt vector from interrupt vector table.
2190            The interrupt number can be positive to specify a device specific interrupt,
2191            or negative to specify a processor exception.
2192   \param [in]   IRQn      Interrupt number.
2193   \return                 Address of interrupt handler function
2194  */
2195 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2196 {
2197   uint32_t *vectors = (uint32_t *)SCB->VTOR;
2198   return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2199 }
2200
2201
2202 /**
2203   \brief   System Reset
2204   \details Initiates a system reset request to reset the MCU.
2205  */
2206 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2207 {
2208   __DSB();                                                          /* Ensure all outstanding memory accesses included
2209                                                                        buffered write are completed before reset */
2210   SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
2211                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2212                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
2213   __DSB();                                                          /* Ensure completion of memory access */
2214
2215   for(;;)                                                           /* wait until reset */
2216   {
2217     __NOP();
2218   }
2219 }
2220
2221 /*@} end of CMSIS_Core_NVICFunctions */
2222
2223
2224 /* ##########################  MPU functions  #################################### */
2225
2226 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2227
2228 #include "mpu_armv7.h"
2229
2230 #endif
2231
2232
2233 /* ##########################  FPU functions  #################################### */
2234 /**
2235   \ingroup  CMSIS_Core_FunctionInterface
2236   \defgroup CMSIS_Core_FpuFunctions FPU Functions
2237   \brief    Function that provides FPU type.
2238   @{
2239  */
2240
2241 /**
2242   \brief   get FPU type
2243   \details returns the FPU type
2244   \returns
2245    - \b  0: No FPU
2246    - \b  1: Single precision FPU
2247    - \b  2: Double + Single precision FPU
2248  */
2249 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2250 {
2251   uint32_t mvfr0;
2252
2253   mvfr0 = SCB->MVFR0;
2254   if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2255   {
2256     return 2U;           /* Double + Single precision FPU */
2257   }
2258   else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2259   {
2260     return 1U;           /* Single precision FPU */
2261   }
2262   else
2263   {
2264     return 0U;           /* No FPU */
2265   }
2266 }
2267
2268 /*@} end of CMSIS_Core_FpuFunctions */
2269
2270
2271 /* ##########################  Cache functions  #################################### */
2272
2273 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
2274      (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
2275 #include "cachel1_armv7.h"
2276 #endif
2277
2278
2279 /* ##################################    SysTick function  ############################################ */
2280 /**
2281   \ingroup  CMSIS_Core_FunctionInterface
2282   \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2283   \brief    Functions that configure the System.
2284   @{
2285  */
2286
2287 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2288
2289 /**
2290   \brief   System Tick Configuration
2291   \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2292            Counter is in free running mode to generate periodic interrupts.
2293   \param [in]  ticks  Number of ticks between two interrupts.
2294   \return          0  Function succeeded.
2295   \return          1  Function failed.
2296   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2297            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2298            must contain a vendor-specific implementation of this function.
2299  */
2300 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2301 {
2302   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2303   {
2304     return (1UL);                                                   /* Reload value impossible */
2305   }
2306
2307   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
2308   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2309   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
2310   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
2311                    SysTick_CTRL_TICKINT_Msk   |
2312                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
2313   return (0UL);                                                     /* Function successful */
2314 }
2315
2316 #endif
2317
2318 /*@} end of CMSIS_Core_SysTickFunctions */
2319
2320
2321
2322 /* ##################################### Debug In/Output function ########################################### */
2323 /**
2324   \ingroup  CMSIS_Core_FunctionInterface
2325   \defgroup CMSIS_core_DebugFunctions ITM Functions
2326   \brief    Functions that access the ITM debug interface.
2327   @{
2328  */
2329
2330 extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
2331 #define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2332
2333
2334 /**
2335   \brief   ITM Send Character
2336   \details Transmits a character via the ITM channel 0, and
2337            \li Just returns when no debugger is connected that has booked the output.
2338            \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2339   \param [in]     ch  Character to transmit.
2340   \returns            Character to transmit.
2341  */
2342 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2343 {
2344   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
2345       ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
2346   {
2347     while (ITM->PORT[0U].u32 == 0UL)
2348     {
2349       __NOP();
2350     }
2351     ITM->PORT[0U].u8 = (uint8_t)ch;
2352   }
2353   return (ch);
2354 }
2355
2356
2357 /**
2358   \brief   ITM Receive Character
2359   \details Inputs a character via the external variable \ref ITM_RxBuffer.
2360   \return             Received character.
2361   \return         -1  No character pending.
2362  */
2363 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2364 {
2365   int32_t ch = -1;                           /* no character available */
2366
2367   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2368   {
2369     ch = ITM_RxBuffer;
2370     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
2371   }
2372
2373   return (ch);
2374 }
2375
2376
2377 /**
2378   \brief   ITM Check Character
2379   \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2380   \return          0  No character available.
2381   \return          1  Character available.
2382  */
2383 __STATIC_INLINE int32_t ITM_CheckChar (void)
2384 {
2385
2386   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2387   {
2388     return (0);                              /* no character available */
2389   }
2390   else
2391   {
2392     return (1);                              /*    character available */
2393   }
2394 }
2395
2396 /*@} end of CMSIS_core_DebugFunctions */
2397
2398
2399
2400
2401 #ifdef __cplusplus
2402 }
2403 #endif
2404
2405 #endif /* __CORE_CM7_H_DEPENDANT */
2406
2407 #endif /* __CMSIS_GENERIC */