arm/include/core_cm4.h

0001 /**************************************************************************//**
0002  * @file     core_cm4.h
0003  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
0004  * @version  V5.2.0
0005  * @date     04. April 2023
0006  ******************************************************************************/
0007 /*
0008  * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
0009  *
0010  * SPDX-License-Identifier: Apache-2.0
0011  *
0012  * Licensed under the Apache License, Version 2.0 (the License); you may
0013  * not use this file except in compliance with the License.
0014  * You may obtain a copy of the License at
0015  *
0016  * www.apache.org/licenses/LICENSE-2.0
0017  *
0018  * Unless required by applicable law or agreed to in writing, software
0019  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
0020  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
0021  * See the License for the specific language governing permissions and
0022  * limitations under the License.
0023  */
0024
0025 #if   defined ( __ICCARM__ )
0026   #pragma system_include         /* treat file as system include file for MISRA check */
0027 #elif defined (__clang__)
0028   #pragma clang system_header   /* treat file as system include file */
0029 #endif
0030
0031 #ifndef __CORE_CM4_H_GENERIC
0032 #define __CORE_CM4_H_GENERIC
0033
0034 #include <stdint.h>
0035
0036 #ifdef __cplusplus
0037  extern "C" {
0038 #endif
0039
0040 /**
0041   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
0042   CMSIS violates the following MISRA-C:2004 rules:
0043
0044    \li Required Rule 8.5, object/function definition in header file.<br>
0045      Function definitions in header files are used to allow 'inlining'.
0046
0047    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
0048      Unions are used for effective representation of core registers.
0049
0050    \li Advisory Rule 19.7, Function-like macro defined.<br>
0051      Function-like macros are used to allow more efficient code.
0052  */
0053
0054
0055 /*******************************************************************************
0056  *                 CMSIS definitions
0057  ******************************************************************************/
0058 /**
0059   \ingroup Cortex_M4
0060   @{
0061  */
0062
0063 #include "cmsis_version.h"
0064
0065 /* CMSIS CM4 definitions */
0066 #define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
0067 #define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
0068 #define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
0069                                     __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
0070
0071 #define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
0072
0073 /** __FPU_USED indicates whether an FPU is used or not.
0074     For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
0075 */
0076 #if defined ( __CC_ARM )
0077   #if defined __TARGET_FPU_VFP
0078     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0079       #define __FPU_USED       1U
0080     #else
0081       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0082       #define __FPU_USED       0U
0083     #endif
0084   #else
0085     #define __FPU_USED         0U
0086   #endif
0087
0088 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
0089   #if defined __ARM_FP
0090     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0091       #define __FPU_USED       1U
0092     #else
0093       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0094       #define __FPU_USED       0U
0095     #endif
0096   #else
0097     #define __FPU_USED         0U
0098   #endif
0099
0100 #elif defined (__ti__)
0101   #if defined (__ARM_FP)
0102     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0103       #define __FPU_USED       1U
0104     #else
0105       #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0106       #define __FPU_USED       0U
0107     #endif
0108   #else
0109     #define __FPU_USED         0U
0110   #endif
0111
0112 #elif defined ( __GNUC__ )
0113   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
0114     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0115       #define __FPU_USED       1U
0116     #else
0117       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0118       #define __FPU_USED       0U
0119     #endif
0120   #else
0121     #define __FPU_USED         0U
0122   #endif
0123
0124 #elif defined ( __ICCARM__ )
0125   #if defined __ARMVFP__
0126     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0127       #define __FPU_USED       1U
0128     #else
0129       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0130       #define __FPU_USED       0U
0131     #endif
0132   #else
0133     #define __FPU_USED         0U
0134   #endif
0135
0136 #elif defined ( __TI_ARM__ )
0137   #if defined __TI_VFP_SUPPORT__
0138     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0139       #define __FPU_USED       1U
0140     #else
0141       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0142       #define __FPU_USED       0U
0143     #endif
0144   #else
0145     #define __FPU_USED         0U
0146   #endif
0147
0148 #elif defined ( __TASKING__ )
0149   #if defined __FPU_VFP__
0150     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0151       #define __FPU_USED       1U
0152     #else
0153       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0154       #define __FPU_USED       0U
0155     #endif
0156   #else
0157     #define __FPU_USED         0U
0158   #endif
0159
0160 #elif defined ( __CSMC__ )
0161   #if ( __CSMC__ & 0x400U)
0162     #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
0163       #define __FPU_USED       1U
0164     #else
0165       #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
0166       #define __FPU_USED       0U
0167     #endif
0168   #else
0169     #define __FPU_USED         0U
0170   #endif
0171
0172 #endif
0173
0174 #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
0175
0176
0177 #ifdef __cplusplus
0178 }
0179 #endif
0180
0181 #endif /* __CORE_CM4_H_GENERIC */
0182
0183 #ifndef __CMSIS_GENERIC
0184
0185 #ifndef __CORE_CM4_H_DEPENDANT
0186 #define __CORE_CM4_H_DEPENDANT
0187
0188 #ifdef __cplusplus
0189  extern "C" {
0190 #endif
0191
0192 /* check device defines and use defaults */
0193 #if defined __CHECK_DEVICE_DEFINES
0194   #ifndef __CM4_REV
0195     #define __CM4_REV               0x0000U
0196     #warning "__CM4_REV not defined in device header file; using default!"
0197   #endif
0198
0199   #ifndef __FPU_PRESENT
0200     #define __FPU_PRESENT             0U
0201     #warning "__FPU_PRESENT not defined in device header file; using default!"
0202   #endif
0203
0204   #ifndef __MPU_PRESENT
0205     #define __MPU_PRESENT             0U
0206     #warning "__MPU_PRESENT not defined in device header file; using default!"
0207   #endif
0208
0209   #ifndef __VTOR_PRESENT
0210     #define __VTOR_PRESENT             1U
0211     #warning "__VTOR_PRESENT not defined in device header file; using default!"
0212   #endif
0213
0214   #ifndef __NVIC_PRIO_BITS
0215     #define __NVIC_PRIO_BITS          3U
0216     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
0217   #endif
0218
0219   #ifndef __Vendor_SysTickConfig
0220     #define __Vendor_SysTickConfig    0U
0221     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
0222   #endif
0223 #endif
0224
0225 /* IO definitions (access restrictions to peripheral registers) */
0226 /**
0227     \defgroup CMSIS_glob_defs CMSIS Global Defines
0228
0229     <strong>IO Type Qualifiers</strong> are used
0230     \li to specify the access to peripheral variables.
0231     \li for automatic generation of peripheral register debug information.
0232 */
0233 #ifdef __cplusplus
0234   #define   __I     volatile             /*!< Defines 'read only' permissions */
0235 #else
0236   #define   __I     volatile const       /*!< Defines 'read only' permissions */
0237 #endif
0238 #define     __O     volatile             /*!< Defines 'write only' permissions */
0239 #define     __IO    volatile             /*!< Defines 'read / write' permissions */
0240
0241 /* following defines should be used for structure members */
0242 #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
0243 #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
0244 #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
0245
0246 /*@} end of group Cortex_M4 */
0247
0248
0249
0250 /*******************************************************************************
0251  *                 Register Abstraction
0252   Core Register contain:
0253   - Core Register
0254   - Core NVIC Register
0255   - Core SCB Register
0256   - Core SysTick Register
0257   - Core Debug Register
0258   - Core MPU Register
0259   - Core FPU Register
0260  ******************************************************************************/
0261 /**
0262   \defgroup CMSIS_core_register Defines and Type Definitions
0263   \brief Type definitions and defines for Cortex-M processor based devices.
0264 */
0265
0266 /**
0267   \ingroup    CMSIS_core_register
0268   \defgroup   CMSIS_CORE  Status and Control Registers
0269   \brief      Core Register type definitions.
0270   @{
0271  */
0272
0273 /**
0274   \brief  Union type to access the Application Program Status Register (APSR).
0275  */
0276 typedef union
0277 {
0278   struct
0279   {
0280     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
0281     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
0282     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
0283     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
0284     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
0285     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
0286     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
0287     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
0288   } b;                                   /*!< Structure used for bit  access */
0289   uint32_t w;                            /*!< Type      used for word access */
0290 } APSR_Type;
0291
0292 /* APSR Register Definitions */
0293 #define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
0294 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
0295
0296 #define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
0297 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
0298
0299 #define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
0300 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
0301
0302 #define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
0303 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
0304
0305 #define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
0306 #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
0307
0308 #define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
0309 #define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
0310
0311
0312 /**
0313   \brief  Union type to access the Interrupt Program Status Register (IPSR).
0314  */
0315 typedef union
0316 {
0317   struct
0318   {
0319     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
0320     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
0321   } b;                                   /*!< Structure used for bit  access */
0322   uint32_t w;                            /*!< Type      used for word access */
0323 } IPSR_Type;
0324
0325 /* IPSR Register Definitions */
0326 #define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
0327 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
0328
0329
0330 /**
0331   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
0332  */
0333 typedef union
0334 {
0335   struct
0336   {
0337     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
0338     uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
0339     uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
0340     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
0341     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
0342     uint32_t T:1;                        /*!< bit:     24  Thumb bit */
0343     uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
0344     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
0345     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
0346     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
0347     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
0348     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
0349   } b;                                   /*!< Structure used for bit  access */
0350   uint32_t w;                            /*!< Type      used for word access */
0351 } xPSR_Type;
0352
0353 /* xPSR Register Definitions */
0354 #define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
0355 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
0356
0357 #define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
0358 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
0359
0360 #define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
0361 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
0362
0363 #define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
0364 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
0365
0366 #define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
0367 #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
0368
0369 #define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
0370 #define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
0371
0372 #define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
0373 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
0374
0375 #define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
0376 #define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
0377
0378 #define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
0379 #define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
0380
0381 #define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
0382 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
0383
0384
0385 /**
0386   \brief  Union type to access the Control Registers (CONTROL).
0387  */
0388 typedef union
0389 {
0390   struct
0391   {
0392     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
0393     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
0394     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
0395     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
0396   } b;                                   /*!< Structure used for bit  access */
0397   uint32_t w;                            /*!< Type      used for word access */
0398 } CONTROL_Type;
0399
0400 /* CONTROL Register Definitions */
0401 #define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
0402 #define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
0403
0404 #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
0405 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
0406
0407 #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
0408 #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
0409
0410 /*@} end of group CMSIS_CORE */
0411
0412
0413 /**
0414   \ingroup    CMSIS_core_register
0415   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
0416   \brief      Type definitions for the NVIC Registers
0417   @{
0418  */
0419
0420 /**
0421   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
0422  */
0423 typedef struct
0424 {
0425   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
0426         uint32_t RESERVED0[24U];
0427   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
0428         uint32_t RESERVED1[24U];
0429   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
0430         uint32_t RESERVED2[24U];
0431   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
0432         uint32_t RESERVED3[24U];
0433   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
0434         uint32_t RESERVED4[56U];
0435   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
0436         uint32_t RESERVED5[644U];
0437   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
0438 }  NVIC_Type;
0439
0440 /* Software Triggered Interrupt Register Definitions */
0441 #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
0442 #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
0443
0444 /*@} end of group CMSIS_NVIC */
0445
0446
0447 /**
0448   \ingroup  CMSIS_core_register
0449   \defgroup CMSIS_SCB     System Control Block (SCB)
0450   \brief    Type definitions for the System Control Block Registers
0451   @{
0452  */
0453
0454 /**
0455   \brief  Structure type to access the System Control Block (SCB).
0456  */
0457 typedef struct
0458 {
0459   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
0460   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
0461   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
0462   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
0463   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
0464   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
0465   __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
0466   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
0467   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
0468   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
0469   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
0470   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
0471   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
0472   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
0473   __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
0474   __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
0475   __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
0476   __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
0477   __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
0478         uint32_t RESERVED0[5U];
0479   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
0480 } SCB_Type;
0481
0482 /* SCB CPUID Register Definitions */
0483 #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
0484 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
0485
0486 #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
0487 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
0488
0489 #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
0490 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
0491
0492 #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
0493 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
0494
0495 #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
0496 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
0497
0498 /* SCB Interrupt Control State Register Definitions */
0499 #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
0500 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
0501
0502 #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
0503 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
0504
0505 #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
0506 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
0507
0508 #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
0509 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
0510
0511 #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
0512 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
0513
0514 #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
0515 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
0516
0517 #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
0518 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
0519
0520 #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
0521 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
0522
0523 #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
0524 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
0525
0526 #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
0527 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
0528
0529 /* SCB Vector Table Offset Register Definitions */
0530 #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
0531 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
0532
0533 /* SCB Application Interrupt and Reset Control Register Definitions */
0534 #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
0535 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
0536
0537 #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
0538 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
0539
0540 #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
0541 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
0542
0543 #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
0544 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
0545
0546 #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
0547 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
0548
0549 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
0550 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
0551
0552 #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
0553 #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
0554
0555 /* SCB System Control Register Definitions */
0556 #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
0557 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
0558
0559 #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
0560 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
0561
0562 #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
0563 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
0564
0565 /* SCB Configuration Control Register Definitions */
0566 #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
0567 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
0568
0569 #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
0570 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
0571
0572 #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
0573 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
0574
0575 #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
0576 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
0577
0578 #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
0579 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
0580
0581 #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
0582 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
0583
0584 /* SCB System Handler Control and State Register Definitions */
0585 #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
0586 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
0587
0588 #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
0589 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
0590
0591 #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
0592 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
0593
0594 #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
0595 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
0596
0597 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
0598 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
0599
0600 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
0601 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
0602
0603 #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
0604 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
0605
0606 #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
0607 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
0608
0609 #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
0610 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
0611
0612 #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
0613 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
0614
0615 #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
0616 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
0617
0618 #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
0619 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
0620
0621 #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
0622 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
0623
0624 #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
0625 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
0626
0627 /* SCB Configurable Fault Status Register Definitions */
0628 #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
0629 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
0630
0631 #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
0632 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
0633
0634 #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
0635 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
0636
0637 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
0638 #define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */
0639 #define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
0640
0641 #define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */
0642 #define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
0643
0644 #define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */
0645 #define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
0646
0647 #define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
0648 #define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
0649
0650 #define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */
0651 #define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
0652
0653 #define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */
0654 #define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
0655
0656 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
0657 #define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
0658 #define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
0659
0660 #define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
0661 #define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
0662
0663 #define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
0664 #define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
0665
0666 #define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
0667 #define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
0668
0669 #define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
0670 #define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
0671
0672 #define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
0673 #define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
0674
0675 #define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
0676 #define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
0677
0678 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
0679 #define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
0680 #define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
0681
0682 #define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
0683 #define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
0684
0685 #define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
0686 #define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
0687
0688 #define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
0689 #define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
0690
0691 #define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
0692 #define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
0693
0694 #define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
0695 #define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
0696
0697 /* SCB Hard Fault Status Register Definitions */
0698 #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
0699 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
0700
0701 #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
0702 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
0703
0704 #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
0705 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
0706
0707 /* SCB Debug Fault Status Register Definitions */
0708 #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
0709 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
0710
0711 #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
0712 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
0713
0714 #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
0715 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
0716
0717 #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
0718 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
0719
0720 #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
0721 #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
0722
0723 /*@} end of group CMSIS_SCB */
0724
0725
0726 /**
0727   \ingroup  CMSIS_core_register
0728   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
0729   \brief    Type definitions for the System Control and ID Register not in the SCB
0730   @{
0731  */
0732
0733 /**
0734   \brief  Structure type to access the System Control and ID Register not in the SCB.
0735  */
0736 typedef struct
0737 {
0738         uint32_t RESERVED0[1U];
0739   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
0740   __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
0741 } SCnSCB_Type;
0742
0743 /* Interrupt Controller Type Register Definitions */
0744 #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
0745 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
0746
0747 /* Auxiliary Control Register Definitions */
0748 #define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
0749 #define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
0750
0751 #define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
0752 #define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
0753
0754 #define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
0755 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
0756
0757 #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
0758 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
0759
0760 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
0761 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
0762
0763 /*@} end of group CMSIS_SCnotSCB */
0764
0765
0766 /**
0767   \ingroup  CMSIS_core_register
0768   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
0769   \brief    Type definitions for the System Timer Registers.
0770   @{
0771  */
0772
0773 /**
0774   \brief  Structure type to access the System Timer (SysTick).
0775  */
0776 typedef struct
0777 {
0778   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
0779   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
0780   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
0781   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
0782 } SysTick_Type;
0783
0784 /* SysTick Control / Status Register Definitions */
0785 #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
0786 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
0787
0788 #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
0789 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
0790
0791 #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
0792 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
0793
0794 #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
0795 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
0796
0797 /* SysTick Reload Register Definitions */
0798 #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
0799 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
0800
0801 /* SysTick Current Register Definitions */
0802 #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
0803 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
0804
0805 /* SysTick Calibration Register Definitions */
0806 #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
0807 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
0808
0809 #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
0810 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
0811
0812 #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
0813 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
0814
0815 /*@} end of group CMSIS_SysTick */
0816
0817
0818 /**
0819   \ingroup  CMSIS_core_register
0820   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
0821   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
0822   @{
0823  */
0824
0825 /**
0826   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
0827  */
0828 typedef struct
0829 {
0830   __OM  union
0831   {
0832     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
0833     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
0834     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
0835   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
0836         uint32_t RESERVED0[864U];
0837   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
0838         uint32_t RESERVED1[15U];
0839   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
0840         uint32_t RESERVED2[15U];
0841   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
0842         uint32_t RESERVED3[32U];
0843         uint32_t RESERVED4[43U];
0844   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
0845   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
0846         uint32_t RESERVED5[6U];
0847   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
0848   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
0849   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
0850   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
0851   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
0852   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
0853   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
0854   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
0855   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
0856   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
0857   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
0858   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
0859 } ITM_Type;
0860
0861 /* ITM Trace Privilege Register Definitions */
0862 #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
0863 #define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
0864
0865 /* ITM Trace Control Register Definitions */
0866 #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
0867 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
0868
0869 #define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
0870 #define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
0871
0872 #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
0873 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
0874
0875 #define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
0876 #define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPrescale Mask */
0877
0878 #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
0879 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
0880
0881 #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
0882 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
0883
0884 #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
0885 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
0886
0887 #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
0888 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
0889
0890 #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
0891 #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
0892
0893 /* ITM Lock Status Register Definitions */
0894 #define ITM_LSR_BYTEACC_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
0895 #define ITM_LSR_BYTEACC_Msk                (1UL << ITM_LSR_BYTEACC_Pos)                   /*!< ITM LSR: ByteAcc Mask */
0896
0897 #define ITM_LSR_ACCESS_Pos                  1U                                            /*!< ITM LSR: Access Position */
0898 #define ITM_LSR_ACCESS_Msk                 (1UL << ITM_LSR_ACCESS_Pos)                    /*!< ITM LSR: Access Mask */
0899
0900 #define ITM_LSR_PRESENT_Pos                 0U                                            /*!< ITM LSR: Present Position */
0901 #define ITM_LSR_PRESENT_Msk                (1UL /*<< ITM_LSR_PRESENT_Pos*/)               /*!< ITM LSR: Present Mask */
0902
0903 /*@}*/ /* end of group CMSIS_ITM */
0904
0905
0906 /**
0907   \ingroup  CMSIS_core_register
0908   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
0909   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
0910   @{
0911  */
0912
0913 /**
0914   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
0915  */
0916 typedef struct
0917 {
0918   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
0919   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
0920   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
0921   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
0922   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
0923   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
0924   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
0925   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
0926   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
0927   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
0928   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
0929         uint32_t RESERVED0[1U];
0930   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
0931   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
0932   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
0933         uint32_t RESERVED1[1U];
0934   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
0935   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
0936   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
0937         uint32_t RESERVED2[1U];
0938   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
0939   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
0940   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
0941 } DWT_Type;
0942
0943 /* DWT Control Register Definitions */
0944 #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
0945 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
0946
0947 #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
0948 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
0949
0950 #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
0951 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
0952
0953 #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
0954 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
0955
0956 #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
0957 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
0958
0959 #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
0960 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
0961
0962 #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
0963 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
0964
0965 #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
0966 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
0967
0968 #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
0969 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
0970
0971 #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
0972 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
0973
0974 #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
0975 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
0976
0977 #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
0978 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
0979
0980 #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
0981 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
0982
0983 #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
0984 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
0985
0986 #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
0987 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
0988
0989 #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
0990 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
0991
0992 #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
0993 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
0994
0995 #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
0996 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
0997
0998 /* DWT CPI Count Register Definitions */
0999 #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
1000 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
1001
1002 /* DWT Exception Overhead Count Register Definitions */
1003 #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
1004 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
1005
1006 /* DWT Sleep Count Register Definitions */
1007 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
1008 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1009
1010 /* DWT LSU Count Register Definitions */
1011 #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
1012 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
1013
1014 /* DWT Folded-instruction Count Register Definitions */
1015 #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
1016 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
1017
1018 /* DWT Comparator Mask Register Definitions */
1019 #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
1020 #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
1021
1022 /* DWT Comparator Function Register Definitions */
1023 #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
1024 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
1025
1026 #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
1027 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
1028
1029 #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
1030 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
1031
1032 #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
1033 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
1034
1035 #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
1036 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
1037
1038 #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
1039 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
1040
1041 #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
1042 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
1043
1044 #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
1045 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
1046
1047 #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
1048 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
1049
1050 /*@}*/ /* end of group CMSIS_DWT */
1051
1052
1053 /**
1054   \ingroup  CMSIS_core_register
1055   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
1056   \brief    Type definitions for the Trace Port Interface (TPI)
1057   @{
1058  */
1059
1060 /**
1061   \brief  Structure type to access the Trace Port Interface Register (TPI).
1062  */
1063 typedef struct
1064 {
1065   __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
1066   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
1067         uint32_t RESERVED0[2U];
1068   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
1069         uint32_t RESERVED1[55U];
1070   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
1071         uint32_t RESERVED2[131U];
1072   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
1073   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
1074   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
1075         uint32_t RESERVED3[759U];
1076   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
1077   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
1078   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
1079         uint32_t RESERVED4[1U];
1080   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
1081   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
1082   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
1083         uint32_t RESERVED5[39U];
1084   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
1085   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
1086         uint32_t RESERVED7[8U];
1087   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
1088   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
1089 } TPI_Type;
1090
1091 /* TPI Asynchronous Clock Prescaler Register Definitions */
1092 #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
1093 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
1094
1095 /* TPI Selected Pin Protocol Register Definitions */
1096 #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
1097 #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
1098
1099 /* TPI Formatter and Flush Status Register Definitions */
1100 #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
1101 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
1102
1103 #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
1104 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
1105
1106 #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
1107 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
1108
1109 #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
1110 #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
1111
1112 /* TPI Formatter and Flush Control Register Definitions */
1113 #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
1114 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
1115
1116 #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
1117 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
1118
1119 /* TPI TRIGGER Register Definitions */
1120 #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
1121 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
1122
1123 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1124 #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
1125 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
1126
1127 #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
1128 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
1129
1130 #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
1131 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
1132
1133 #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
1134 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
1135
1136 #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
1137 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
1138
1139 #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
1140 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
1141
1142 #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
1143 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
1144
1145 /* TPI ITATBCTR2 Register Definitions */
1146 #define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
1147 #define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
1148
1149 #define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
1150 #define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
1151
1152 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1153 #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
1154 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
1155
1156 #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
1157 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
1158
1159 #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
1160 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
1161
1162 #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
1163 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
1164
1165 #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
1166 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
1167
1168 #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
1169 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
1170
1171 #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
1172 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
1173
1174 /* TPI ITATBCTR0 Register Definitions */
1175 #define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
1176 #define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
1177
1178 #define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
1179 #define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
1180
1181 /* TPI Integration Mode Control Register Definitions */
1182 #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
1183 #define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
1184
1185 /* TPI DEVID Register Definitions */
1186 #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
1187 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
1188
1189 #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
1190 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
1191
1192 #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
1193 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
1194
1195 #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
1196 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
1197
1198 #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
1199 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
1200
1201 #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
1202 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
1203
1204 /* TPI DEVTYPE Register Definitions */
1205 #define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
1206 #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
1207
1208 #define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
1209 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
1210
1211 /*@}*/ /* end of group CMSIS_TPI */
1212
1213
1214 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1215 /**
1216   \ingroup  CMSIS_core_register
1217   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
1218   \brief    Type definitions for the Memory Protection Unit (MPU)
1219   @{
1220  */
1221
1222 /**
1223   \brief  Structure type to access the Memory Protection Unit (MPU).
1224  */
1225 typedef struct
1226 {
1227   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
1228   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
1229   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
1230   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
1231   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
1232   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
1233   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
1234   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
1235   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
1236   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
1237   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
1238 } MPU_Type;
1239
1240 #define MPU_TYPE_RALIASES                  4U
1241
1242 /* MPU Type Register Definitions */
1243 #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
1244 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
1245
1246 #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
1247 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
1248
1249 #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
1250 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
1251
1252 /* MPU Control Register Definitions */
1253 #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
1254 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
1255
1256 #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
1257 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
1258
1259 #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
1260 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
1261
1262 /* MPU Region Number Register Definitions */
1263 #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
1264 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
1265
1266 /* MPU Region Base Address Register Definitions */
1267 #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
1268 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
1269
1270 #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
1271 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
1272
1273 #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
1274 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
1275
1276 /* MPU Region Attribute and Size Register Definitions */
1277 #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
1278 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
1279
1280 #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
1281 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
1282
1283 #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
1284 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
1285
1286 #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
1287 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
1288
1289 #define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
1290 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
1291
1292 #define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
1293 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
1294
1295 #define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
1296 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
1297
1298 #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
1299 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
1300
1301 #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
1302 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
1303
1304 #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
1305 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
1306
1307 /*@} end of group CMSIS_MPU */
1308 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1309
1310
1311 /**
1312   \ingroup  CMSIS_core_register
1313   \defgroup CMSIS_FPU     Floating Point Unit (FPU)
1314   \brief    Type definitions for the Floating Point Unit (FPU)
1315   @{
1316  */
1317
1318 /**
1319   \brief  Structure type to access the Floating Point Unit (FPU).
1320  */
1321 typedef struct
1322 {
1323         uint32_t RESERVED0[1U];
1324   __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
1325   __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
1326   __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
1327   __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
1328   __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
1329   __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
1330 } FPU_Type;
1331
1332 /* Floating-Point Context Control Register Definitions */
1333 #define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
1334 #define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
1335
1336 #define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
1337 #define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
1338
1339 #define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
1340 #define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
1341
1342 #define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
1343 #define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
1344
1345 #define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
1346 #define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
1347
1348 #define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
1349 #define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
1350
1351 #define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
1352 #define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
1353
1354 #define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
1355 #define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
1356
1357 #define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
1358 #define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
1359
1360 /* Floating-Point Context Address Register Definitions */
1361 #define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
1362 #define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
1363
1364 /* Floating-Point Default Status Control Register Definitions */
1365 #define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
1366 #define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
1367
1368 #define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
1369 #define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
1370
1371 #define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
1372 #define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
1373
1374 #define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
1375 #define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
1376
1377 /* Media and FP Feature Register 0 Definitions */
1378 #define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
1379 #define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
1380
1381 #define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
1382 #define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
1383
1384 #define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
1385 #define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
1386
1387 #define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
1388 #define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
1389
1390 #define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
1391 #define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
1392
1393 #define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
1394 #define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
1395
1396 #define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
1397 #define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
1398
1399 #define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
1400 #define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
1401
1402 /* Media and FP Feature Register 1 Definitions */
1403 #define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
1404 #define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
1405
1406 #define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
1407 #define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
1408
1409 #define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
1410 #define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
1411
1412 #define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
1413 #define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
1414
1415 /* Media and FP Feature Register 2 Definitions */
1416
1417 #define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */
1418 #define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */
1419
1420 /*@} end of group CMSIS_FPU */
1421
1422
1423 /**
1424   \ingroup  CMSIS_core_register
1425   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
1426   \brief    Type definitions for the Core Debug Registers
1427   @{
1428  */
1429
1430 /**
1431   \brief  Structure type to access the Core Debug Register (CoreDebug).
1432  */
1433 typedef struct
1434 {
1435   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
1436   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
1437   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
1438   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
1439 } CoreDebug_Type;
1440
1441 /* Debug Halting Control and Status Register Definitions */
1442 #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
1443 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
1444
1445 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
1446 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1447
1448 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1449 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1450
1451 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
1452 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1453
1454 #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
1455 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
1456
1457 #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
1458 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
1459
1460 #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
1461 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
1462
1463 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1464 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1465
1466 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
1467 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1468
1469 #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
1470 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
1471
1472 #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
1473 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
1474
1475 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1476 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1477
1478 /* Debug Core Register Selector Register Definitions */
1479 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
1480 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
1481
1482 #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
1483 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
1484
1485 /* Debug Exception and Monitor Control Register Definitions */
1486 #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
1487 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
1488
1489 #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
1490 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
1491
1492 #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
1493 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
1494
1495 #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
1496 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
1497
1498 #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
1499 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
1500
1501 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
1502 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1503
1504 #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
1505 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
1506
1507 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
1508 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1509
1510 #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
1511 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
1512
1513 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
1514 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1515
1516 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1517 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1518
1519 #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
1520 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
1521
1522 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
1523 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1524
1525 /*@} end of group CMSIS_CoreDebug */
1526
1527
1528 /**
1529   \ingroup    CMSIS_core_register
1530   \defgroup   CMSIS_core_bitfield     Core register bit field macros
1531   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1532   @{
1533  */
1534
1535 /**
1536   \brief   Mask and shift a bit field value for use in a register bit range.
1537   \param[in] field  Name of the register bit field.
1538   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
1539   \return           Masked and shifted value.
1540 */
1541 #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1542
1543 /**
1544   \brief     Mask and shift a register value to extract a bit filed value.
1545   \param[in] field  Name of the register bit field.
1546   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
1547   \return           Masked and shifted bit field value.
1548 */
1549 #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1550
1551 /*@} end of group CMSIS_core_bitfield */
1552
1553
1554 /**
1555   \ingroup    CMSIS_core_register
1556   \defgroup   CMSIS_core_base     Core Definitions
1557   \brief      Definitions for base addresses, unions, and structures.
1558   @{
1559  */
1560
1561 /* Memory mapping of Core Hardware */
1562 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
1563 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
1564 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
1565 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
1566 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
1567 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
1568 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
1569 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
1570
1571 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
1572 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
1573 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
1574 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
1575 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
1576 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
1577 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
1578 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
1579
1580 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1581   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
1582   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
1583 #endif
1584
1585 #define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
1586 #define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
1587
1588 /*@} */
1589
1590
1591 /**
1592   \ingroup    CMSIS_core_register
1593   \defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases
1594   \brief      Register alias definitions for backwards compatibility.
1595   @{
1596  */
1597
1598 /* Capitalize ITM_TCR Register Definitions */
1599
1600 /* ITM Trace Control Register Definitions */
1601 #define ITM_TCR_TraceBusID_Pos           (ITM_TCR_TRACEBUSID_Pos)     /*!< \deprecated ITM_TCR_TraceBusID_Pos */
1602 #define ITM_TCR_TraceBusID_Msk           (ITM_TCR_TRACEBUSID_Msk)     /*!< \deprecated ITM_TCR_TraceBusID_Msk */
1603
1604 #define ITM_TCR_TSPrescale_Pos           (ITM_TCR_TSPRESCALE_Pos)     /*!< \deprecated ITM_TCR_TSPrescale_Pos */
1605 #define ITM_TCR_TSPrescale_Msk           (ITM_TCR_TSPRESCALE_Msk)     /*!< \deprecated ITM_TCR_TSPrescale_Msk */
1606
1607 /* ITM Lock Status Register Definitions */
1608 #define ITM_LSR_ByteAcc_Pos              (ITM_LSR_BYTEACC_Pos)        /*!< \deprecated ITM_LSR_ByteAcc_Pos */
1609 #define ITM_LSR_ByteAcc_Msk              (ITM_LSR_BYTEACC_Msk)        /*!< \deprecated ITM_LSR_ByteAcc_Msk */
1610
1611 #define ITM_LSR_Access_Pos               (ITM_LSR_ACCESS_Pos)         /*!< \deprecated ITM_LSR_Access_Pos */
1612 #define ITM_LSR_Access_Msk               (ITM_LSR_ACCESS_Msk)         /*!< \deprecated ITM_LSR_Access_Msk */
1613
1614 #define ITM_LSR_Present_Pos              (ITM_LSR_PRESENT_Pos)        /*!< \deprecated ITM_LSR_Present_Pos */
1615 #define ITM_LSR_Present_Msk              (ITM_LSR_PRESENT_Msk)        /*!< \deprecated ITM_LSR_Present_Msk */
1616
1617 /*@} */
1618
1619
1620
1621 /*******************************************************************************
1622  *                Hardware Abstraction Layer
1623   Core Function Interface contains:
1624   - Core NVIC Functions
1625   - Core SysTick Functions
1626   - Core Debug Functions
1627   - Core Register Access Functions
1628  ******************************************************************************/
1629 /**
1630   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1631 */
1632
1633
1634
1635 /* ##########################   NVIC functions  #################################### */
1636 /**
1637   \ingroup  CMSIS_Core_FunctionInterface
1638   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1639   \brief    Functions that manage interrupts and exceptions via the NVIC.
1640   @{
1641  */
1642
1643 #ifdef CMSIS_NVIC_VIRTUAL
1644   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1645     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1646   #endif
1647   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1648 #else
1649   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
1650   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
1651   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
1652   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
1653   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
1654   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
1655   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
1656   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
1657   #define NVIC_GetActive              __NVIC_GetActive
1658   #define NVIC_SetPriority            __NVIC_SetPriority
1659   #define NVIC_GetPriority            __NVIC_GetPriority
1660   #define NVIC_SystemReset            __NVIC_SystemReset
1661 #endif /* CMSIS_NVIC_VIRTUAL */
1662
1663 #ifdef CMSIS_VECTAB_VIRTUAL
1664   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1665     #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1666   #endif
1667   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1668 #else
1669   #define NVIC_SetVector              __NVIC_SetVector
1670   #define NVIC_GetVector              __NVIC_GetVector
1671 #endif  /* (CMSIS_VECTAB_VIRTUAL) */
1672
1673 #define NVIC_USER_IRQ_OFFSET          16
1674
1675
1676 /* The following EXC_RETURN values are saved the LR on exception entry */
1677 #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
1678 #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
1679 #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
1680 #define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
1681 #define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
1682 #define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
1683
1684
1685 /**
1686   \brief   Set Priority Grouping
1687   \details Sets the priority grouping field using the required unlock sequence.
1688            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1689            Only values from 0..7 are used.
1690            In case of a conflict between priority grouping and available
1691            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1692   \param [in]      PriorityGroup  Priority grouping field.
1693  */
1694 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1695 {
1696   uint32_t reg_value;
1697   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
1698
1699   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
1700   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
1701   reg_value  =  (reg_value                                   |
1702                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1703                 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
1704   SCB->AIRCR =  reg_value;
1705 }
1706
1707
1708 /**
1709   \brief   Get Priority Grouping
1710   \details Reads the priority grouping field from the NVIC Interrupt Controller.
1711   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1712  */
1713 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1714 {
1715   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1716 }
1717
1718
1719 /**
1720   \brief   Enable Interrupt
1721   \details Enables a device specific interrupt in the NVIC interrupt controller.
1722   \param [in]      IRQn  Device specific interrupt number.
1723   \note    IRQn must not be negative.
1724  */
1725 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1726 {
1727   if ((int32_t)(IRQn) >= 0)
1728   {
1729     __COMPILER_BARRIER();
1730     NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1731     __COMPILER_BARRIER();
1732   }
1733 }
1734
1735
1736 /**
1737   \brief   Get Interrupt Enable status
1738   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1739   \param [in]      IRQn  Device specific interrupt number.
1740   \return             0  Interrupt is not enabled.
1741   \return             1  Interrupt is enabled.
1742   \note    IRQn must not be negative.
1743  */
1744 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1745 {
1746   if ((int32_t)(IRQn) >= 0)
1747   {
1748     return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1749   }
1750   else
1751   {
1752     return(0U);
1753   }
1754 }
1755
1756
1757 /**
1758   \brief   Disable Interrupt
1759   \details Disables a device specific interrupt in the NVIC interrupt controller.
1760   \param [in]      IRQn  Device specific interrupt number.
1761   \note    IRQn must not be negative.
1762  */
1763 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1764 {
1765   if ((int32_t)(IRQn) >= 0)
1766   {
1767     NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1768     __DSB();
1769     __ISB();
1770   }
1771 }
1772
1773
1774 /**
1775   \brief   Get Pending Interrupt
1776   \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1777   \param [in]      IRQn  Device specific interrupt number.
1778   \return             0  Interrupt status is not pending.
1779   \return             1  Interrupt status is pending.
1780   \note    IRQn must not be negative.
1781  */
1782 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1783 {
1784   if ((int32_t)(IRQn) >= 0)
1785   {
1786     return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1787   }
1788   else
1789   {
1790     return(0U);
1791   }
1792 }
1793
1794
1795 /**
1796   \brief   Set Pending Interrupt
1797   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1798   \param [in]      IRQn  Device specific interrupt number.
1799   \note    IRQn must not be negative.
1800  */
1801 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1802 {
1803   if ((int32_t)(IRQn) >= 0)
1804   {
1805     NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1806   }
1807 }
1808
1809
1810 /**
1811   \brief   Clear Pending Interrupt
1812   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1813   \param [in]      IRQn  Device specific interrupt number.
1814   \note    IRQn must not be negative.
1815  */
1816 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1817 {
1818   if ((int32_t)(IRQn) >= 0)
1819   {
1820     NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1821   }
1822 }
1823
1824
1825 /**
1826   \brief   Get Active Interrupt
1827   \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1828   \param [in]      IRQn  Device specific interrupt number.
1829   \return             0  Interrupt status is not active.
1830   \return             1  Interrupt status is active.
1831   \note    IRQn must not be negative.
1832  */
1833 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1834 {
1835   if ((int32_t)(IRQn) >= 0)
1836   {
1837     return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1838   }
1839   else
1840   {
1841     return(0U);
1842   }
1843 }
1844
1845
1846 /**
1847   \brief   Set Interrupt Priority
1848   \details Sets the priority of a device specific interrupt or a processor exception.
1849            The interrupt number can be positive to specify a device specific interrupt,
1850            or negative to specify a processor exception.
1851   \param [in]      IRQn  Interrupt number.
1852   \param [in]  priority  Priority to set.
1853   \note    The priority cannot be set for every processor exception.
1854  */
1855 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1856 {
1857   if ((int32_t)(IRQn) >= 0)
1858   {
1859     NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1860   }
1861   else
1862   {
1863     SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1864   }
1865 }
1866
1867
1868 /**
1869   \brief   Get Interrupt Priority
1870   \details Reads the priority of a device specific interrupt or a processor exception.
1871            The interrupt number can be positive to specify a device specific interrupt,
1872            or negative to specify a processor exception.
1873   \param [in]   IRQn  Interrupt number.
1874   \return             Interrupt Priority.
1875                       Value is aligned automatically to the implemented priority bits of the microcontroller.
1876  */
1877 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1878 {
1879
1880   if ((int32_t)(IRQn) >= 0)
1881   {
1882     return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
1883   }
1884   else
1885   {
1886     return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1887   }
1888 }
1889
1890
1891 /**
1892   \brief   Encode Priority
1893   \details Encodes the priority for an interrupt with the given priority group,
1894            preemptive priority value, and subpriority value.
1895            In case of a conflict between priority grouping and available
1896            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1897   \param [in]     PriorityGroup  Used priority group.
1898   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
1899   \param [in]       SubPriority  Subpriority value (starting from 0).
1900   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1901  */
1902 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1903 {
1904   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
1905   uint32_t PreemptPriorityBits;
1906   uint32_t SubPriorityBits;
1907
1908   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1909   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1910
1911   return (
1912            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1913            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
1914          );
1915 }
1916
1917
1918 /**
1919   \brief   Decode Priority
1920   \details Decodes an interrupt priority value with a given priority group to
1921            preemptive priority value and subpriority value.
1922            In case of a conflict between priority grouping and available
1923            priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1924   \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1925   \param [in]     PriorityGroup  Used priority group.
1926   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
1927   \param [out]     pSubPriority  Subpriority value (starting from 0).
1928  */
1929 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1930 {
1931   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
1932   uint32_t PreemptPriorityBits;
1933   uint32_t SubPriorityBits;
1934
1935   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1936   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1937
1938   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1939   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
1940 }
1941
1942
1943 /**
1944   \brief   Set Interrupt Vector
1945   \details Sets an interrupt vector in SRAM based interrupt vector table.
1946            The interrupt number can be positive to specify a device specific interrupt,
1947            or negative to specify a processor exception.
1948            VTOR must been relocated to SRAM before.
1949   \param [in]   IRQn      Interrupt number
1950   \param [in]   vector    Address of interrupt handler function
1951  */
1952 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1953 {
1954   uint32_t *vectors = (uint32_t *)SCB->VTOR;
1955   vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1956   /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
1957 }
1958
1959
1960 /**
1961   \brief   Get Interrupt Vector
1962   \details Reads an interrupt vector from interrupt vector table.
1963            The interrupt number can be positive to specify a device specific interrupt,
1964            or negative to specify a processor exception.
1965   \param [in]   IRQn      Interrupt number.
1966   \return                 Address of interrupt handler function
1967  */
1968 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1969 {
1970   uint32_t *vectors = (uint32_t *)SCB->VTOR;
1971   return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1972 }
1973
1974
1975 /**
1976   \brief   System Reset
1977   \details Initiates a system reset request to reset the MCU.
1978  */
1979 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1980 {
1981   __DSB();                                                          /* Ensure all outstanding memory accesses included
1982                                                                        buffered write are completed before reset */
1983   SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
1984                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1985                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
1986   __DSB();                                                          /* Ensure completion of memory access */
1987
1988   for(;;)                                                           /* wait until reset */
1989   {
1990     __NOP();
1991   }
1992 }
1993
1994 /*@} end of CMSIS_Core_NVICFunctions */
1995
1996
1997 /* ##########################  MPU functions  #################################### */
1998
1999 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2000
2001 #include "mpu_armv7.h"
2002
2003 #endif
2004
2005
2006 /* ##########################  FPU functions  #################################### */
2007 /**
2008   \ingroup  CMSIS_Core_FunctionInterface
2009   \defgroup CMSIS_Core_FpuFunctions FPU Functions
2010   \brief    Function that provides FPU type.
2011   @{
2012  */
2013
2014 /**
2015   \brief   get FPU type
2016   \details returns the FPU type
2017   \returns
2018    - \b  0: No FPU
2019    - \b  1: Single precision FPU
2020    - \b  2: Double + Single precision FPU
2021  */
2022 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2023 {
2024   uint32_t mvfr0;
2025
2026   mvfr0 = FPU->MVFR0;
2027   if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2028   {
2029     return 1U;           /* Single precision FPU */
2030   }
2031   else
2032   {
2033     return 0U;           /* No FPU */
2034   }
2035 }
2036
2037
2038 /*@} end of CMSIS_Core_FpuFunctions */
2039
2040
2041
2042 /* ##################################    SysTick function  ############################################ */
2043 /**
2044   \ingroup  CMSIS_Core_FunctionInterface
2045   \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2046   \brief    Functions that configure the System.
2047   @{
2048  */
2049
2050 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2051
2052 /**
2053   \brief   System Tick Configuration
2054   \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2055            Counter is in free running mode to generate periodic interrupts.
2056   \param [in]  ticks  Number of ticks between two interrupts.
2057   \return          0  Function succeeded.
2058   \return          1  Function failed.
2059   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2060            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2061            must contain a vendor-specific implementation of this function.
2062  */
2063 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2064 {
2065   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2066   {
2067     return (1UL);                                                   /* Reload value impossible */
2068   }
2069
2070   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
2071   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2072   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
2073   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
2074                    SysTick_CTRL_TICKINT_Msk   |
2075                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
2076   return (0UL);                                                     /* Function successful */
2077 }
2078
2079 #endif
2080
2081 /*@} end of CMSIS_Core_SysTickFunctions */
2082
2083
2084
2085 /* ##################################### Debug In/Output function ########################################### */
2086 /**
2087   \ingroup  CMSIS_Core_FunctionInterface
2088   \defgroup CMSIS_core_DebugFunctions ITM Functions
2089   \brief    Functions that access the ITM debug interface.
2090   @{
2091  */
2092
2093 extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
2094 #define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2095
2096
2097 /**
2098   \brief   ITM Send Character
2099   \details Transmits a character via the ITM channel 0, and
2100            \li Just returns when no debugger is connected that has booked the output.
2101            \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2102   \param [in]     ch  Character to transmit.
2103   \returns            Character to transmit.
2104  */
2105 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2106 {
2107   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
2108       ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
2109   {
2110     while (ITM->PORT[0U].u32 == 0UL)
2111     {
2112       __NOP();
2113     }
2114     ITM->PORT[0U].u8 = (uint8_t)ch;
2115   }
2116   return (ch);
2117 }
2118
2119
2120 /**
2121   \brief   ITM Receive Character
2122   \details Inputs a character via the external variable \ref ITM_RxBuffer.
2123   \return             Received character.
2124   \return         -1  No character pending.
2125  */
2126 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2127 {
2128   int32_t ch = -1;                           /* no character available */
2129
2130   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2131   {
2132     ch = ITM_RxBuffer;
2133     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
2134   }
2135
2136   return (ch);
2137 }
2138
2139
2140 /**
2141   \brief   ITM Check Character
2142   \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2143   \return          0  No character available.
2144   \return          1  Character available.
2145  */
2146 __STATIC_INLINE int32_t ITM_CheckChar (void)
2147 {
2148
2149   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2150   {
2151     return (0);                              /* no character available */
2152   }
2153   else
2154   {
2155     return (1);                              /*    character available */
2156   }
2157 }
2158
2159 /*@} end of CMSIS_core_DebugFunctions */
2160
2161
2162
2163
2164 #ifdef __cplusplus
2165 }
2166 #endif
2167
2168 #endif /* __CORE_CM4_H_DEPENDANT */
2169
2170 #endif /* __CMSIS_GENERIC */