include/bsp/lpc-timer.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup lpc_timer
0007  *
0008  * @brief Timer API.
0009  */
0010
0011 /*
0012  * Copyright (c) 2009 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_ARM_SHARED_LPC_TIMER_H
0037 #define LIBBSP_ARM_SHARED_LPC_TIMER_H
0038
0039 #include <stdint.h>
0040
0041 #ifdef __cplusplus
0042 extern "C" {
0043 #endif
0044
0045 /**
0046  * @defgroup lpc_timer Timer Support
0047  *
0048  * @ingroup RTEMSBSPsARMLPC24XX
0049  * @ingroup RTEMSBSPsARMLPC32XX
0050  *
0051  * @brief Timer support.
0052  *
0053  * @{
0054  */
0055
0056 /**
0057  * @name Interrupt Register Defines
0058  *
0059  * @{
0060  */
0061
0062 #define LPC_TIMER_IR_MR0 0x1U
0063 #define LPC_TIMER_IR_MR1 0x2U
0064 #define LPC_TIMER_IR_MR2 0x4U
0065 #define LPC_TIMER_IR_MR3 0x8U
0066 #define LPC_TIMER_IR_CR0 0x10U
0067 #define LPC_TIMER_IR_CR1 0x20U
0068 #define LPC_TIMER_IR_CR2 0x40U
0069 #define LPC_TIMER_IR_CR3 0x80U
0070 #define LPC_TIMER_IR_ALL 0xffU
0071
0072 /** @} */
0073
0074 /**
0075  * @name Timer Control Register Defines
0076  *
0077  * @{
0078  */
0079
0080 #define LPC_TIMER_TCR_EN 0x1U
0081 #define LPC_TIMER_TCR_RST 0x2U
0082
0083 /** @} */
0084
0085 /**
0086  * @name Match Control Register Defines
0087  *
0088  * @{
0089  */
0090
0091 #define LPC_TIMER_MCR_MR0_INTR 0x1U
0092 #define LPC_TIMER_MCR_MR0_RST 0x2U
0093 #define LPC_TIMER_MCR_MR0_STOP 0x4U
0094 #define LPC_TIMER_MCR_MR1_INTR 0x8U
0095 #define LPC_TIMER_MCR_MR1_RST 0x10U
0096 #define LPC_TIMER_MCR_MR1_STOP 0x20U
0097 #define LPC_TIMER_MCR_MR2_INTR 0x40U
0098 #define LPC_TIMER_MCR_MR2_RST 0x80U
0099 #define LPC_TIMER_MCR_MR2_STOP 0x100U
0100 #define LPC_TIMER_MCR_MR3_INTR 0x200U
0101 #define LPC_TIMER_MCR_MR3_RST 0x400U
0102 #define LPC_TIMER_MCR_MR3_STOP 0x800U
0103
0104 /** @} */
0105
0106 /**
0107  * @name Capture Control Register Defines
0108  *
0109  * @{
0110  */
0111
0112 #define LPC_TIMER_CCR_CAP0_RE 0x1U
0113 #define LPC_TIMER_CCR_CAP0_FE 0x2U
0114 #define LPC_TIMER_CCR_CAP0_INTR 0x4U
0115 #define LPC_TIMER_CCR_CAP1_RE 0x8U
0116 #define LPC_TIMER_CCR_CAP1_FE 0x10U
0117 #define LPC_TIMER_CCR_CAP1_INTR 0x20U
0118 #define LPC_TIMER_CCR_CAP2_RE 0x40U
0119 #define LPC_TIMER_CCR_CAP2_FE 0x80U
0120 #define LPC_TIMER_CCR_CAP2_INTR 0x100U
0121 #define LPC_TIMER_CCR_CAP3_RE 0x200U
0122 #define LPC_TIMER_CCR_CAP3_FE 0x400U
0123 #define LPC_TIMER_CCR_CAP3_INTR 0x800U
0124
0125 /** @} */
0126
0127 /**
0128  * @name External Match Register Defines
0129  *
0130  * @{
0131  */
0132
0133 #define LPC_TIMER_EMR_EM0_RE 0x1U
0134 #define LPC_TIMER_EMR_EM1_FE 0x2U
0135 #define LPC_TIMER_EMR_EM2_INTR 0x4U
0136 #define LPC_TIMER_EMR_EM3_RE 0x8U
0137 #define LPC_TIMER_EMR_EMC0_FE 0x10U
0138 #define LPC_TIMER_EMR_EMC1_INTR 0x20U
0139 #define LPC_TIMER_EMR_EMC2_RE 0x40U
0140 #define LPC_TIMER_EMR_EMC3_FE 0x80U
0141
0142 /** @} */
0143
0144 /**
0145  * @brief Timer control block.
0146  */
0147 typedef struct {
0148   uint32_t ir;
0149   uint32_t tcr;
0150   uint32_t tc;
0151   uint32_t pr;
0152   uint32_t pc;
0153   uint32_t mcr;
0154   uint32_t mr0;
0155   uint32_t mr1;
0156   uint32_t mr2;
0157   uint32_t mr3;
0158   uint32_t ccr;
0159   uint32_t cr0;
0160   uint32_t cr1;
0161   uint32_t cr2;
0162   uint32_t cr3;
0163   uint32_t emr;
0164   uint32_t ctcr;
0165 } lpc_timer;
0166
0167 /** @} */
0168
0169 #ifdef __cplusplus
0170 }
0171 #endif /* __cplusplus */
0172
0173 #endif /* LIBBSP_ARM_SHARED_LPC_TIMER_H */