include/bsp/lpc-lcd.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup lpc_lcd
0007  *
0008  * @brief LCD support API.
0009  */
0010
0011 /*
0012  * Copyright (c) 2011 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_ARM_SHARED_LPC_LCD_H
0037 #define LIBBSP_ARM_SHARED_LPC_LCD_H
0038
0039 #include <bsp/utility.h>
0040
0041 #ifdef __cplusplus
0042 extern "C" {
0043 #endif
0044
0045 /**
0046  * @defgroup lpc_lcd LCD Support
0047  *
0048  * @ingroup RTEMSBSPsARMLPC24XX
0049  * @ingroup RTEMSBSPsARMLPC32XX
0050  *
0051  * @brief LCD support.
0052  *
0053  * @{
0054  */
0055
0056 typedef struct {
0057   uint8_t img [1024];
0058   uint32_t ctrl;
0059   uint32_t cfg;
0060   uint32_t pal0;
0061   uint32_t pal1;
0062   uint32_t xy;
0063   uint32_t clip;
0064   uint32_t intmsk;
0065   uint32_t intclr;
0066   uint32_t intraw;
0067   uint32_t intstat;
0068 } lpc_cursor;
0069
0070 typedef struct {
0071   uint32_t timh;
0072   uint32_t timv;
0073   uint32_t pol;
0074   uint32_t le;
0075   uint32_t upbase;
0076   uint32_t lpbase;
0077   uint32_t ctrl;
0078   uint32_t intmsk;
0079   uint32_t intraw;
0080   uint32_t intstat;
0081   uint32_t intclr;
0082   uint32_t upcurr;
0083   uint32_t lpcurr;
0084   uint8_t reserved_0 [0x200 - 0x034];
0085   uint16_t pal [256];
0086   uint8_t reserved_1 [0x800 - 0x400];
0087   lpc_cursor crsr;
0088 } lpc_lcd;
0089
0090 /**
0091  * @name LCD Configuration Register
0092  *
0093  * @{
0094  */
0095
0096 #define LCD_CFG_CLKDIV(val) BSP_FLD32(val, 0, 4)
0097 #define LCD_CFG_HCLK_ENABLE BSP_BIT32(5)
0098 #define LCD_CFG_MODE_SELECT(val) BSP_FLD32(val, 6, 7)
0099 #define LCD_CFG_DISPLAY_TYPE BSP_BIT32(8)
0100
0101 /** @} */
0102
0103 /**
0104  * @name LCD Horizontal Timing Register
0105  *
0106  * @{
0107  */
0108
0109 #define LCD_TIMH_PPL(val) BSP_FLD32(val, 2, 7)
0110 #define LCD_TIMH_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7)
0111 #define LCD_TIMH_HSW(val) BSP_FLD32(val, 8, 15)
0112 #define LCD_TIMH_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15)
0113 #define LCD_TIMH_HFP(val) BSP_FLD32(val, 16, 23)
0114 #define LCD_TIMH_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
0115 #define LCD_TIMH_HBP(val) BSP_FLD32(val, 24, 31)
0116 #define LCD_TIMH_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
0117
0118 /** @} */
0119
0120 /**
0121  * @name LCD Vertical Timing Register
0122  *
0123  * @{
0124  */
0125
0126 #define LCD_TIMV_LPP(val) BSP_FLD32(val, 0, 9)
0127 #define LCD_TIMV_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9)
0128 #define LCD_TIMV_VSW(val) BSP_FLD32(val, 10, 15)
0129 #define LCD_TIMV_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15)
0130 #define LCD_TIMV_VFP(val) BSP_FLD32(val, 16, 23)
0131 #define LCD_TIMV_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
0132 #define LCD_TIMV_VBP(val) BSP_FLD32(val, 24, 31)
0133 #define LCD_TIMV_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
0134
0135 /** @} */
0136
0137 /**
0138  * @name LCD Clock and Signal Polarity Register
0139  *
0140  * @{
0141  */
0142
0143 #define LCD_POL_PCD_LO(val) BSP_FLD32(val, 0, 4)
0144 #define LCD_POL_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4)
0145 #define LCD_POL_CLKSEL BSP_BIT32(5)
0146 #define LCD_POL_ACB(val) BSP_FLD32(val, 6, 10)
0147 #define LCD_POL_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10)
0148 #define LCD_POL_IVS BSP_BIT32(11)
0149 #define LCD_POL_IHS BSP_BIT32(12)
0150 #define LCD_POL_IPC BSP_BIT32(13)
0151 #define LCD_POL_IOE BSP_BIT32(14)
0152 #define LCD_POL_CPL(val) BSP_FLD32(val, 16, 25)
0153 #define LCD_POL_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25)
0154 #define LCD_POL_BCD BSP_BIT32(26)
0155 #define LCD_POL_PCD_HI(val) BSP_FLD32(val, 27, 31)
0156 #define LCD_POL_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31)
0157
0158 /** @} */
0159
0160 /**
0161  * @name LCD Line End Control Register
0162  *
0163  * @{
0164  */
0165
0166 #define LCD_LE_LED(val) BSP_FLD32(val, 0, 6)
0167 #define LCD_LE_LEE BSP_BIT32(16)
0168
0169 /** @} */
0170
0171 /**
0172  * @name LCD Control Register
0173  *
0174  * @{
0175  */
0176
0177 #define LCD_CTRL_LCDEN BSP_BIT32(0)
0178 #define LCD_CTRL_LCDBPP(val) BSP_FLD32(val, 1, 3)
0179 #define LCD_CTRL_LCDBPP_GET(reg) BSP_FLD32GET(reg, 1, 3)
0180 #define LCD_CTRL_LCDBW BSP_BIT32(4)
0181 #define LCD_CTRL_LCDTFT BSP_BIT32(5)
0182 #define LCD_CTRL_LCDMONO8 BSP_BIT32(6)
0183 #define LCD_CTRL_LCDDUAL BSP_BIT32(7)
0184 #define LCD_CTRL_BGR BSP_BIT32(8)
0185 #define LCD_CTRL_BEBO BSP_BIT32(9)
0186 #define LCD_CTRL_BEPO BSP_BIT32(10)
0187 #define LCD_CTRL_LCDPWR BSP_BIT32(11)
0188 #define LCD_CTRL_LCDVCOMP(val) BSP_FLD32(val, 12, 13)
0189 #define LCD_CTRL_LCDVCOMP_GET(reg) BSP_FLD32GET(reg, 12, 13)
0190 #define LCD_CTRL_WATERMARK BSP_BIT32(16)
0191
0192 /** @} */
0193
0194 /**
0195  * @name LCD Interrupt Registers
0196  *
0197  * @{
0198  */
0199
0200 #define LCD_INT_FUF BSP_BIT32(1)
0201 #define LCD_INT_LNBU BSP_BIT32(2)
0202 #define LCD_INT_VCOMP BSP_BIT32(3)
0203 #define LCD_INT_BER BSP_BIT32(4)
0204
0205 /** @} */
0206
0207 /**
0208  * @name LCD Color Palette Register
0209  *
0210  * @{
0211  */
0212
0213 #define LCD_PAL_R(val) BSP_FLD16(val, 0, 4)
0214 #define LCD_PAL_G(val) BSP_FLD16(val, 5, 9)
0215 #define LCD_PAL_B(val) BSP_FLD16(val, 10, 14)
0216 #define LCD_PAL_I BSP_BIT16(15)
0217
0218 /** @} */
0219
0220 /** @} */
0221
0222 #ifdef __cplusplus
0223 }
0224 #endif /* __cplusplus */
0225
0226 #endif /* LIBBSP_ARM_SHARED_LPC_LCD_H */