include/bsp/lpc-emc.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup lpc_emc
0007  *
0008  * @brief EMC support API.
0009  */
0010
0011 /*
0012  * Copyright (C) 2010, 2011 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_ARM_SHARED_LPC_EMC_H
0037 #define LIBBSP_ARM_SHARED_LPC_EMC_H
0038
0039 #include <bsp/utility.h>
0040
0041 #ifdef __cplusplus
0042 extern "C" {
0043 #endif /* __cplusplus */
0044
0045 /**
0046  * @defgroup lpc_emc EMC Support
0047  *
0048  * @ingroup RTEMSBSPsARMLPC24XX
0049  * @ingroup RTEMSBSPsARMLPC32XX
0050  *
0051  * @brief EMC Support
0052  *
0053  * @{
0054  */
0055
0056 /**
0057  * @name EMC Control Register (EMCControl)
0058  *
0059  * @{
0060  */
0061
0062 #define EMC_CTRL_E BSP_BIT32(0)
0063 #define EMC_CTRL_M BSP_BIT32(0)
0064 #define EMC_CTRL_L BSP_BIT32(2)
0065
0066 /** @} */
0067
0068 /**
0069  * @name EMC Dynamic Memory Control Register (EMCDynamicControl)
0070  *
0071  * @{
0072  */
0073
0074 #define EMC_DYN_CTRL_CE BSP_BIT32(0)
0075 #define EMC_DYN_CTRL_CS BSP_BIT32(1)
0076 #define EMC_DYN_CTRL_SR BSP_BIT32(2)
0077 #define EMC_DYN_CTRL_SRMCC BSP_BIT32(3)
0078 #define EMC_DYN_CTRL_IMCC BSP_BIT32(4)
0079 #define EMC_DYN_CTRL_MCC BSP_BIT32(5)
0080 #define EMC_DYN_CTRL_I_MASK BSP_MSK32(7, 8)
0081 #define EMC_DYN_CTRL_I_NORMAL BSP_FLD32(0x0, 7, 8)
0082 #define EMC_DYN_CTRL_I_MODE BSP_FLD32(0x1, 7, 8)
0083 #define EMC_DYN_CTRL_I_PALL BSP_FLD32(0x2, 7, 8)
0084 #define EMC_DYN_CTRL_I_NOP BSP_FLD32(0x3, 7, 8)
0085 #define EMC_DYN_CTRL_DP BSP_BIT32(13)
0086
0087 /** @} */
0088
0089 /**
0090  * @name EMC Dynamic Memory Read Configuration Register (EMCDynamicReadConfig)
0091  *
0092  * @{
0093  */
0094
0095 #define EMC_DYN_READ_CONFIG_SDR_STRAT(val) BSP_FLD32(val, 0, 1)
0096 #define EMC_DYN_READ_CONFIG_SDR_POL_POS BSP_BIT32(4)
0097 #define EMC_DYN_READ_CONFIG_DDR_STRAT(val) BSP_FLD32(val, 8, 9)
0098 #define EMC_DYN_READ_CONFIG_DDR_POL_POS BSP_BIT32(12)
0099
0100 /** @} */
0101
0102 /**
0103  * @name EMC Dynamic Memory Configuration N Register (EMCDynamicConfigN)
0104  *
0105  * @{
0106  */
0107
0108 #define EMC_DYN_CFG_MD_LPC24XX(val) BSP_FLD32(val, 3, 4)
0109 #define EMC_DYN_CFG_MD_LPC32XX(val) BSP_FLD32(val, 0, 2)
0110 #define EMC_DYN_CFG_AM(val) BSP_FLD32(val, 7, 14)
0111 #define EMC_DYN_CFG_B BSP_BIT32(19)
0112 #define EMC_DYN_CFG_P BSP_BIT32(20)
0113
0114 /** @} */
0115
0116 /**
0117  * @name EMC Dynamic Memory RAS and CAS Delay N Register (EMCDynamicRasCasN)
0118  *
0119  * @{
0120  */
0121
0122 #define EMC_DYN_RASCAS_RAS(val) BSP_FLD32(val, 0, 3)
0123 #define EMC_DYN_RASCAS_CAS(val, half) BSP_FLD32(((val) << 1) | (half), 7, 10)
0124
0125 /** @} */
0126
0127 #define EMC_DYN_CHIP_COUNT 4
0128
0129 #define EMC_STATIC_CHIP_COUNT 4
0130
0131 typedef struct {
0132   uint32_t config;
0133   uint32_t rascas;
0134   uint32_t reserved_0 [6];
0135 } lpc_emc_dynamic;
0136
0137 typedef struct {
0138   uint32_t config;
0139   uint32_t waitwen;
0140   uint32_t waitoen;
0141   uint32_t waitrd;
0142   uint32_t waitpage;
0143   uint32_t waitwr;
0144   uint32_t waitturn;
0145   uint32_t reserved_0 [1];
0146 } lpc_emc_static;
0147
0148 typedef struct {
0149   uint32_t control;
0150   uint32_t status;
0151   uint32_t config;
0152   uint32_t reserved_0 [5];
0153   uint32_t dynamiccontrol;
0154   uint32_t dynamicrefresh;
0155   uint32_t dynamicreadconfig;
0156   uint32_t reserved_1;
0157   uint32_t dynamictrp;
0158   uint32_t dynamictras;
0159   uint32_t dynamictsrex;
0160   uint32_t dynamictapr;
0161   uint32_t dynamictdal;
0162   uint32_t dynamictwr;
0163   uint32_t dynamictrc;
0164   uint32_t dynamictrfc;
0165   uint32_t dynamictxsr;
0166   uint32_t dynamictrrd;
0167   uint32_t dynamictmrd;
0168   uint32_t dynamictcdlr;
0169   uint32_t reserved_3 [8];
0170   uint32_t staticextendedwait;
0171   uint32_t reserved_4 [31];
0172   lpc_emc_dynamic dynamic [EMC_DYN_CHIP_COUNT];
0173   uint32_t reserved_5 [32];
0174   lpc_emc_static emcstatic [EMC_STATIC_CHIP_COUNT];
0175 } lpc_emc;
0176
0177 /** @} */
0178
0179 #ifdef __cplusplus
0180 }
0181 #endif /* __cplusplus */
0182
0183 #endif /* LIBBSP_ARM_SHARED_LPC_EMC_H */