include/bsp/lpc-dma.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup lpc_dma
0007  *
0008  * @brief DMA support API.
0009  */
0010
0011 /*
0012  * Copyright (C) 2010, 2012 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_ARM_SHARED_LPC_DMA_H
0037 #define LIBBSP_ARM_SHARED_LPC_DMA_H
0038
0039 #include <bspopts.h>
0040 #include <bsp/utility.h>
0041
0042 #ifdef __cplusplus
0043 extern "C" {
0044 #endif
0045
0046 /**
0047  * @defgroup lpc_dma DMA Support
0048  *
0049  * @ingroup RTEMSBSPsARMLPC24XX
0050  * @ingroup RTEMSBSPsARMLPC32XX
0051  *
0052  * @brief DMA support.
0053  *
0054  * @{
0055  */
0056
0057 /**
0058  * @brief DMA descriptor item.
0059  */
0060 typedef struct {
0061   uint32_t src;
0062   uint32_t dest;
0063   uint32_t lli;
0064   uint32_t ctrl;
0065 } lpc_dma_descriptor;
0066
0067 /**
0068  * @brief DMA channel block.
0069  */
0070 typedef struct {
0071   lpc_dma_descriptor desc;
0072   uint32_t cfg;
0073   uint32_t reserved [3];
0074 } lpc_dma_channel;
0075
0076 /**
0077  * @brief DMA control block.
0078  */
0079 typedef struct {
0080   uint32_t int_stat;
0081   uint32_t int_tc_stat;
0082   uint32_t int_tc_clear;
0083   uint32_t int_err_stat;
0084   uint32_t int_err_clear;
0085   uint32_t raw_tc_stat;
0086   uint32_t raw_err_stat;
0087   uint32_t enabled_channels;
0088   uint32_t soft_burst_req;
0089   uint32_t soft_single_req;
0090   uint32_t soft_last_burst_req;
0091   uint32_t soft_last_single_req;
0092   uint32_t cfg;
0093   uint32_t sync;
0094   uint32_t reserved [50];
0095   lpc_dma_channel channels [LPC_DMA_CHANNEL_COUNT];
0096 } lpc_dma;
0097
0098 /**
0099  * @name DMA Configuration Register
0100  *
0101  * @{
0102  */
0103
0104 #define DMA_CFG_E BSP_BIT32(0)
0105 #define DMA_CFG_M_0 BSP_BIT32(1)
0106 #define DMA_CFG_M_1 BSP_BIT32(2)
0107
0108 /** @} */
0109
0110 /**
0111  * @name DMA Channel Control Register
0112  *
0113  * @{
0114  */
0115
0116 #define DMA_CH_CTRL_TSZ(val) BSP_FLD32(val, 0, 11)
0117 #define DMA_CH_CTRL_TSZ_MAX DMA_CH_CTRL_TSZ(0xfff)
0118
0119 #define DMA_CH_CTRL_SB(val) BSP_FLD32(val, 12, 14)
0120 #define DMA_CH_CTRL_SB_1 DMA_CH_CTRL_SB(0)
0121 #define DMA_CH_CTRL_SB_4 DMA_CH_CTRL_SB(1)
0122 #define DMA_CH_CTRL_SB_8 DMA_CH_CTRL_SB(2)
0123 #define DMA_CH_CTRL_SB_16 DMA_CH_CTRL_SB(3)
0124 #define DMA_CH_CTRL_SB_32 DMA_CH_CTRL_SB(4)
0125 #define DMA_CH_CTRL_SB_64 DMA_CH_CTRL_SB(5)
0126 #define DMA_CH_CTRL_SB_128 DMA_CH_CTRL_SB(6)
0127 #define DMA_CH_CTRL_SB_256 DMA_CH_CTRL_SB(7)
0128
0129 #define DMA_CH_CTRL_DB(val) BSP_FLD32(val, 15, 17)
0130 #define DMA_CH_CTRL_DB_1 DMA_CH_CTRL_DB(0)
0131 #define DMA_CH_CTRL_DB_4 DMA_CH_CTRL_DB(1)
0132 #define DMA_CH_CTRL_DB_8 DMA_CH_CTRL_DB(2)
0133 #define DMA_CH_CTRL_DB_16 DMA_CH_CTRL_DB(3)
0134 #define DMA_CH_CTRL_DB_32 DMA_CH_CTRL_DB(4)
0135 #define DMA_CH_CTRL_DB_64 DMA_CH_CTRL_DB(5)
0136 #define DMA_CH_CTRL_DB_128 DMA_CH_CTRL_DB(6)
0137 #define DMA_CH_CTRL_DB_256 DMA_CH_CTRL_DB(7)
0138
0139 #define DMA_CH_CTRL_SW(val) BSP_FLD32(val, 18, 20)
0140 #define DMA_CH_CTRL_SW_8 DMA_CH_CTRL_SW(0)
0141 #define DMA_CH_CTRL_SW_16 DMA_CH_CTRL_SW(1)
0142 #define DMA_CH_CTRL_SW_32 DMA_CH_CTRL_SW(2)
0143
0144 #define DMA_CH_CTRL_DW(val) BSP_FLD32(val, 21, 23)
0145 #define DMA_CH_CTRL_DW_8 DMA_CH_CTRL_DW(0)
0146 #define DMA_CH_CTRL_DW_16 DMA_CH_CTRL_DW(1)
0147 #define DMA_CH_CTRL_DW_32 DMA_CH_CTRL_DW(2)
0148
0149 #define DMA_CH_CTRL_S BSP_BIT32(24)
0150 #define DMA_CH_CTRL_D BSP_BIT32(25)
0151 #define DMA_CH_CTRL_SI BSP_BIT32(26)
0152 #define DMA_CH_CTRL_DI BSP_BIT32(27)
0153 #define DMA_CH_CTRL_PROT(val) BSP_FLD32(val, 28, 30)
0154 #define DMA_CH_CTRL_I BSP_BIT32(31)
0155
0156 /** @} */
0157
0158 /**
0159  * @name DMA Channel Configuration Register
0160  *
0161  * @{
0162  */
0163
0164 #define DMA_CH_CFG_E BSP_BIT32(0)
0165 #define DMA_CH_CFG_SPER(val) BSP_FLD32(val, 1, 5)
0166 #define DMA_CH_CFG_DPER(val) BSP_FLD32(val, 6, 10)
0167
0168 #define DMA_CH_CFG_FLOW(val) BSP_FLD32(val, 11, 13)
0169 #define DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA DMA_CH_CFG_FLOW(0)
0170 #define DMA_CH_CFG_FLOW_MEM_TO_PER_DMA DMA_CH_CFG_FLOW(1)
0171 #define DMA_CH_CFG_FLOW_PER_TO_MEM_DMA DMA_CH_CFG_FLOW(2)
0172 #define DMA_CH_CFG_FLOW_PER_TO_PER_DMA DMA_CH_CFG_FLOW(3)
0173 #define DMA_CH_CFG_FLOW_PER_TO_PER_DEST DMA_CH_CFG_FLOW(4)
0174 #define DMA_CH_CFG_FLOW_MEM_TO_PER_PER DMA_CH_CFG_FLOW(5)
0175 #define DMA_CH_CFG_FLOW_PER_TO_MEM_PER DMA_CH_CFG_FLOW(6)
0176 #define DMA_CH_CFG_FLOW_PER_TO_PER_SRC DMA_CH_CFG_FLOW(7)
0177
0178 #define DMA_CH_CFG_IE BSP_BIT32(14)
0179 #define DMA_CH_CFG_ITC BSP_BIT32(15)
0180 #define DMA_CH_CFG_L BSP_BIT32(16)
0181 #define DMA_CH_CFG_A BSP_BIT32(17)
0182 #define DMA_CH_CFG_H BSP_BIT32(18)
0183
0184 /** @} */
0185
0186 /**
0187  * @name LPC24XX DMA Peripherals
0188  *
0189  * @{
0190  */
0191
0192 #define LPC24XX_DMA_PER_SSP_0_TX 0
0193 #define LPC24XX_DMA_PER_SSP_0_RX 1
0194 #define LPC24XX_DMA_PER_SSP_1_TX 2
0195 #define LPC24XX_DMA_PER_SSP_1_RX 3
0196 #define LPC24XX_DMA_PER_SD_MMC 4
0197 #define LPC24XX_DMA_PER_I2S_CH_0 5
0198 #define LPC24XX_DMA_PER_I2S_CH_1 6
0199
0200 /** @} */
0201
0202 /**
0203  * @name LPC32XX DMA Peripherals
0204  *
0205  * @{
0206  */
0207
0208 #define LPC32XX_DMA_PER_I2S_0_CH_0 0
0209 #define LPC32XX_DMA_PER_I2S_0_CH_1 13
0210 #define LPC32XX_DMA_PER_I2S_1_CH_0 2
0211 #define LPC32XX_DMA_PER_I2S_1_CH_1 10
0212 #define LPC32XX_DMA_PER_NAND_0 1
0213 #define LPC32XX_DMA_PER_NAND_1 12
0214 #define LPC32XX_DMA_PER_SD_MMC 4
0215 #define LPC32XX_DMA_PER_SSP_0_RX 14
0216 #define LPC32XX_DMA_PER_SSP_0_TX 15
0217 #define LPC32XX_DMA_PER_SSP_1_RX 3
0218 #define LPC32XX_DMA_PER_SSP_1_TX 11
0219 #define LPC32XX_DMA_PER_UART_1_RX 6
0220 #define LPC32XX_DMA_PER_UART_1_TX 5
0221 #define LPC32XX_DMA_PER_UART_2_RX 8
0222 #define LPC32XX_DMA_PER_UART_2_TX 7
0223 #define LPC32XX_DMA_PER_UART_7_RX 10
0224 #define LPC32XX_DMA_PER_UART_7_TX 9
0225
0226 /** @} */
0227
0228 /** @} */
0229
0230 #ifdef __cplusplus
0231 }
0232 #endif /* __cplusplus */
0233
0234 #endif /* LIBBSP_ARM_SHARED_LPC_DMA_H */