include/bsp/arm-pl111-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  *  @file
0005  *
0006  *  @ingroup RTEMSBSPsARMShared
0007  *
0008  *  @brief ARM PL111 Register definitions
0009  */
0010
0011 /*
0012  * Copyright (c) 2013 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_ARM_SHARED_ARM_PL111_REGS_H
0037 #define LIBBSP_ARM_SHARED_ARM_PL111_REGS_H
0038
0039 #include <bsp/utility.h>
0040
0041 typedef struct {
0042     uint32_t timing0;
0043 #define PL111_LCD_TIMING0_PPL(val) BSP_FLD32(val, 2, 7)
0044 #define PL111_LCD_TIMING0_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7)
0045 #define PL111_LCD_TIMING0_PPL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 7)
0046 #define PL111_LCD_TIMING0_HSW(val) BSP_FLD32(val, 8, 15)
0047 #define PL111_LCD_TIMING0_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15)
0048 #define PL111_LCD_TIMING0_HSW_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
0049 #define PL111_LCD_TIMING0_HFP(val) BSP_FLD32(val, 16, 23)
0050 #define PL111_LCD_TIMING0_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
0051 #define PL111_LCD_TIMING0_HFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
0052 #define PL111_LCD_TIMING0_HBP(val) BSP_FLD32(val, 24, 31)
0053 #define PL111_LCD_TIMING0_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
0054 #define PL111_LCD_TIMING0_HBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
0055     uint32_t timing1;
0056 #define PL111_LCD_TIMING1_LPP(val) BSP_FLD32(val, 0, 9)
0057 #define PL111_LCD_TIMING1_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9)
0058 #define PL111_LCD_TIMING1_LPP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
0059 #define PL111_LCD_TIMING1_VSW(val) BSP_FLD32(val, 10, 15)
0060 #define PL111_LCD_TIMING1_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15)
0061 #define PL111_LCD_TIMING1_VSW_SET(reg, val) BSP_FLD32SET(reg, val, 10, 15)
0062 #define PL111_LCD_TIMING1_VFP(val) BSP_FLD32(val, 16, 23)
0063 #define PL111_LCD_TIMING1_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
0064 #define PL111_LCD_TIMING1_VFP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
0065 #define PL111_LCD_TIMING1_VBP(val) BSP_FLD32(val, 24, 31)
0066 #define PL111_LCD_TIMING1_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
0067 #define PL111_LCD_TIMING1_VBP_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
0068     uint32_t timing2;
0069 #define PL111_LCD_TIMING2_PCD_LO(val) BSP_FLD32(val, 0, 4)
0070 #define PL111_LCD_TIMING2_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4)
0071 #define PL111_LCD_TIMING2_PCD_LO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
0072 #define PL111_LCD_TIMING2_CLKSEL BSP_BIT32(5)
0073 #define PL111_LCD_TIMING2_ACB(val) BSP_FLD32(val, 6, 10)
0074 #define PL111_LCD_TIMING2_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10)
0075 #define PL111_LCD_TIMING2_ACB_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10)
0076 #define PL111_LCD_TIMING2_IVS BSP_BIT32(11)
0077 #define PL111_LCD_TIMING2_IHS BSP_BIT32(12)
0078 #define PL111_LCD_TIMING2_IPC BSP_BIT32(13)
0079 #define PL111_LCD_TIMING2_IOE BSP_BIT32(14)
0080 #define PL111_LCD_TIMING2_CPL(val) BSP_FLD32(val, 16, 25)
0081 #define PL111_LCD_TIMING2_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25)
0082 #define PL111_LCD_TIMING2_CPL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25)
0083 #define PL111_LCD_TIMING2_BCD BSP_BIT32(26)
0084 #define PL111_LCD_TIMING2_PCD_HI(val) BSP_FLD32(val, 27, 31)
0085 #define PL111_LCD_TIMING2_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31)
0086 #define PL111_LCD_TIMING2_PCD_HI_SET(reg, val) BSP_FLD32SET(reg, val, 27, 31)
0087     uint32_t timing3;
0088 #define PL111_LCD_TIMING3_LED(val) BSP_FLD32(val, 0, 6)
0089 #define PL111_LCD_TIMING3_LED_GET(reg) BSP_FLD32GET(reg, 0, 6)
0090 #define PL111_LCD_TIMING3_LED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6)
0091 #define PL111_LCD_TIMING3_LEE BSP_BIT32(16)
0092     uint32_t upbase;
0093     uint32_t lpbase;
0094     uint32_t control;
0095 #define PL111_LCD_CONTROL_LCD_EN BSP_BIT32(0)
0096 #define PL111_LCD_CONTROL_LCD_BPP(val) BSP_FLD32(val, 1, 3)
0097 #define PL111_LCD_CONTROL_LCD_BPP_GET(reg) BSP_FLD32GET(reg, 1, 3)
0098 #define PL111_LCD_CONTROL_LCD_BPP_SET(reg, val) BSP_FLD32SET(reg, val, 1, 3)
0099 #define PL111_LCD_CONTROL_LCD_BPP_1 0x00U
0100 #define PL111_LCD_CONTROL_LCD_BPP_2 0x01U
0101 #define PL111_LCD_CONTROL_LCD_BPP_4 0x02U
0102 #define PL111_LCD_CONTROL_LCD_BPP_8 0x03U
0103 #define PL111_LCD_CONTROL_LCD_BPP_16 0x04U
0104 #define PL111_LCD_CONTROL_LCD_BPP_24 0x05U
0105 #define PL111_LCD_CONTROL_LCD_BPP_16_5_6_5 0x06U
0106 #define PL111_LCD_CONTROL_LCD_BPP_12 0x07U
0107 #define PL111_LCD_CONTROL_LCD_BW BSP_BIT32(4)
0108 #define PL111_LCD_CONTROL_LCD_TFT BSP_BIT32(5)
0109 #define PL111_LCD_CONTROL_LCD_MONO8 BSP_BIT32(6)
0110 #define PL111_LCD_CONTROL_LCD_DUAL BSP_BIT32(7)
0111 #define PL111_LCD_CONTROL_BGR BSP_BIT32(8)
0112 #define PL111_LCD_CONTROL_BEBO BSP_BIT32(9)
0113 #define PL111_LCD_CONTROL_BEPO BSP_BIT32(10)
0114 #define PL111_LCD_CONTROL_LCD_PWR BSP_BIT32(11)
0115 #define PL111_LCD_CONTROL_LCD_V_COMP(val) BSP_FLD32(val, 12, 13)
0116 #define PL111_LCD_CONTROL_LCD_V_COMP_GET(reg) BSP_FLD32GET(reg, 12, 13)
0117 #define PL111_LCD_CONTROL_LCD_V_COMP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13)
0118 #define PL111_LCD_CONTROL_WATERMARK BSP_BIT32(16)
0119     uint32_t imsc;
0120     uint32_t ris;
0121     uint32_t mis;
0122     uint32_t icr;
0123 #define PL111_LCD_I_FUF BSP_BIT32(1)
0124 #define PL111_LCD_I_LNBU BSP_BIT32(2)
0125 #define PL111_LCD_I_VCOMP BSP_BIT32(3)
0126 #define PL111_LCD_I_MBERROR BSP_BIT32(4)
0127     uint32_t upcurr;
0128     uint32_t lpcurr;
0129     uint32_t reserved_34[115];
0130     uint16_t pal[256];
0131 #define PL111_LCD_PAL_R(val) BSP_FLD16(val, 0, 4)
0132 #define PL111_LCD_PAL_R_GET(reg) BSP_FLD16GET(reg, 0, 4)
0133 #define PL111_LCD_PAL_R_SET(reg, val) BSP_FLD16SET(reg, val, 0, 4)
0134 #define PL111_LCD_PAL_G(val) BSP_FLD16(val, 5, 9)
0135 #define PL111_LCD_PAL_G_GET(reg) BSP_FLD16GET(reg, 5, 9)
0136 #define PL111_LCD_PAL_G_SET(reg, val) BSP_FLD16SET(reg, val, 5, 9)
0137 #define PL111_LCD_PAL_B(val) BSP_FLD16(val, 10, 14)
0138 #define PL111_LCD_PAL_B_GET(reg) BSP_FLD16GET(reg, 10, 14)
0139 #define PL111_LCD_PAL_B_SET(reg, val) BSP_FLD16SET(reg, val, 10, 14)
0140 #define PL111_LCD_PAL_I BSP_BIT16(15)
0141 } pl111_lcd;
0142
0143 typedef struct {
0144     uint8_t image[1024];
0145     uint32_t ctrl;
0146 #define PL111_CRSR_CTRL_ON BSP_BIT32(0)
0147 #define PL111_CRSR_CTRL_NUMBER(val) BSP_FLD32(val, 4, 5)
0148 #define PL111_CRSR_CTRL_NUMBER_GET(reg) BSP_FLD32GET(reg, 4, 5)
0149 #define PL111_CRSR_CTRL_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)
0150     uint32_t config;
0151 #define PL111_CRSR_CONFIG_SIZE BSP_BIT32(0)
0152 #define PL111_CRSR_CONFIG_FRAME_SYNC BSP_BIT32(1)
0153     uint32_t palette0;
0154     uint32_t palette1;
0155 #define PL111_CRSR_PALETTE_RED(val) BSP_FLD32(val, 0, 7)
0156 #define PL111_CRSR_PALETTE_RED_GET(reg) BSP_FLD32GET(reg, 0, 7)
0157 #define PL111_CRSR_PALETTE_RED_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
0158 #define PL111_CRSR_PALETTE_GREEN(val) BSP_FLD32(val, 8, 15)
0159 #define PL111_CRSR_PALETTE_GREEN_GET(reg) BSP_FLD32GET(reg, 8, 15)
0160 #define PL111_CRSR_PALETTE_GREEN_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
0161 #define PL111_CRSR_PALETTE_BLUE(val) BSP_FLD32(val, 16, 23)
0162 #define PL111_CRSR_PALETTE_BLUE_GET(reg) BSP_FLD32GET(reg, 16, 23)
0163 #define PL111_CRSR_PALETTE_BLUE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
0164     uint32_t xy;
0165 #define PL111_CRSR_XY_X(val) BSP_FLD32(val, 0, 9)
0166 #define PL111_CRSR_XY_X_GET(reg) BSP_FLD32GET(reg, 0, 9)
0167 #define PL111_CRSR_XY_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
0168 #define PL111_CRSR_XY_X_EXP(val) BSP_FLD32(val, 10, 11)
0169 #define PL111_CRSR_XY_X_EXP_GET(reg) BSP_FLD32GET(reg, 10, 11)
0170 #define PL111_CRSR_XY_X_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 10, 11)
0171 #define PL111_CRSR_XY_Y(val) BSP_FLD32(val, 16, 25)
0172 #define PL111_CRSR_XY_Y_GET(reg) BSP_FLD32GET(reg, 16, 25)
0173 #define PL111_CRSR_XY_Y_SET(reg, val) BSP_FLD32SET(reg, val, 16, 25)
0174 #define PL111_CRSR_XY_Y_EXP(val) BSP_FLD32(val, 25, 27)
0175 #define PL111_CRSR_XY_Y_EXP_GET(reg) BSP_FLD32GET(reg, 25, 27)
0176 #define PL111_CRSR_XY_Y_EXP_SET(reg, val) BSP_FLD32SET(reg, val, 25, 27)
0177     uint32_t clip;
0178 #define PL111_CRSR_CLIP_X(val) BSP_FLD32(val, 0, 5)
0179 #define PL111_CRSR_CLIP_X_GET(reg) BSP_FLD32GET(reg, 0, 5)
0180 #define PL111_CRSR_CLIP_X_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
0181 #define PL111_CRSR_CLIP_Y(val) BSP_FLD32(val, 8, 13)
0182 #define PL111_CRSR_CLIP_Y_GET(reg) BSP_FLD32GET(reg, 8, 13)
0183 #define PL111_CRSR_CLIP_Y_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
0184     uint32_t imsc;
0185     uint32_t icr;
0186     uint32_t ris;
0187     uint32_t mis;
0188 #define PL111_CRSR_I_CRSR BSP_BIT32(0)
0189 } pl111_crsr;
0190
0191 typedef struct {
0192     pl111_lcd lcd;
0193     uint32_t reserved_400[256];
0194     pl111_crsr crsr;
0195 } pl111;
0196
0197 #endif /* LIBBSP_ARM_SHARED_ARM_PL111_REGS_H */