include/bsp/arm-a9mpcore-start.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup A9MPCoreSupport
0007  *
0008  * @brief This header file provides the interfaces of the @ref A9MPCoreSupport.
0009  */
0010
0011 /*
0012  * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H
0037 #define LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H
0038
0039 #include <rtems/score/smpimpl.h>
0040
0041 #include <libcpu/arm-cp15.h>
0042
0043 #include <bsp.h>
0044 #include <bsp/start.h>
0045 #include <bsp/arm-a9mpcore-regs.h>
0046 #include <bsp/arm-cp15-start.h>
0047 #include <bsp/arm-errata.h>
0048 #include <dev/irq/arm-gic-irq.h>
0049
0050 #ifdef __cplusplus
0051 extern "C" {
0052 #endif /* __cplusplus */
0053
0054 /**
0055  * @addtogroup A9MPCoreSupport
0056  *
0057  * @{
0058  */
0059
0060 BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_scu_invalidate(
0061   volatile a9mpcore_scu *scu,
0062   uint32_t cpu_id,
0063   uint32_t ways
0064 )
0065 {
0066   scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4);
0067 }
0068
0069 BSP_START_TEXT_SECTION static inline void
0070 arm_a9mpcore_start_errata_764369_handler(volatile a9mpcore_scu *scu)
0071 {
0072   if (arm_errata_is_applicable_processor_errata_764369()) {
0073     scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE;
0074   }
0075 }
0076
0077 BSP_START_TEXT_SECTION static inline void
0078 arm_a9mpcore_start_scu_enable(volatile a9mpcore_scu *scu)
0079 {
0080   scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN;
0081   arm_a9mpcore_start_errata_764369_handler(scu);
0082 }
0083
0084 #ifdef RTEMS_SMP
0085 BSP_START_TEXT_SECTION static inline void
0086 arm_a9mpcore_start_on_secondary_processor(void)
0087 {
0088   uint32_t ctrl;
0089
0090   arm_gic_irq_initialize_secondary_cpu();
0091
0092   /* Change the VBAR from the start to the normal vector table */
0093   arm_cp15_set_vector_base_address(bsp_vector_table_begin);
0094
0095   ctrl = arm_cp15_start_setup_mmu_and_cache(
0096     0,
0097     ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
0098   );
0099
0100   arm_cp15_set_domain_access_control(
0101     ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT)
0102   );
0103
0104   /* FIXME: Sharing the translation table between processors is brittle */
0105   arm_cp15_set_translation_table_base(
0106     (uint32_t *) bsp_translation_table_base
0107   );
0108
0109   ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
0110   arm_cp15_set_control(ctrl);
0111
0112   _SMP_Start_multitasking_on_secondary_processor(_Per_CPU_Get());
0113 }
0114
0115 BSP_START_TEXT_SECTION static inline void
0116 arm_a9mpcore_start_enable_smp_in_auxiliary_control(void)
0117 {
0118   /*
0119    * Enable cache coherency support and cache/MMU maintenance broadcasts for
0120    * this processor.
0121    */
0122   uint32_t actlr = arm_cp15_get_auxiliary_control();
0123   actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW;
0124   arm_cp15_set_auxiliary_control(actlr);
0125 }
0126
0127 BSP_START_TEXT_SECTION static inline void
0128 arm_a9mpcore_start_errata_794072_handler(void)
0129 {
0130   uint32_t diag;
0131
0132   /*
0133    * Workaround for Errata 794072: A short loop including a DMB instruction
0134    * might cause a denial of service on another which executes a CP15 broadcast
0135    * operation.
0136    */
0137   diag = arm_cp15_get_diagnostic_control();
0138   diag |= 1U << 4;
0139   arm_cp15_set_diagnostic_control(diag);
0140 }
0141
0142 BSP_START_TEXT_SECTION static inline void
0143 arm_a9mpcore_start_errata_845369_handler(void)
0144 {
0145   uint32_t diag;
0146
0147   /*
0148    * Workaround for Errata 845369: Under Very Rare Timing Circumstances
0149    * Transition into Streaming Mode Might Create Data Corruption.
0150    */
0151   diag = arm_cp15_get_diagnostic_control();
0152   diag |= 1U << 22;
0153   arm_cp15_set_diagnostic_control(diag);
0154 }
0155 #endif
0156
0157 BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void)
0158 {
0159   volatile a9mpcore_scu *scu =
0160     (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
0161   uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
0162
0163   if (cpu_id == 0) {
0164     arm_a9mpcore_start_scu_enable(scu);
0165   }
0166
0167 #ifdef RTEMS_SMP
0168   arm_a9mpcore_start_errata_794072_handler();
0169   arm_a9mpcore_start_errata_845369_handler();
0170   arm_a9mpcore_start_enable_smp_in_auxiliary_control();
0171 #endif
0172
0173   arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf);
0174
0175 #ifdef RTEMS_SMP
0176   if (cpu_id != 0) {
0177     arm_a9mpcore_start_on_secondary_processor();
0178   }
0179 #endif
0180 }
0181
0182 BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_global_timer(void)
0183 {
0184   volatile a9mpcore_gt *gt = (volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE;
0185
0186   gt->ctrl = 0;
0187   gt->cntrlower = 0;
0188   gt->cntrupper = 0;
0189   gt->ctrl = A9MPCORE_GT_CTRL_TMR_EN;
0190 }
0191
0192 BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_1(void)
0193 {
0194   arm_a9mpcore_start_global_timer();
0195 }
0196
0197 /** @} */
0198
0199 #ifdef __cplusplus
0200 }
0201 #endif /* __cplusplus */
0202
0203 #endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H */