include/bsp/arm-a9mpcore-regs.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup A9MPCoreSupport
0007  *
0008  * @brief This header file provides the interfaces of the @ref A9MPCoreSupport.
0009  */
0010
0011 /*
0012  * Copyright (c) 2013 embedded brains GmbH & Co. KG
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
0037 #define LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
0038
0039 #include <bsp/utility.h>
0040
0041 /**
0042  * @defgroup A9MPCoreSupport Cortex-A9 MPCore Support
0043  *
0044  * @ingroup RTEMSBSPsARMShared
0045  *
0046  * @brief This group contains support interfaces for the Cortex-A9 MPCore.
0047  *
0048  * @{
0049  */
0050
0051 typedef struct {
0052   uint32_t ctrl;
0053 #define A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0)
0054 #define A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1)
0055 #define A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2)
0056 #define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3)
0057 #define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4)
0058 #define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5)
0059 #define A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6)
0060   uint32_t cfg;
0061 #define A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1)
0062 #define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1)
0063 #define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
0064 #define A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7)
0065 #define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7)
0066 #define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
0067 #define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15)
0068 #define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15)
0069 #define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
0070   uint32_t pwrst;
0071   uint32_t invss;
0072 #define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3)
0073 #define A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */
0074 #define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
0075 #define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7)
0076 #define A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */
0077 #define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
0078 #define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11)
0079 #define A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */
0080 #define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
0081 #define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15)
0082 #define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */
0083 #define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
0084   uint32_t reserved_09[8];
0085   uint32_t diagn_ctrl;
0086 #define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0)
0087   uint32_t reserved_10[3];
0088   uint32_t fltstart;
0089   uint32_t fltend;
0090   uint32_t reserved_48[2];
0091   uint32_t sac;
0092   uint32_t snsac;
0093 } a9mpcore_scu;
0094
0095 typedef struct {
0096 } a9mpcore_gic;
0097
0098 typedef struct {
0099   uint32_t cntrlower;
0100   uint32_t cntrupper;
0101 #define A9MPCORE_GT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
0102 #define A9MPCORE_GT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
0103 #define A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
0104 #define A9MPCORE_GT_CTRL_AUTOINC_EN BSP_BIT32(3)
0105 #define A9MPCORE_GT_CTRL_IRQ_EN BSP_BIT32(2)
0106 #define A9MPCORE_GT_CTRL_COMP_EN BSP_BIT32(1)
0107 #define A9MPCORE_GT_CTRL_TMR_EN BSP_BIT32(0)
0108   uint32_t ctrl;
0109 #define A9MPCORE_GT_IRQST_EFLG BSP_BIT32(0)
0110   uint32_t irqst;
0111   uint32_t cmpvallower;
0112   uint32_t cmpvalupper;
0113   uint32_t autoinc;
0114 } a9mpcore_gt;
0115
0116 typedef struct {
0117   uint32_t load;
0118   uint32_t cntr;
0119   uint32_t ctrl;
0120 #define A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
0121 #define A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
0122 #define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
0123 #define A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2)
0124 #define A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1)
0125 #define A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0)
0126   uint32_t irqst;
0127 #define A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0)
0128 } a9mpcore_pt;
0129
0130 typedef struct {
0131   uint32_t load;
0132   uint32_t cntr;
0133   uint32_t ctrl;
0134   uint32_t irqst;
0135   uint32_t rstst;
0136   uint32_t dis;
0137 } a9mpcore_pw;
0138
0139 typedef struct {
0140 } a9mpcore_idist;
0141
0142 typedef struct {
0143   a9mpcore_scu scu;
0144   uint32_t reserved_58[42];
0145   a9mpcore_gic gic;
0146   uint32_t reserved_100[64];
0147   a9mpcore_gt gt;
0148   uint32_t reserved_21c[249];
0149   a9mpcore_pt pt;
0150   uint32_t reserved_610[4];
0151   a9mpcore_pw pw;
0152   uint32_t reserved_638[626];
0153   a9mpcore_idist idist;
0154 } a9mpcore;
0155
0156 /** @} */
0157
0158 #endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H */