imxrt/start/mpu-config.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2020 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <imxrt/memory.h>
0029 #include <imxrt/mpu-config.h>
0030 #include <rtems/score/armv7m.h>
0031
0032 BSP_START_DATA_SECTION const ARMV7M_MPU_Region_config
0033   imxrt_config_mpu_region [] = {
0034     {
0035       .begin = imxrt_memory_extram_begin,
0036       .end = imxrt_memory_extram_end,
0037       .rasr = ARMV7M_MPU_RASR_AP(0x3)
0038         | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
0039         | ARMV7M_MPU_RASR_ENABLE,
0040     }, {
0041       .begin = imxrt_memory_ocram_begin,
0042       .end = imxrt_memory_ocram_end,
0043       .rasr = ARMV7M_MPU_RASR_AP(0x3)
0044         | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
0045         | ARMV7M_MPU_RASR_ENABLE,
0046     }, {
0047       .begin = imxrt_memory_flash_raw_begin,
0048       .end = imxrt_memory_flash_raw_end,
0049       .rasr = ARMV7M_MPU_RASR_AP(0x3)
0050         | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
0051         | ARMV7M_MPU_RASR_ENABLE,
0052     }, {
0053       .begin = imxrt_memory_extram_nocache_begin,
0054       .end = imxrt_memory_extram_nocache_end,
0055       .rasr = ARMV7M_MPU_RASR_AP(0x3)
0056         | ARMV7M_MPU_RASR_TEX(0x1)
0057         | ARMV7M_MPU_RASR_ENABLE,
0058     }, {
0059       .begin = imxrt_memory_ocram_nocache_begin,
0060       .end = imxrt_memory_ocram_nocache_end,
0061       .rasr = ARMV7M_MPU_RASR_AP(0x3)
0062         | ARMV7M_MPU_RASR_TEX(0x1)
0063         | ARMV7M_MPU_RASR_ENABLE,
0064     }, {
0065       .begin = imxrt_memory_peripheral_begin,
0066       .end = imxrt_memory_peripheral_end,
0067       .rasr = ARMV7M_MPU_RASR_XN
0068         | ARMV7M_MPU_RASR_AP(0x3)
0069         | ARMV7M_MPU_RASR_TEX(0x2)
0070         | ARMV7M_MPU_RASR_ENABLE,
0071     }, {
0072       .begin = imxrt_memory_null_begin,
0073       .end = imxrt_memory_null_end,
0074       .rasr = ARMV7M_MPU_RASR_XN
0075         | ARMV7M_MPU_RASR_AP(0x0)
0076         | ARMV7M_MPU_RASR_ENABLE,
0077     }
0078   };
0079
0080 BSP_START_DATA_SECTION const size_t imxrt_config_mpu_region_count =
0081   RTEMS_ARRAY_SIZE(imxrt_config_mpu_region);