imxrt/start/imxrt-ffec-init.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2020 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <bsp.h>
0029 #include <bsp/fdt.h>
0030 #include <bsp/imx-gpio.h>
0031 #include <chip.h>
0032 #include <fsl_clock.h>
0033 #include <libfdt.h>
0034 #include <rtems/counter.h>
0035
0036 void imxrt_ffec_init(void)
0037 {
0038   volatile IOMUXC_GPR_Type *iomuxc_gpr = IOMUXC_GPR;
0039   const void *fdt;
0040   int node;
0041
0042   fdt = bsp_fdt_get();
0043
0044 #if IMXRT_IS_MIMXRT10xx
0045   const clock_enet_pll_config_t config = {
0046     .enableClkOutput = true,
0047     .enableClkOutput25M = false,
0048     .loopDivider = 1
0049   };
0050
0051   CLOCK_InitEnetPll(&config);
0052
0053   iomuxc_gpr->GPR1 |= IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
0054 #else
0055   iomuxc_gpr->GPR4 |= IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
0056 #endif
0057
0058   node = fdt_node_offset_by_compatible(fdt, -1, "fsl,imxrt-fec");
0059   if (node >= 0) {
0060     struct imx_gpio_pin reset;
0061     struct imx_gpio_pin interrupt;
0062     rtems_status_code sc;
0063
0064     sc = imx_gpio_init_from_fdt_property(
0065         &reset, node, "phy-reset-gpios",
0066         IMX_GPIO_MODE_OUTPUT, 0);
0067
0068     if (sc == RTEMS_SUCCESSFUL) {
0069       sc = imx_gpio_init_from_fdt_property(
0070           &interrupt, node, "rtems,phy-interrupt-gpios",
0071           IMX_GPIO_MODE_INPUT, 0);
0072
0073       imx_gpio_set_output(&reset, 0);
0074       if (sc == RTEMS_SUCCESSFUL) {
0075         /* Force interrupt GPIO to high. Otherwise we
0076          * get NAND_TREE mode of the PHY. */
0077         interrupt.mode = IMX_GPIO_MODE_OUTPUT;
0078         imx_gpio_init(&interrupt);
0079         imx_gpio_set_output(&interrupt, 1);
0080       }
0081       rtems_counter_delay_nanoseconds(100000);
0082       imx_gpio_set_output(&reset, 1);
0083       rtems_counter_delay_nanoseconds(5);
0084       if (sc == RTEMS_SUCCESSFUL) {
0085         interrupt.mode = IMX_GPIO_MODE_INPUT;
0086         imx_gpio_init(&interrupt);
0087       }
0088     }
0089   }
0090 }