File indexing completed on 2025-05-11 08:23:02
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0028 #include <rtems/sysinit.h>
0029
0030 #include <bsp.h>
0031 #include <bsp/bootcard.h>
0032 #include <bsp/fdt.h>
0033 #include <bsp/imx-iomux.h>
0034 #include <bsp/irq-generic.h>
0035 #include <bsp/irq.h>
0036 #include <bsp/linker-symbols.h>
0037 #include <bsp/flash-headers.h>
0038 #include <fsl/edma.h>
0039
0040 #include <fsl_clock.h>
0041 #include <libfdt.h>
0042
0043 uint32_t imxrt_systick_frequency(void)
0044 {
0045 return CLOCK_GetCpuClkFreq();
0046 }
0047
0048 static void imxrt_disable_wait_mode(void)
0049 {
0050 #if IMXRT_IS_MIMXRT10xx
0051
0052
0053
0054
0055
0056
0057
0058
0059
0060
0061 CLOCK_SetMode(kCLOCK_ModeRun);
0062 #elif IMXRT_IS_MIMXRT11xx
0063
0064
0065
0066
0067
0068
0069 #else
0070 #error Disabling wait mode not implemented for this chip.
0071 #endif
0072 }
0073
0074 void bsp_start(void)
0075 {
0076 imxrt_disable_wait_mode();
0077
0078 bsp_interrupt_initialize();
0079 rtems_cache_coherent_add_area(
0080 bsp_section_nocacheheap_begin,
0081 (uintptr_t) bsp_section_nocacheheap_size
0082 );
0083 }
0084
0085 const void *bsp_fdt_get(void)
0086 {
0087 return imxrt_dtb;
0088 }
0089
0090 bool imxrt_fdt_node_is_enabled(const void *fdt, int node)
0091 {
0092 int len;
0093 const uint32_t *val;
0094
0095 val = fdt_getprop(fdt, node, "status", &len);
0096 if (val != NULL &&
0097 (strcmp((char*)val, "ok") == 0 || strcmp((char*)val, "okay") == 0)) {
0098 return true;
0099 }
0100
0101 return false;
0102 }
0103
0104 void *imx_get_reg_of_node(const void *fdt, int node)
0105 {
0106 int len;
0107 const uint32_t *val;
0108
0109 val = fdt_getprop(fdt, node, "reg", &len);
0110 if (val == NULL || len < 4) {
0111 return NULL;
0112 }
0113
0114 return (void *) fdt32_to_cpu(val[0]);
0115 }
0116
0117 rtems_vector_number imx_get_irq_of_node(
0118 const void *fdt,
0119 int node,
0120 size_t index
0121 )
0122 {
0123 int len;
0124 const uint32_t *val;
0125
0126 val = fdt_getprop(fdt, node, "interrupts", &len);
0127 if (val == NULL || len < (int) ((index) * 4)) {
0128 return BSP_INTERRUPT_VECTOR_INVALID;
0129 }
0130
0131 return fdt32_to_cpu(val[index]);
0132 }
0133
0134 uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
0135 {
0136 return intr[0];
0137 }
0138
0139
0140
0141
0142
0143 #if IMXRT_IS_MIMXRT11xx
0144 uint32_t
0145 imx_ccm_sdhci_hz(void)
0146 {
0147
0148
0149
0150
0151 return CLOCK_GetRootClockFreq(kCLOCK_Root_Usdhc1);
0152 }
0153 #endif
0154
0155
0156 __attribute__((used)) static const void *hdr_dcd = &imxrt_dcd_data;
0157 __attribute__((used)) static const void *hdr_ivt = &imxrt_image_vector_table;
0158 __attribute__((used)) static const void *hdr_btd = &imxrt_boot_data;
0159 __attribute__((used)) static const void *hdr_fsc = &imxrt_flexspi_config;
0160
0161
0162 __attribute__((used)) static const void *drv_iomux = &imx_iomux_configure_pins;
0163
0164 RTEMS_SYSINIT_ITEM(imxrt_lpspi_init, RTEMS_SYSINIT_DEVICE_DRIVERS,
0165 RTEMS_SYSINIT_ORDER_MIDDLE);
0166 RTEMS_SYSINIT_ITEM(imxrt_lpi2c_init, RTEMS_SYSINIT_DEVICE_DRIVERS,
0167 RTEMS_SYSINIT_ORDER_MIDDLE);
0168 RTEMS_SYSINIT_ITEM(imxrt_ffec_init, RTEMS_SYSINIT_DEVICE_DRIVERS,
0169 RTEMS_SYSINIT_ORDER_MIDDLE);
0170 RTEMS_SYSINIT_ITEM(fsl_edma_init, RTEMS_SYSINIT_DEVICE_DRIVERS,
0171 RTEMS_SYSINIT_ORDER_FIRST);