drivers/xbara/fsl_xbara.c

0001 /*
0002  * Copyright (c) 2015, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2019 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #include "fsl_xbara.h"
0010
0011 /*******************************************************************************
0012  * Definitions
0013  ******************************************************************************/
0014
0015 /* Component ID definition, used by tools. */
0016 #ifndef FSL_COMPONENT_ID
0017 #define FSL_COMPONENT_ID "platform.drivers.xbara"
0018 #endif
0019
0020 /* Macros for entire XBARA_CTRL register.  */
0021 #define XBARA_CTRLx(base, index) (((volatile uint16_t *)(&((base)->CTRL0)))[(index)])
0022
0023 typedef union
0024 {
0025     uint8_t _u8[2];
0026     uint16_t _u16;
0027 } xbara_u8_u16_t;
0028
0029 /*******************************************************************************
0030  * Prototypes
0031  ******************************************************************************/
0032
0033 /*!
0034  * @brief Get the XBARA instance from peripheral base address.
0035  *
0036  * @param base XBARA peripheral base address.
0037  * @return XBARA instance.
0038  */
0039 static uint32_t XBARA_GetInstance(XBARA_Type *base);
0040
0041 /*******************************************************************************
0042  * Variables
0043  ******************************************************************************/
0044
0045 /* Array of XBARA peripheral base address. */
0046 static XBARA_Type *const s_xbaraBases[] = XBARA_BASE_PTRS;
0047
0048 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0049 /* Array of XBARA clock name. */
0050 static const clock_ip_name_t s_xbaraClock[] = XBARA_CLOCKS;
0051 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0052
0053 /*******************************************************************************
0054  * Code
0055  ******************************************************************************/
0056
0057 static uint32_t XBARA_GetInstance(XBARA_Type *base)
0058 {
0059     uint32_t instance;
0060
0061     /* Find the instance index from base address mappings. */
0062     for (instance = 0; instance < ARRAY_SIZE(s_xbaraBases); instance++)
0063     {
0064         if (s_xbaraBases[instance] == base)
0065         {
0066             break;
0067         }
0068     }
0069
0070     assert(instance < ARRAY_SIZE(s_xbaraBases));
0071
0072     return instance;
0073 }
0074
0075 /*!
0076  * brief Initializes the XBARA module.
0077  *
0078  * This function un-gates the XBARA clock.
0079  *
0080  * param base XBARA peripheral address.
0081  */
0082 void XBARA_Init(XBARA_Type *base)
0083 {
0084 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0085     /* Enable XBARA module clock. */
0086     CLOCK_EnableClock(s_xbaraClock[XBARA_GetInstance(base)]);
0087 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0088 }
0089
0090 /*!
0091  * brief Shuts down the XBARA module.
0092  *
0093  * This function disables XBARA clock.
0094  *
0095  * param base XBARA peripheral address.
0096  */
0097 void XBARA_Deinit(XBARA_Type *base)
0098 {
0099 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0100     /* Disable XBARA module clock. */
0101     CLOCK_DisableClock(s_xbaraClock[XBARA_GetInstance(base)]);
0102 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0103 }
0104
0105 /*!
0106  * brief Sets a connection between the selected XBARA_IN[*] input and the XBARA_OUT[*] output signal.
0107  *
0108  * This function connects the XBARA input to the selected XBARA output.
0109  * If more than one XBARA module is available, only the inputs and outputs from the same module
0110  * can be connected.
0111  *
0112  * Example:
0113    code
0114    XBARA_SetSignalsConnection(XBARA, kXBARA_InputPIT_TRG0, kXBARA_OutputDMAMUX18);
0115    endcode
0116  *
0117  * param base XBARA peripheral address.
0118  * param input XBARA input signal.
0119  * param output XBARA output signal.
0120  */
0121 void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output)
0122 {
0123     xbara_u8_u16_t regVal;
0124     uint8_t byteInReg;
0125     uint8_t outputIndex = (uint8_t)output;
0126
0127     byteInReg = outputIndex % 2U;
0128
0129     regVal._u16 = XBARA_SELx(base, outputIndex);
0130
0131     regVal._u8[byteInReg] = (uint8_t)input;
0132
0133     XBARA_SELx(base, outputIndex) = regVal._u16;
0134 }
0135
0136 /*!
0137  * brief Gets the active edge detection status.
0138  *
0139  * This function gets the active edge detect status of all XBARA_OUTs. If the
0140  * active edge occurs, the return value is asserted. When the interrupt or the DMA
0141  * functionality is enabled for the XBARA_OUTx, this field is 1 when the interrupt
0142  * or DMA request is asserted and 0 when the interrupt or DMA request has been
0143  * cleared.
0144  *
0145  * param base XBARA peripheral address.
0146  * return the mask of these status flag bits.
0147  */
0148 uint32_t XBARA_GetStatusFlags(XBARA_Type *base)
0149 {
0150     uint32_t status_flag;
0151
0152     status_flag = ((uint32_t)base->CTRL0 & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
0153
0154     status_flag |= (((uint32_t)base->CTRL1 & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)) << 16U);
0155
0156     return status_flag;
0157 }
0158
0159 /*!
0160  * brief Clears the edge detection status flags of relative mask.
0161  *
0162  * param base XBARA peripheral address.
0163  * param mask the status flags to clear.
0164  */
0165 void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask)
0166 {
0167     uint16_t regVal;
0168
0169     /* Assign regVal to CTRL0 register's value */
0170     regVal = (base->CTRL0);
0171     /* Perform this command to avoid writing 1 into interrupt flag bits */
0172     regVal &= (uint16_t)(~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
0173     /* Write 1 to interrupt flag bits corresponding to mask */
0174     regVal |= (uint16_t)(mask & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
0175     /* Write regVal value into CTRL0 register */
0176     base->CTRL0 = regVal;
0177
0178     /* Assign regVal to CTRL1 register's value */
0179     regVal = (base->CTRL1);
0180     /* Perform this command to avoid writing 1 into interrupt flag bits */
0181     regVal &= (uint16_t)(~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK));
0182     /* Write 1 to interrupt flag bits corresponding to mask */
0183     regVal |= (uint16_t)((mask >> 16U) & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK));
0184     /* Write regVal value into CTRL1 register */
0185     base->CTRL1 = regVal;
0186 }
0187
0188 /*!
0189  * brief Configures the XBARA control register.
0190  *
0191  * This function configures an XBARA control register. The active edge detection
0192  * and the DMA/IRQ function on the corresponding XBARA output can be set.
0193  *
0194  * Example:
0195    code
0196    xbara_control_config_t userConfig;
0197    userConfig.activeEdge = kXBARA_EdgeRising;
0198    userConfig.requestType = kXBARA_RequestInterruptEnalbe;
0199    XBARA_SetOutputSignalConfig(XBARA, kXBARA_OutputDMAMUX18, &userConfig);
0200    endcode
0201  *
0202  * param base XBARA peripheral address.
0203  * param output XBARA output number.
0204  * param controlConfig Pointer to structure that keeps configuration of control register.
0205  */
0206 void XBARA_SetOutputSignalConfig(XBARA_Type *base,
0207                                  xbar_output_signal_t output,
0208                                  const xbara_control_config_t *controlConfig)
0209 {
0210     uint8_t outputIndex = (uint8_t)output;
0211     uint8_t regIndex;
0212     uint8_t byteInReg;
0213     xbara_u8_u16_t regVal;
0214
0215     assert(outputIndex < (uint32_t)FSL_FEATURE_XBARA_INTERRUPT_COUNT);
0216
0217     regIndex  = outputIndex / 2U;
0218     byteInReg = outputIndex % 2U;
0219
0220     regVal._u16 = XBARA_CTRLx(base, regIndex);
0221
0222     /* Don't clear the status flags. */
0223     regVal._u16 &= (uint16_t)(~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
0224
0225     regVal._u8[byteInReg] = (uint8_t)(XBARA_CTRL0_EDGE0(controlConfig->activeEdge) |
0226                                       (uint16_t)(((uint32_t)controlConfig->requestType) << XBARA_CTRL0_DEN0_SHIFT));
0227
0228     XBARA_CTRLx(base, regIndex) = regVal._u16;
0229 }