drivers/wdog01/fsl_wdog.h

0001 /*
0002  * Copyright (c) 2016, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2019 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008 #ifndef _FSL_WDOG_H_
0009 #define _FSL_WDOG_H_
0010
0011 #include "fsl_common.h"
0012
0013 /*!
0014  * @addtogroup wdog
0015  * @{
0016  */
0017
0018 /*******************************************************************************
0019  * Definitions
0020  *******************************************************************************/
0021 /*! @name Driver version */
0022 /*@{*/
0023 /*! @brief Defines WDOG driver version */
0024 #define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
0025 /*@}*/
0026 /*! @name Refresh sequence */
0027 /*@{*/
0028 #define WDOG_REFRESH_KEY (0xAAAA5555U)
0029 /*@}*/
0030
0031 /*! @brief Defines WDOG work mode. */
0032 typedef struct _wdog_work_mode
0033 {
0034     bool enableWait;  /*!< continue or suspend WDOG in wait mode  */
0035     bool enableStop;  /*!< continue or suspend WDOG in stop mode  */
0036     bool enableDebug; /*!< continue or suspend WDOG in debug mode */
0037 } wdog_work_mode_t;
0038
0039 /*! @brief Describes WDOG configuration structure. */
0040 typedef struct _wdog_config
0041 {
0042     bool enableWdog;             /*!< Enables or disables WDOG */
0043     wdog_work_mode_t workMode;   /*!< Configures WDOG work mode in debug stop and wait mode */
0044     bool enableInterrupt;        /*!< Enables or disables WDOG interrupt */
0045     uint16_t timeoutValue;       /*!< Timeout value */
0046     uint16_t interruptTimeValue; /*!< Interrupt count timeout value */
0047     bool softwareResetExtension; /*!< software reset extension */
0048     bool enablePowerDown;        /*!< power down enable bit */
0049     bool enableTimeOutAssert;    /*!< Enable WDOG_B timeout assertion. */
0050 } wdog_config_t;
0051
0052 /*!
0053  * @brief WDOG interrupt configuration structure, default settings all disabled.
0054  *
0055  * This structure contains the settings for all of the WDOG interrupt configurations.
0056  */
0057 enum _wdog_interrupt_enable
0058 {
0059     kWDOG_InterruptEnable = WDOG_WICR_WIE_MASK /*!< WDOG timeout generates an interrupt before reset*/
0060 };
0061
0062 /*!
0063  * @brief WDOG status flags.
0064  *
0065  * This structure contains the WDOG status flags for use in the WDOG functions.
0066  */
0067 enum _wdog_status_flags
0068 {
0069     kWDOG_RunningFlag       = WDOG_WCR_WDE_MASK,   /*!< Running flag, set when WDOG is enabled*/
0070     kWDOG_PowerOnResetFlag  = WDOG_WRSR_POR_MASK,  /*!< Power On flag, set when reset is the result of a powerOnReset*/
0071     kWDOG_TimeoutResetFlag  = WDOG_WRSR_TOUT_MASK, /*!< Timeout flag, set when reset is the result of a timeout*/
0072     kWDOG_SoftwareResetFlag = WDOG_WRSR_SFTW_MASK, /*!< Software flag, set when reset is the result of a software*/
0073     kWDOG_InterruptFlag     = WDOG_WICR_WTIS_MASK  /*!< interrupt flag,whether interrupt has occurred or not*/
0074 };
0075
0076 /*******************************************************************************
0077  * API
0078  *******************************************************************************/
0079
0080 #if defined(__cplusplus)
0081 extern "C" {
0082 #endif /* __cplusplus */
0083
0084 /*!
0085  * @name WDOG Initialization and De-initialization.
0086  * @{
0087  */
0088
0089 /*!
0090  * @brief Initializes the WDOG configuration structure.
0091  *
0092  * This function initializes the WDOG configuration structure to default values. The default
0093  * values are as follows.
0094  * @code
0095  *   wdogConfig->enableWdog = true;
0096  *   wdogConfig->workMode.enableWait = true;
0097  *   wdogConfig->workMode.enableStop = false;
0098  *   wdogConfig->workMode.enableDebug = false;
0099  *   wdogConfig->enableInterrupt = false;
0100  *   wdogConfig->enablePowerdown = false;
0101  *   wdogConfig->resetExtension = flase;
0102  *   wdogConfig->timeoutValue = 0xFFU;
0103  *   wdogConfig->interruptTimeValue = 0x04u;
0104  * @endcode
0105  *
0106  * @param config Pointer to the WDOG configuration structure.
0107  * @see wdog_config_t
0108  */
0109 void WDOG_GetDefaultConfig(wdog_config_t *config);
0110
0111 /*!
0112  * @brief Initializes the WDOG.
0113  *
0114  * This function initializes the WDOG. When called, the WDOG runs according to the configuration.
0115  *
0116  * This is an example.
0117  * @code
0118  *   wdog_config_t config;
0119  *   WDOG_GetDefaultConfig(&config);
0120  *   config.timeoutValue = 0xffU;
0121  *   config->interruptTimeValue = 0x04u;
0122  *   WDOG_Init(wdog_base,&config);
0123  * @endcode
0124  *
0125  * @param base   WDOG peripheral base address
0126  * @param config The configuration of WDOG
0127  */
0128 void WDOG_Init(WDOG_Type *base, const wdog_config_t *config);
0129
0130 /*!
0131  * @brief Shuts down the WDOG.
0132  *
0133  * This function shuts down the WDOG.
0134  * Watchdog Enable bit is a write one once only bit. It is not
0135  * possible to clear this bit by a software write, once the bit is set.
0136  * This bit(WDE) can be set/reset only in debug mode(exception).
0137  */
0138 void WDOG_Deinit(WDOG_Type *base);
0139
0140 /*!
0141  * @brief Enables the WDOG module.
0142  *
0143  * This function writes a value into the WDOG_WCR register to enable the WDOG.
0144  * This is a write one once only bit. It is not possible to clear this bit by a software write,
0145  * once the bit is set. only debug mode exception.
0146  * @param base WDOG peripheral base address
0147  */
0148 static inline void WDOG_Enable(WDOG_Type *base)
0149 {
0150     base->WCR |= WDOG_WCR_WDE_MASK;
0151 }
0152
0153 /*!
0154  * @brief Disables the WDOG module.
0155  *
0156  * This function writes a value into the WDOG_WCR register to disable the WDOG.
0157  * This is a write one once only bit. It is not possible to clear this bit by a software write,once the bit is set.
0158  * only debug mode exception
0159  * @param base WDOG peripheral base address
0160  */
0161 static inline void WDOG_Disable(WDOG_Type *base)
0162 {
0163     base->WCR &= ~(uint16_t)WDOG_WCR_WDE_MASK;
0164 }
0165
0166 /*!
0167  * @brief Trigger the system software reset.
0168  *
0169  * This function will write to the WCR[SRS] bit to trigger a software system reset.
0170  * This bit will automatically resets to "1" after it has been asserted to "0".
0171  * Note: Calling this API will reset the system right now, please using it with more attention.
0172  *
0173  * @param base WDOG peripheral base address
0174  */
0175 static inline void WDOG_TriggerSystemSoftwareReset(WDOG_Type *base)
0176 {
0177     base->WCR &= ~(uint16_t)WDOG_WCR_SRS_MASK;
0178 }
0179
0180 /*!
0181  * @brief Trigger an output assertion.
0182  *
0183  * This function will write to the WCR[WDA] bit to trigger WDOG_B signal assertion.
0184  * The WDOG_B signal can be routed to external pin of the chip, the output pin will turn to
0185  * assertion along with WDOG_B signal.
0186  * Note: The WDOG_B signal will remain assert until a power on reset occurred, so, please
0187  * take more attention while calling it.
0188  *
0189  * @param base WDOG peripheral base address
0190  */
0191 static inline void WDOG_TriggerSoftwareSignal(WDOG_Type *base)
0192 {
0193     base->WCR &= ~(uint16_t)WDOG_WCR_WDA_MASK;
0194 }
0195
0196 /*!
0197  * @brief Enables the WDOG interrupt.
0198  *
0199  *This bit is a write once only bit. Once the software does a write access to this bit, it will get
0200  *locked and cannot be reprogrammed until the next system reset assertion
0201  *
0202  * @param base WDOG peripheral base address
0203  * @param mask The interrupts to enable
0204  * The parameter can be combination of the following source if defined.
0205  * @arg kWDOG_InterruptEnable
0206  */
0207 static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint16_t mask)
0208 {
0209     base->WICR |= mask;
0210 }
0211
0212 /*!
0213  * @brief Gets the WDOG all reset status flags.
0214  *
0215  * This function gets all reset status flags.
0216  *
0217  * @code
0218  * uint16_t status;
0219  * status = WDOG_GetStatusFlags (wdog_base);
0220  * @endcode
0221  * @param base        WDOG peripheral base address
0222  * @return            State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags
0223  *                    - true: a related status flag has been set.
0224  *                    - false: a related status flag is not set.
0225  */
0226 uint16_t WDOG_GetStatusFlags(WDOG_Type *base);
0227
0228 /*!
0229  * @brief Clears the WDOG flag.
0230  *
0231  * This function clears the WDOG status flag.
0232  *
0233  * This is an example for clearing the interrupt flag.
0234  * @code
0235  *   WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag);
0236  * @endcode
0237  * @param base        WDOG peripheral base address
0238  * @param mask        The status flags to clear.
0239  *                    The parameter could be any combination of the following values.
0240  *                    kWDOG_TimeoutFlag
0241  */
0242 void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask);
0243
0244 /*!
0245  * @brief Sets the WDOG timeout value.
0246  *
0247  * This function sets the timeout value.
0248  * This function writes a value into WCR registers.
0249  * The time-out value can be written at any point of time but it is loaded to the counter at the time
0250  * when WDOG is enabled or after the service routine has been performed.
0251  *
0252  * @param base WDOG peripheral base address
0253  * @param timeoutCount WDOG timeout value; count of WDOG clock tick.
0254  */
0255 static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount)
0256 {
0257     base->WCR = (base->WCR & (uint16_t)~WDOG_WCR_WT_MASK) | WDOG_WCR_WT(timeoutCount);
0258 }
0259
0260 /*!
0261  * @brief Sets the WDOG interrupt count timeout value.
0262  *
0263  * This function sets the interrupt count timeout value.
0264  * This function writes a value into WIC registers which are wirte-once.
0265  * This field is write once only. Once the software does a write access to this field, it will get locked
0266  * and cannot be reprogrammed until the next system reset assertion.
0267  * @param base WDOG peripheral base address
0268  * @param timeoutCount WDOG timeout value; count of WDOG clock tick.
0269  */
0270 static inline void WDOG_SetInterrputTimeoutValue(WDOG_Type *base, uint16_t timeoutCount)
0271 {
0272     base->WICR = (base->WICR & ~(uint16_t)WDOG_WICR_WICT_MASK) | WDOG_WICR_WICT(timeoutCount);
0273 }
0274
0275 /*!
0276  * @brief Disable the WDOG power down enable bit.
0277  *
0278  * This function disable the WDOG power down enable(PDE).
0279  * This function writes a value into WMCR registers which are wirte-once.
0280  * This field is write once only. Once software sets this bit it cannot be reset until the next system reset.
0281  * @param base WDOG peripheral base address
0282  */
0283 static inline void WDOG_DisablePowerDownEnable(WDOG_Type *base)
0284 {
0285     base->WMCR &= ~(uint16_t)WDOG_WMCR_PDE_MASK;
0286 }
0287
0288 /*!
0289  * @brief Refreshes the WDOG timer.
0290  *
0291  * This function feeds the WDOG.
0292  * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted.
0293  *
0294  * @param base WDOG peripheral base address
0295  */
0296 void WDOG_Refresh(WDOG_Type *base);
0297 /*@}*/
0298
0299 #if defined(__cplusplus)
0300 }
0301 #endif /* __cplusplus */
0302
0303 /*! @}*/
0304
0305 #endif /* _FSL_WDOG_H_ */