drivers/wdog01/fsl_wdog.c

0001 /*
0002  * Copyright (c) 2016, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2019 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #include "fsl_wdog.h"
0010
0011 /* Component ID definition, used by tools. */
0012 #ifndef FSL_COMPONENT_ID
0013 #define FSL_COMPONENT_ID "platform.drivers.wdog01"
0014 #endif
0015
0016 /*******************************************************************************
0017  * Variables
0018  ******************************************************************************/
0019 static WDOG_Type *const s_wdogBases[] = WDOG_BASE_PTRS;
0020 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0021 /* Array of WDOG clock name. */
0022 static const clock_ip_name_t s_wdogClock[] = WDOG_CLOCKS;
0023 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0024
0025 static const IRQn_Type s_wdogIRQ[] = WDOG_IRQS;
0026
0027 /*******************************************************************************
0028  * Code
0029  ******************************************************************************/
0030 static uint32_t WDOG_GetInstance(WDOG_Type *base)
0031 {
0032     uint32_t instance;
0033
0034     /* Find the instance index from base address mappings. */
0035     for (instance = 0; instance < ARRAY_SIZE(s_wdogBases); instance++)
0036     {
0037         if (s_wdogBases[instance] == base)
0038         {
0039             break;
0040         }
0041     }
0042
0043     assert(instance < ARRAY_SIZE(s_wdogBases));
0044
0045     return instance;
0046 }
0047
0048 /*!
0049  * brief Initializes the WDOG configuration structure.
0050  *
0051  * This function initializes the WDOG configuration structure to default values. The default
0052  * values are as follows.
0053  * code
0054  *   wdogConfig->enableWdog = true;
0055  *   wdogConfig->workMode.enableWait = true;
0056  *   wdogConfig->workMode.enableStop = false;
0057  *   wdogConfig->workMode.enableDebug = false;
0058  *   wdogConfig->enableInterrupt = false;
0059  *   wdogConfig->enablePowerdown = false;
0060  *   wdogConfig->resetExtension = flase;
0061  *   wdogConfig->timeoutValue = 0xFFU;
0062  *   wdogConfig->interruptTimeValue = 0x04u;
0063  * endcode
0064  *
0065  * param config Pointer to the WDOG configuration structure.
0066  * see wdog_config_t
0067  */
0068 void WDOG_GetDefaultConfig(wdog_config_t *config)
0069 {
0070     assert(NULL != config);
0071
0072     /* Initializes the configure structure to zero. */
0073     (void)memset(config, 0, sizeof(*config));
0074
0075     config->enableWdog             = true;
0076     config->workMode.enableWait    = false;
0077     config->workMode.enableStop    = false;
0078     config->workMode.enableDebug   = false;
0079     config->enableInterrupt        = false;
0080     config->softwareResetExtension = false;
0081     config->enablePowerDown        = false;
0082     config->timeoutValue           = 0xffu;
0083     config->interruptTimeValue     = 0x04u;
0084     config->enableTimeOutAssert    = false;
0085 }
0086
0087 /*!
0088  * brief Initializes the WDOG.
0089  *
0090  * This function initializes the WDOG. When called, the WDOG runs according to the configuration.
0091  *
0092  * This is an example.
0093  * code
0094  *   wdog_config_t config;
0095  *   WDOG_GetDefaultConfig(&config);
0096  *   config.timeoutValue = 0xffU;
0097  *   config->interruptTimeValue = 0x04u;
0098  *   WDOG_Init(wdog_base,&config);
0099  * endcode
0100  *
0101  * param base   WDOG peripheral base address
0102  * param config The configuration of WDOG
0103  */
0104 void WDOG_Init(WDOG_Type *base, const wdog_config_t *config)
0105 {
0106     assert(NULL != config);
0107
0108     uint16_t value        = 0u;
0109     uint32_t primaskValue = 0U;
0110
0111     value = WDOG_WCR_WDE(config->enableWdog) | WDOG_WCR_WDW(config->workMode.enableWait) |
0112             WDOG_WCR_WDZST(config->workMode.enableStop) | WDOG_WCR_WDBG(config->workMode.enableDebug) |
0113             WDOG_WCR_SRE(config->softwareResetExtension) | WDOG_WCR_WT(config->timeoutValue) |
0114             WDOG_WCR_WDT(config->enableTimeOutAssert) | WDOG_WCR_SRS_MASK | WDOG_WCR_WDA_MASK;
0115
0116 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0117     /* Set configuration */
0118     CLOCK_EnableClock(s_wdogClock[WDOG_GetInstance(base)]);
0119 #endif
0120
0121     primaskValue = DisableGlobalIRQ();
0122     base->WICR   = WDOG_WICR_WICT(config->interruptTimeValue) | WDOG_WICR_WIE(config->enableInterrupt);
0123     base->WMCR   = WDOG_WMCR_PDE(config->enablePowerDown);
0124     base->WCR    = value;
0125     EnableGlobalIRQ(primaskValue);
0126     if (config->enableInterrupt)
0127     {
0128         (void)EnableIRQ(s_wdogIRQ[WDOG_GetInstance(base)]);
0129     }
0130 }
0131
0132 /*!
0133  * brief Shuts down the WDOG.
0134  *
0135  * This function shuts down the WDOG.
0136  * Watchdog Enable bit is a write one once only bit. It is not
0137  * possible to clear this bit by a software write, once the bit is set.
0138  * This bit(WDE) can be set/reset only in debug mode(exception).
0139  */
0140 void WDOG_Deinit(WDOG_Type *base)
0141 {
0142     if (0U != (base->WCR & WDOG_WCR_WDBG_MASK))
0143     {
0144         WDOG_Disable(base);
0145     }
0146 }
0147
0148 /*!
0149  * brief Gets the WDOG all reset status flags.
0150  *
0151  * This function gets all reset status flags.
0152  *
0153  * code
0154  * uint16_t status;
0155  * status = WDOG_GetStatusFlags (wdog_base);
0156  * endcode
0157  * param base        WDOG peripheral base address
0158  * return            State of the status flag: asserted (true) or not-asserted (false).see _wdog_status_flags
0159  *                    - true: a related status flag has been set.
0160  *                    - false: a related status flag is not set.
0161  */
0162 uint16_t WDOG_GetStatusFlags(WDOG_Type *base)
0163 {
0164     uint16_t status_flag = 0U;
0165
0166     status_flag |= (base->WCR & WDOG_WCR_WDE_MASK);
0167     status_flag |= (base->WRSR & WDOG_WRSR_POR_MASK);
0168     status_flag |= (base->WRSR & WDOG_WRSR_TOUT_MASK);
0169     status_flag |= (base->WRSR & WDOG_WRSR_SFTW_MASK);
0170     status_flag |= (base->WICR & WDOG_WICR_WTIS_MASK);
0171
0172     return status_flag;
0173 }
0174
0175 /*!
0176  * brief Clears the WDOG flag.
0177  *
0178  * This function clears the WDOG status flag.
0179  *
0180  * This is an example for clearing the interrupt flag.
0181  * code
0182  *   WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag);
0183  * endcode
0184  * param base        WDOG peripheral base address
0185  * param mask        The status flags to clear.
0186  *                    The parameter could be any combination of the following values.
0187  *                    kWDOG_TimeoutFlag
0188  */
0189 void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask)
0190 {
0191     if (0U != (mask & (uint16_t)kWDOG_InterruptFlag))
0192     {
0193         base->WICR |= WDOG_WICR_WTIS_MASK;
0194     }
0195 }
0196
0197 /*!
0198  * brief Refreshes the WDOG timer.
0199  *
0200  * This function feeds the WDOG.
0201  * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted.
0202  *
0203  * param base WDOG peripheral base address
0204  */
0205 void WDOG_Refresh(WDOG_Type *base)
0206 {
0207     uint32_t primaskValue = 0U;
0208
0209     /* Disable the global interrupt to protect refresh sequence */
0210     primaskValue = DisableGlobalIRQ();
0211     base->WSR    = WDOG_REFRESH_KEY & 0xFFFFU;
0212     base->WSR    = (WDOG_REFRESH_KEY >> 16U) & 0xFFFFU;
0213     EnableGlobalIRQ(primaskValue);
0214 }