drivers/src/fsl_src.h

0001 /*
0002  * Copyright (c) 2016, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2020 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #ifndef _FSL_SRC_H_
0010 #define _FSL_SRC_H_
0011
0012 #include "fsl_common.h"
0013
0014 /*!
0015  * @addtogroup src
0016  * @{
0017  */
0018
0019 /*******************************************************************************
0020  * Definitions
0021  ******************************************************************************/
0022
0023 /*! @name Driver version */
0024 /*@{*/
0025 /*! @brief SRC driver version 2.0.1. */
0026 #define FSL_SRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
0027 /*@}*/
0028
0029 /*!
0030  * @brief SRC reset status flags.
0031  */
0032 enum _src_reset_status_flags
0033 {
0034 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT) && FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT)
0035     kSRC_ResetOutputEnableFlag = SRC_SRSR_RESET_OUT_MASK, /*!< This bit indicates if RESET status is
0036                                                                driven out on PTE0 pin. */
0037 #endif                                                    /* FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT */
0038 #if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI)
0039     kSRC_WarmBootIndicationFlag = SRC_SRSR_WBI_MASK,     /*!< WARM boot indication shows that WARM boot
0040                                                               was initiated by software. */
0041 #endif                                                   /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */
0042     kSRC_TemperatureSensorResetFlag = SRC_SRSR_TSR_MASK, /*!< Indicates whether the reset was the
0043                                                               result of software reset from on-chip
0044                                                               Temperature Sensor. Temperature Sensor
0045                                                               Interrupt needs to be served before this
0046                                                               bit can be cleaned.*/
0047 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) && FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B)
0048     kSRC_Wdog3ResetFlag = SRC_SRSR_WDOG3_RST_B_MASK, /*!< IC Watchdog3 Time-out reset. Indicates
0049                                                           whether the reset was the result of the
0050                                                           watchdog3 time-out event. */
0051 #endif                                               /* FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B */
0052 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_SW) && FSL_FEATURE_SRC_HAS_SRSR_SW)
0053     kSRC_SoftwareResetFlag = SRC_SRSR_SW_MASK, /*!< Indicates a reset has been caused by software
0054                                                     setting of SYSRESETREQ bit in Application
0055                                                     Interrupt and Reset Control Register in the
0056                                                     ARM core. */
0057 #endif                                         /* FSL_FEATURE_SRC_HAS_SRSR_SW */
0058 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST) && FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST)
0059     kSRC_JTAGSystemResetFlag =
0060         SRC_SRSR_JTAG_SW_RST_MASK, /*!< Indicates whether the reset was the result of software reset form JTAG */
0061 #endif                             /* FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST */
0062     kSRC_JTAGSoftwareResetFlag = SRC_SRSR_SJC_MASK,   /*!< Indicates whether the reset was the result of
0063                                                       setting SJC_GPCCR bit 31. */
0064     kSRC_JTAGGeneratedResetFlag = SRC_SRSR_JTAG_MASK, /*!< Indicates a reset has been caused by JTAG
0065                                                            selection of certain IR codes: EXTEST or
0066                                                            HIGHZ. */
0067     kSRC_WatchdogResetFlag = SRC_SRSR_WDOG_MASK,      /*!< Indicates a reset has been caused by the
0068                                                            watchdog timer timing out. This reset source
0069                                                            can be blocked by disabling the watchdog. */
0070 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B)
0071     kSRC_IppUserResetFlag = SRC_SRSR_IPP_USER_RESET_B_MASK, /*!< Indicates whether the reset was the
0072                                                                  result of the ipp_user_reset_b
0073                                                                  qualified reset. */
0074 #endif                                                      /* FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B */
0075 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_SNVS) && FSL_FEATURE_SRC_HAS_SRSR_SNVS)
0076     kSRC_SNVSFailResetFlag = SRC_SRSR_SNVS_MASK, /*!< SNVS hardware failure will always cause a cold
0077                                                       reset. This flag indicates whether the reset
0078                                                       is a result of SNVS hardware failure. */
0079 #endif                                           /* FSL_FEATURE_SRC_HAS_SRSR_SNVS */
0080 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B)
0081     kSRC_CsuResetFlag = SRC_SRSR_CSU_RESET_B_MASK, /*!< Indicates whether the reset was the result
0082                                                         of the csu_reset_b input. */
0083 #endif                                             /* FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B */
0084 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP)
0085     kSRC_CoreLockupResetFlag = SRC_SRSR_LOCKUP_MASK, /*!< Indicates a reset has been caused by the
0086                                                           ARM core indication of a LOCKUP event. */
0087 #endif                                               /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP */
0088 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_POR) && FSL_FEATURE_SRC_HAS_SRSR_POR)
0089     kSRC_PowerOnResetFlag = SRC_SRSR_POR_MASK, /*!< Indicates a reset has been caused by the
0090                                                     power-on detection logic. */
0091 #endif                                         /* FSL_FEATURE_SRC_HAS_SRSR_POR */
0092 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ)
0093     kSRC_LockupSysResetFlag =
0094         SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software
0095                                                setting of SYSRESETREQ bit in Application Interrupt and
0096                                                Reset Control Register of the ARM core. */
0097 #endif                                    /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */
0098 #if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B)
0099     kSRC_IppResetPinFlag = SRC_SRSR_IPP_RESET_B_MASK, /*!< Indicates whether reset was the result of
0100                                                            ipp_reset_b pin (Power-up sequence). */
0101 #endif                                                /* FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B */
0102 };
0103
0104 #if (defined(FSL_FEATURE_SRC_HAS_SISR) && FSL_FEATURE_SRC_HAS_SISR)
0105 /*!
0106  * @brief SRC interrupt status flag.
0107  */
0108 enum _src_status_flags
0109 {
0110     kSRC_Core0WdogResetReqFlag =
0111         SRC_SISR_CORE0_WDOG_RST_REQ_MASK, /*!< WDOG reset request from core0. Read-only status bit. */
0112 };
0113 #endif /* FSL_FEATURE_SRC_HAS_SISR */
0114
0115 #if (defined(FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) && FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH)
0116 /*!
0117  * @brief Selection of SoC mix power reset stretch.
0118  *
0119  * This type defines the SoC mix (Audio, ENET, uSDHC, EIM, QSPI, OCRAM, MMDC, etc) power up reset
0120  * stretch mix reset width with the optional count of cycles
0121  */
0122 typedef enum _src_mix_reset_stretch_cycles
0123 {
0124     kSRC_MixResetStretchCycleAlt0 = 0U, /*!< mix reset width is 1 x 88 ipg_cycle cycles. */
0125     kSRC_MixResetStretchCycleAlt1 = 1U, /*!< mix reset width is 2 x 88 ipg_cycle cycles. */
0126     kSRC_MixResetStretchCycleAlt2 = 2U, /*!< mix reset width is 3 x 88 ipg_cycle cycles. */
0127     kSRC_MixResetStretchCycleAlt3 = 3U, /*!< mix reset width is 4 x 88 ipg_cycle cycles. */
0128 } src_mix_reset_stretch_cycles_t;
0129 #endif /* FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH */
0130
0131 #if (defined(FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) && FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN)
0132 /*!
0133  * @brief Selection of WDOG3 reset option.
0134  */
0135 typedef enum _src_wdog3_reset_option
0136 {
0137     kSRC_Wdog3ResetOptionAlt0 = 0U, /*!< Wdog3_rst_b asserts M4 reset (default). */
0138     kSRC_Wdog3ResetOptionAlt1 = 1U, /*!< Wdog3_rst_b asserts global reset. */
0139 } src_wdog3_reset_option_t;
0140 #endif /* FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN */
0141
0142 /*!
0143  * @brief Selection of WARM reset bypass count.
0144  *
0145  * This type defines the  32KHz clock cycles to count before bypassing the MMDC acknowledge for WARM
0146  * reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD reset will
0147  * be initiated.
0148  */
0149 typedef enum _src_warm_reset_bypass_count
0150 {
0151     kSRC_WarmResetWaitAlways = 0U, /*!< System will wait until MMDC acknowledge is asserted. */
0152     kSRC_WarmResetWaitClk16  = 1U, /*!< Wait 16 32KHz clock cycles before switching the reset. */
0153     kSRC_WarmResetWaitClk32  = 2U, /*!< Wait 32 32KHz clock cycles before switching the reset. */
0154     kSRC_WarmResetWaitClk64  = 3U, /*!< Wait 64 32KHz clock cycles before switching the reset. */
0155 } src_warm_reset_bypass_count_t;
0156
0157 #if defined(__cplusplus)
0158 extern "C" {
0159 #endif
0160
0161 /*******************************************************************************
0162  * API
0163  ******************************************************************************/
0164
0165 #if (defined(FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST) && FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST)
0166 /*!
0167  * @brief Enable the WDOG3 reset.
0168  *
0169  * The WDOG3 reset is enabled by default.
0170  *
0171  * @param base SRC peripheral base address.
0172  * @param enable Enable the reset or not.
0173  */
0174 static inline void SRC_EnableWDOG3Reset(SRC_Type *base, bool enable)
0175 {
0176     if (enable)
0177     {
0178         base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0xA);
0179     }
0180     else
0181     {
0182         base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0x5);
0183     }
0184 }
0185 #endif /* FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST */
0186
0187 #if (defined(FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) && FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH)
0188 /*!
0189  * @brief Set the mix power up reset stretch mix reset width.
0190  *
0191  * @param base SRC peripheral base address.
0192  * @param option Setting option, see to #src_mix_reset_stretch_cycles_t.
0193  */
0194 static inline void SRC_SetMixResetStretchCycles(SRC_Type *base, src_mix_reset_stretch_cycles_t option)
0195 {
0196     base->SCR = (base->SCR & ~SRC_SCR_MIX_RST_STRCH_MASK) | SRC_SCR_MIX_RST_STRCH(option);
0197 }
0198 #endif /* FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH */
0199
0200 #if (defined(FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG) && FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG)
0201 /*!
0202  * @brief Debug reset would be asserted after power gating event.
0203  *
0204  * @param base SRC peripheral base address.
0205  * @param enable Enable the reset or not.
0206  */
0207 static inline void SRC_EnableCoreDebugResetAfterPowerGate(SRC_Type *base, bool enable)
0208 {
0209     if (enable)
0210     {
0211         base->SCR &= ~SRC_SCR_DBG_RST_MSK_PG_MASK;
0212     }
0213     else
0214     {
0215         base->SCR |= SRC_SCR_DBG_RST_MSK_PG_MASK;
0216     }
0217 }
0218 #endif /* FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG */
0219
0220 #if (defined(FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) && FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN)
0221 /*!
0222  * @brief Set the Wdog3_rst_b option.
0223  *
0224  * @param base SRC peripheral base address.
0225  * @param option Setting option, see to #src_wdog3_reset_option_t.
0226  */
0227 static inline void SRC_SetWdog3ResetOption(SRC_Type *base, src_wdog3_reset_option_t option)
0228 {
0229     base->SCR = (base->SCR & ~SRC_SCR_WDOG3_RST_OPTN_MASK) | SRC_SCR_WDOG3_RST_OPTN(option);
0230 }
0231 #endif /* FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN */
0232
0233 #if (defined(FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST) && FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST)
0234 /*!
0235  * @brief Software reset for debug of arm platform only.
0236  *
0237  * @param base SRC peripheral base address.
0238  */
0239 static inline void SRC_DoSoftwareResetARMCoreDebug(SRC_Type *base)
0240 {
0241     base->SCR |= SRC_SCR_CORES_DBG_RST_MASK;
0242 }
0243
0244 /*!
0245  * @brief Check if the software reset for debug of arm platform only is done.
0246  *
0247  * @param base SRC peripheral base address.
0248  */
0249 static inline bool SRC_GetSoftwareResetARMCoreDebugDone(SRC_Type *base)
0250 {
0251     return (0U == (base->SCR & SRC_SCR_CORES_DBG_RST_MASK));
0252 }
0253 #endif /* FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST */
0254
0255 #if (defined(FSL_FEATURE_SRC_HAS_SCR_MTSR) && FSL_FEATURE_SRC_HAS_SCR_MTSR)
0256 /*!
0257  * @brief Enable the temperature sensor reset.
0258  *
0259  * The temperature sersor reset is enabled by default. When the sensor reset happens, an flag bit
0260  * would be asserted. This flag bit can be cleared only by the hardware reset.
0261  *
0262  * @param base SRC peripheral base address.
0263  * @param enable Enable the reset or not.
0264  */
0265 static inline void SRC_EnableTemperatureSensorReset(SRC_Type *base, bool enable)
0266 {
0267     if (enable) /* Temperature sensor reset is not masked. (default) */
0268     {
0269         base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x2);
0270     }
0271     else /* The on-chip temperature sensor interrupt will not create a reset to the chip. */
0272     {
0273         base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x5);
0274     }
0275 }
0276 #endif /* FSL_FEATURE_SRC_HAS_SCR_MTSR */
0277
0278 #if (defined(FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST) && FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST)
0279 /*!
0280  * @brief Do assert the core0 debug reset.
0281  *
0282  * @param base SRC peripheral base address.
0283  */
0284 static inline void SRC_DoAssertCore0DebugReset(SRC_Type *base)
0285 {
0286     base->SCR |= SRC_SCR_CORE0_DBG_RST_MASK;
0287 }
0288
0289 /*!
0290  * @brief Check if the core0 debug reset is done.
0291  *
0292  * @param base SRC peripheral base address.
0293  */
0294 static inline bool SRC_GetAssertCore0DebugResetDone(SRC_Type *base)
0295 {
0296     return (0U == (base->SCR & SRC_SCR_CORE0_DBG_RST_MASK));
0297 }
0298 #endif /* FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST */
0299
0300 #if (defined(FSL_FEATURE_SRC_HAS_SCR_CORE0_RST) && FSL_FEATURE_SRC_HAS_SCR_CORE0_RST)
0301 /*!
0302  * @brief Do software reset the ARM core0 only.
0303  *
0304  * @param base SRC peripheral base address.
0305  */
0306 static inline void SRC_DoSoftwareResetARMCore0(SRC_Type *base)
0307 {
0308     base->SCR |= SRC_SCR_CORE0_RST_MASK;
0309 }
0310
0311 /*!
0312  * @brief Check if the software for ARM core0 is done.
0313  *
0314  * @param base SRC peripheral base address.
0315  * @return If the reset is done.
0316  */
0317 static inline bool SRC_GetSoftwareResetARMCore0Done(SRC_Type *base)
0318 {
0319     return (0U == (base->SCR & SRC_SCR_CORE0_RST_MASK));
0320 }
0321 #endif /* FSL_FEATURE_SRC_HAS_SCR_CORE0_RST */
0322
0323 #if (defined(FSL_FEATURE_SRC_HAS_SCR_SWRC) && FSL_FEATURE_SRC_HAS_SCR_SWRC)
0324 /*!
0325  * @brief Do software reset for ARM core.
0326  *
0327  * This function can be used to assert the ARM core reset. Once it is called, the reset process will
0328  * begin. After the reset process is finished, the command bit would be self cleared.
0329  *
0330  * @param base SRC peripheral base address.
0331  */
0332 static inline void SRC_DoSoftwareResetARMCore(SRC_Type *base)
0333 {
0334     base->SCR |= SRC_SCR_SWRC_MASK;
0335 }
0336
0337 /*!
0338  * @brief Check if the software for ARM core is done.
0339  *
0340  * @param base SRC peripheral base address.
0341  * @return If the reset is done.
0342  */
0343 static inline bool SRC_GetSoftwareResetARMCoreDone(SRC_Type *base)
0344 {
0345     return (0U == (base->SCR & SRC_SCR_SWRC_MASK));
0346 }
0347 #endif /* FSL_FEATURE_SRC_HAS_SCR_SWRC */
0348
0349 #if (defined(FSL_FEATURE_SRC_HAS_SCR_EIM_RST) && FSL_FEATURE_SRC_HAS_SCR_EIM_RST)
0350 /*!
0351  * @brief Assert the EIM reset.
0352  *
0353  * EIM reset is needed in order to reconfigure the EIM chip select.
0354  * The software reset bit must de-asserted since this is not self-refresh.
0355  *
0356  * @param base SRC peripheral base address.
0357  * @param enable Make the assertion or not.
0358  */
0359 static inline void SRC_AssertEIMReset(SRC_Type *base, bool enable)
0360 {
0361     if (enable)
0362     {
0363         base->SCR |= SRC_SCR_EIM_RST_MASK;
0364     }
0365     else
0366     {
0367         base->SCR &= ~SRC_SCR_EIM_RST_MASK;
0368     }
0369 }
0370 #endif /* FSL_FEATURE_SRC_HAS_SCR_EIM_RST */
0371
0372 /*!
0373  * @brief Enable the WDOG Reset in SRC.
0374  *
0375  * WDOG Reset is enabled in SRC by default. If the WDOG event to SRC is masked, it would not create
0376  * a reset to the chip. During the time the WDOG event is masked, when the WDOG event flag is
0377  * asserted, it would remain asserted regardless of servicing the WDOG module. The only way to clear
0378  * that bit is the hardware reset.
0379  *
0380  * @param base SRC peripheral base address.
0381  * @param enable Enable the reset or not.
0382  */
0383 static inline void SRC_EnableWDOGReset(SRC_Type *base, bool enable)
0384 {
0385     if (enable) /* WDOG Reset is not masked in SRC (default). */
0386     {
0387         base->SCR = (base->SCR & ~SRC_SCR_MWDR_MASK) | SRC_SCR_MWDR(0xA);
0388     }
0389     else /* WDOG Reset is masked in SRC. */
0390     {
0391         base->SCR = (base->SCR & ~SRC_SCR_MWDR_MASK) | SRC_SCR_MWDR(0x5);
0392     }
0393 }
0394
0395 #if !(defined(FSL_FEATURE_SRC_HAS_NO_SCR_WRBC) && FSL_FEATURE_SRC_HAS_NO_SCR_WRBC)
0396 /*!
0397  * @brief Set the delay count of waiting MMDC's acknowledge.
0398  *
0399  * This function would define the 32KHz clock cycles to count before bypassing the MMDC acknowledge
0400  * for WARM reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD
0401  * reset will be initiated.
0402  *
0403  * @param base SRC peripheral base address.
0404  * @param option The option of setting mode, see to #src_warm_reset_bypass_count_t.
0405  */
0406 static inline void SRC_SetWarmResetBypassCount(SRC_Type *base, src_warm_reset_bypass_count_t option)
0407 {
0408     base->SCR = (base->SCR & ~SRC_SCR_WRBC_MASK) | SRC_SCR_WRBC(option);
0409 }
0410 #endif /* FSL_FEATURE_SRC_HAS_NO_SCR_WRBC */
0411
0412 #if (defined(FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST) && FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST)
0413 /*!
0414  * @brief Enable the lockup reset.
0415  *
0416  * @param base SRC peripheral base address.
0417  * @param enable Enable the reset or not.
0418  */
0419 static inline void SRC_EnableLockupReset(SRC_Type *base, bool enable)
0420 {
0421     if (enable) /* Enable lockup reset. */
0422     {
0423         base->SCR |= SRC_SCR_LOCKUP_RST_MASK;
0424     }
0425     else /* Disable lockup reset. */
0426     {
0427         base->SCR &= ~SRC_SCR_LOCKUP_RST_MASK;
0428     }
0429 }
0430 #endif /* FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST */
0431
0432 #if (defined(FSL_FEATURE_SRC_HAS_SCR_LUEN) && FSL_FEATURE_SRC_HAS_SCR_LUEN)
0433 /*!
0434  * @brief Enable the core lockup reset.
0435  *
0436  * When enable the core luckup reset, the system would be reset when core luckup event happens.
0437  *
0438  * @param base SRC peripheral base address.
0439  * @param enable Enable the reset or not.
0440  */
0441 static inline void SRC_EnableCoreLockupReset(SRC_Type *base, bool enable)
0442 {
0443     if (enable) /* Core lockup will cause system reset. */
0444     {
0445         base->SCR |= SRC_SCR_LUEN_MASK;
0446     }
0447     else /* Core lockup will not cause system reset. */
0448     {
0449         base->SCR &= ~SRC_SCR_LUEN_MASK;
0450     }
0451 }
0452 #endif /* FSL_FEATURE_SRC_HAS_SCR_LUEN */
0453
0454 #if !(defined(FSL_FEATURE_SRC_HAS_NO_SCR_WRE) && FSL_FEATURE_SRC_HAS_NO_SCR_WRE)
0455 /*!
0456  * @brief Enable the WARM reset.
0457  *
0458  * Only when the WARM reset is enabled, the WARM reset requests would be served by WARM reset.
0459  * Otherwise, all the WARM reset sources would generate COLD reset.
0460  *
0461  * @param base SRC peripheral base address.
0462  * @param enable Enable the WARM reset or not.
0463  */
0464 static inline void SRC_EnableWarmReset(SRC_Type *base, bool enable)
0465 {
0466     if (enable)
0467     {
0468         base->SCR |= SRC_SCR_WRE_MASK;
0469     }
0470     else
0471     {
0472         base->SCR &= ~SRC_SCR_WRE_MASK;
0473     }
0474 }
0475 #endif /* FSL_FEATURE_SRC_HAS_NO_SCR_WRE */
0476
0477 #if (defined(FSL_FEATURE_SRC_HAS_SISR) && FSL_FEATURE_SRC_HAS_SISR)
0478 /*!
0479  * @brief Get interrupt status flags.
0480  *
0481  * @param base SRC peripheral base address.
0482  * @return Mask value of status flags. See to $_src_status_flags.
0483  */
0484 static inline uint32_t SRC_GetStatusFlags(SRC_Type *base)
0485 {
0486     return base->SISR;
0487 }
0488 #endif /* FSL_FEATURE_SRC_HAS_SISR */
0489
0490 /*!
0491  * @brief Get the boot mode register 1 value.
0492  *
0493  * The Boot Mode register contains bits that reflect the status of BOOT_CFGx pins of the chip.
0494  * See to chip-specific document for detail information about value.
0495  *
0496  * @param base SRC peripheral base address.
0497  * @return status of BOOT_CFGx pins of the chip.
0498  */
0499 static inline uint32_t SRC_GetBootModeWord1(SRC_Type *base)
0500 {
0501     return base->SBMR1;
0502 }
0503
0504 /*!
0505  * @brief Get the boot mode register 2 value.
0506  *
0507  * The Boot Mode register contains bits that reflect the status of BOOT_MODEx Pins and fuse values
0508  * that controls boot of the chip. See to chip-specific document for detail information about value.
0509  *
0510  * @param base SRC peripheral base address.
0511  * @return status of BOOT_MODEx Pins and fuse values that controls boot of the chip.
0512  */
0513 static inline uint32_t SRC_GetBootModeWord2(SRC_Type *base)
0514 {
0515     return base->SBMR2;
0516 }
0517
0518 #if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI)
0519 /*!
0520  * @brief Set the warm boot indication flag.
0521  *
0522  * WARM boot indication shows that WARM boot was initiated by software. This indicates to the
0523  * software that it saved the needed information in the memory before initiating the WARM reset.
0524  * In this case, software will set this bit to '1', before initiating the WARM reset. The warm_boot
0525  * bit should be used as indication only after a warm_reset sequence. Software should clear this bit
0526  * after warm_reset to indicate that the next warm_reset is not performed with warm_boot.
0527  *
0528  * @param base SRC peripheral base address.
0529  * @param enable Assert the flag or not.
0530  */
0531 static inline void SRC_SetWarmBootIndication(SRC_Type *base, bool enable)
0532 {
0533     if (enable)
0534     {
0535         base->SRSR = (base->SRSR & ~SRC_SRSR_W1C_BITS_MASK) | SRC_SRSR_WBI_MASK;
0536     }
0537     else
0538     {
0539         base->SRSR = (base->SRSR & ~SRC_SRSR_W1C_BITS_MASK) & ~SRC_SRSR_WBI_MASK;
0540     }
0541 }
0542 #endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */
0543
0544 /*!
0545  * @brief Get the status flags of SRC.
0546  *
0547  * @param base SRC peripheral base address.
0548  * @return Mask value of status flags, see to #_src_reset_status_flags.
0549  */
0550 static inline uint32_t SRC_GetResetStatusFlags(SRC_Type *base)
0551 {
0552     return base->SRSR;
0553 }
0554
0555 /*!
0556  * @brief Clear the status flags of SRC.
0557  *
0558  * @param base SRC peripheral base address.
0559  * @param flags value of status flags to be cleared, see to #_src_reset_status_flags.
0560  */
0561 void SRC_ClearResetStatusFlags(SRC_Type *base, uint32_t flags);
0562
0563 /*!
0564  * @brief Set value to general purpose registers.
0565  *
0566  * General purpose registers (GPRx) would hold the value during reset process. Wakeup function could
0567  * be kept in these register. For example, the GPR1 holds the entry function for waking-up from
0568  * Partial SLEEP mode while the GPR2 holds the argument. Other GPRx register would store the
0569  * arbitray values.
0570  *
0571  * @param base SRC peripheral base address.
0572  * @param index The index of GPRx register array. Note index 0 reponses the GPR1 register.
0573  * @param value Setting value for GPRx register.
0574  */
0575 static inline void SRC_SetGeneralPurposeRegister(SRC_Type *base, uint32_t index, uint32_t value)
0576 {
0577     assert(index < SRC_GPR_COUNT);
0578
0579     base->GPR[index] = value;
0580 }
0581
0582 /*!
0583  * @brief Get the value from general purpose registers.
0584  *
0585  * @param base SRC peripheral base address.
0586  * @param index The index of GPRx register array. Note index 0 reponses the GPR1 register.
0587  * @return The setting value for GPRx register.
0588  */
0589 static inline uint32_t SRC_GetGeneralPurposeRegister(SRC_Type *base, uint32_t index)
0590 {
0591     assert(index < SRC_GPR_COUNT);
0592
0593     return base->GPR[index];
0594 }
0595
0596 #if defined(__cplusplus)
0597 }
0598 #endif
0599 /*!
0600  * @}
0601  */
0602 #endif /* _FSL_SRC_H_ */