LXR |
|
|
|
|||
File indexing completed on 2025-05-11 08:23:01
0001 /* 0002 * Copyright 2017-2022 NXP 0003 * All rights reserved. 0004 * 0005 * SPDX-License-Identifier: BSD-3-Clause 0006 */ 0007 #ifndef _FSL_SEMC_H_ 0008 #define _FSL_SEMC_H_ 0009 0010 #include "fsl_common.h" 0011 0012 /*! 0013 * @addtogroup semc 0014 * @{ 0015 */ 0016 0017 /******************************************************************************* 0018 * Definitions 0019 ******************************************************************************/ 0020 0021 /*! @name Driver version */ 0022 /*@{*/ 0023 /*! @brief SEMC driver version. */ 0024 #define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 4, 3)) 0025 /*@}*/ 0026 0027 /*! @brief SEMC status, _semc_status. */ 0028 enum 0029 { 0030 kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), /*!< Invalid device type. */ 0031 kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), /*!< IP command execution error. */ 0032 kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), /*!< AXI command execution error. */ 0033 kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), /*!< Invalid memory sie. */ 0034 kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), /*!< Invalid IP command data size. */ 0035 kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), /*!< Invalid address port width. */ 0036 kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), /*!< Invalid data port width. */ 0037 kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), /*!< Invalid SW pinmux selection. */ 0038 kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), /*!< Invalid burst length */ 0039 /*! Invalid column address bit width. */ 0040 kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9), 0041 kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), /*!< Invalid base address. */ 0042 kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), /*!< Invalid timer setting. */ 0043 }; 0044 0045 /*! @brief SEMC memory device type. */ 0046 typedef enum _semc_mem_type 0047 { 0048 kSEMC_MemType_SDRAM = 0, /*!< SDRAM */ 0049 kSEMC_MemType_SRAM, /*!< SRAM */ 0050 kSEMC_MemType_NOR, /*!< NOR */ 0051 kSEMC_MemType_NAND, /*!< NAND */ 0052 kSEMC_MemType_8080 /*!< 8080. */ 0053 } semc_mem_type_t; 0054 0055 /*! @brief SEMC WAIT/RDY polarity. */ 0056 typedef enum _semc_waitready_polarity 0057 { 0058 kSEMC_LowActive = 0, /*!< Low active. */ 0059 kSEMC_HighActive, /*!< High active. */ 0060 } semc_waitready_polarity_t; 0061 0062 /*! @brief SEMC SDRAM Chip selection . */ 0063 typedef enum _semc_sdram_cs 0064 { 0065 kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */ 0066 kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */ 0067 kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */ 0068 kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */ 0069 } semc_sdram_cs_t; 0070 0071 /*! @brief SEMC SRAM Chip selection . */ 0072 typedef enum _semc_sram_cs 0073 { 0074 #if defined(FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT) && (FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT == 0x04U) 0075 kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */ 0076 kSEMC_SRAM_CS1, /*!< SEMC SRAM CS1. */ 0077 kSEMC_SRAM_CS2, /*!< SEMC SRAM CS2. */ 0078 kSEMC_SRAM_CS3 /*!< SEMC SRAM CS3. */ 0079 #else 0080 kSEMC_SRAM_CS0 = 0, /*!< SEMC SRAM CS0. */ 0081 #endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */ 0082 } semc_sram_cs_t; 0083 0084 /*! @brief SEMC NAND device type. */ 0085 typedef enum _semc_nand_access_type 0086 { 0087 kSEMC_NAND_ACCESS_BY_AXI = 0, /*!< Access to NAND flash by AXI bus. */ 0088 kSEMC_NAND_ACCESS_BY_IPCMD, /*!< Access to NAND flash by IP bus. */ 0089 } semc_nand_access_type_t; 0090 0091 /*! @brief SEMC interrupts . */ 0092 typedef enum _semc_interrupt_enable 0093 { 0094 kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */ 0095 kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */ 0096 kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */ 0097 kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */ 0098 } semc_interrupt_enable_t; 0099 0100 /*! @brief SEMC IP command data size in bytes. */ 0101 typedef enum _semc_ipcmd_datasize 0102 { 0103 kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */ 0104 kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */ 0105 kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */ 0106 kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */ 0107 } semc_ipcmd_datasize_t; 0108 0109 /*! @brief SEMC auto-refresh timing. */ 0110 typedef enum _semc_refresh_time 0111 { 0112 kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */ 0113 kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */ 0114 kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */ 0115 } semc_refresh_time_t; 0116 0117 /*! @brief CAS latency */ 0118 typedef enum _semc_caslatency 0119 { 0120 kSEMC_LatencyOne = 1, /*!< Latency 1. */ 0121 kSEMC_LatencyTwo, /*!< Latency 2. */ 0122 kSEMC_LatencyThree, /*!< Latency 3. */ 0123 } semc_caslatency_t; 0124 0125 /*! @brief SEMC sdram column address bit number. */ 0126 typedef enum _semc_sdram_column_bit_num 0127 { 0128 kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */ 0129 kSEMC_SdramColunm_11bit, /*!< 11 bit. */ 0130 kSEMC_SdramColunm_10bit, /*!< 10 bit. */ 0131 kSEMC_SdramColunm_9bit, /*!< 9 bit. */ 0132 #if defined(FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT) && (FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT) 0133 kSEMC_SdramColunm_8bit, /*!< 8 bit. */ 0134 #endif /* FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT */ 0135 } semc_sdram_column_bit_num_t; 0136 0137 /*! @brief SEMC sdram burst length. */ 0138 typedef enum _semc_sdram_burst_len 0139 { 0140 /*! According to ERR050577, Auto-refresh command may possibly fail to be triggered during 0141 long time back-to-back write (or read) when SDRAM controller's burst length is greater than 1. */ 0142 #if defined(FSL_FEATURE_SEMC_ERRATA_050577) && (FSL_FEATURE_SEMC_ERRATA_050577 == 0x01U) 0143 kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/ 0144 #else 0145 kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/ 0146 kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/ 0147 kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/ 0148 kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/ 0149 #endif /* FSL_FEATURE_SEMC_ERRATA_050577 */ 0150 } sem_sdram_burst_len_t; 0151 0152 /*! @brief SEMC nand column address bit number. */ 0153 typedef enum _semc_nand_column_bit_num 0154 { 0155 kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */ 0156 kSEMC_NandColum_15bit, /*!< 15 bit. */ 0157 kSEMC_NandColum_14bit, /*!< 14 bit. */ 0158 kSEMC_NandColum_13bit, /*!< 13 bit. */ 0159 kSEMC_NandColum_12bit, /*!< 12 bit. */ 0160 kSEMC_NandColum_11bit, /*!< 11 bit. */ 0161 kSEMC_NandColum_10bit, /*!< 10 bit. */ 0162 kSEMC_NandColum_9bit, /*!< 9 bit. */ 0163 } semc_nand_column_bit_num_t; 0164 0165 /*! @brief SEMC nand burst length. */ 0166 typedef enum _semc_nand_burst_len 0167 { 0168 kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/ 0169 kSEMC_Nand_BurstLen2, /*!< Burst length 2*/ 0170 kSEMC_Nand_BurstLen4, /*!< Burst length 4*/ 0171 kSEMC_Nand_BurstLen8, /*!< Burst length 8*/ 0172 kSEMC_Nand_BurstLen16, /*!< Burst length 16*/ 0173 kSEMC_Nand_BurstLen32, /*!< Burst length 32*/ 0174 kSEMC_Nand_BurstLen64 /*!< Burst length 64*/ 0175 } sem_nand_burst_len_t; 0176 0177 /*! @brief SEMC nor/sram column address bit number. */ 0178 typedef enum _semc_norsram_column_bit_num 0179 { 0180 kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */ 0181 kSEMC_NorColum_11bit, /*!< 11 bit. */ 0182 kSEMC_NorColum_10bit, /*!< 10 bit. */ 0183 kSEMC_NorColum_9bit, /*!< 9 bit. */ 0184 kSEMC_NorColum_8bit, /*!< 8 bit. */ 0185 kSEMC_NorColum_7bit, /*!< 7 bit. */ 0186 kSEMC_NorColum_6bit, /*!< 6 bit. */ 0187 kSEMC_NorColum_5bit, /*!< 5 bit. */ 0188 kSEMC_NorColum_4bit, /*!< 4 bit. */ 0189 kSEMC_NorColum_3bit, /*!< 3 bit. */ 0190 kSEMC_NorColum_2bit /*!< 2 bit. */ 0191 } semc_norsram_column_bit_num_t; 0192 0193 /*! @brief SEMC nor/sram burst length. */ 0194 typedef enum _semc_norsram_burst_len 0195 { 0196 kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/ 0197 kSEMC_Nor_BurstLen2, /*!< Burst length 2*/ 0198 kSEMC_Nor_BurstLen4, /*!< Burst length 4*/ 0199 kSEMC_Nor_BurstLen8, /*!< Burst length 8*/ 0200 kSEMC_Nor_BurstLen16, /*!< Burst length 16*/ 0201 kSEMC_Nor_BurstLen32, /*!< Burst length 32*/ 0202 kSEMC_Nor_BurstLen64 /*!< Burst length 64*/ 0203 } sem_norsram_burst_len_t; 0204 0205 /*! @brief SEMC dbi column address bit number. */ 0206 typedef enum _semc_dbi_column_bit_num 0207 { 0208 kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */ 0209 kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */ 0210 kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */ 0211 kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */ 0212 kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */ 0213 kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */ 0214 kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */ 0215 kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */ 0216 kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */ 0217 kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */ 0218 kSEMC_Dbi_Colum_2bit /*!< 2 bit. */ 0219 } semc_dbi_column_bit_num_t; 0220 0221 /*! @brief SEMC dbi burst length. */ 0222 typedef enum _semc_dbi_burst_len 0223 { 0224 kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/ 0225 kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/ 0226 kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/ 0227 kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/ 0228 kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/ 0229 kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/ 0230 kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/ 0231 } sem_dbi_burst_len_t; 0232 0233 /*! @brief SEMC IOMUXC. */ 0234 typedef enum _semc_iomux_pin 0235 { 0236 kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */ 0237 kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */ 0238 kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/ 0239 kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */ 0240 kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ 0241 kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ 0242 } semc_iomux_pin; 0243 0244 /*! @brief SEMC NOR/PSRAM Address bit 27 A27. */ 0245 typedef enum _semc_iomux_nora27_pin 0246 { 0247 kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */ 0248 kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ 0249 kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ 0250 } semc_iomux_nora27_pin; 0251 0252 /*! @brief SEMC port size. */ 0253 typedef enum _semc_port_size 0254 { 0255 kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */ 0256 kSEMC_PortSize16Bit, /*!< 16-Bit port size. */ 0257 #if defined(FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH) && (FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH == 0x02U) 0258 kSEMC_PortSize32Bit /*!< 32-Bit port size. */ 0259 #endif /* FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH */ 0260 } smec_port_size_t; 0261 0262 /*! @brief SEMC address mode. */ 0263 typedef enum _semc_addr_mode 0264 { 0265 kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */ 0266 kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */ 0267 kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */ 0268 } semc_addr_mode_t; 0269 0270 /*! @brief SEMC DQS read strobe mode. */ 0271 typedef enum _semc_dqs_mode 0272 { 0273 kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */ 0274 kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */ 0275 } semc_dqs_mode_t; 0276 0277 /*! @brief SEMC ADV signal active polarity. */ 0278 typedef enum _semc_adv_polarity 0279 { 0280 kSEMC_AdvActiveLow = 0, /*!< Adv active low. */ 0281 kSEMC_AdvActiveHigh, /*!< Adv active high. */ 0282 } semc_adv_polarity_t; 0283 0284 /*! @brief SEMC sync mode. */ 0285 typedef enum _semc_sync_mode 0286 { 0287 kSEMC_AsyncMode = 0, /*!< Async mode. */ 0288 kSEMC_SyncMode, /*!< Sync mode. */ 0289 } semc_sync_mode_t; 0290 0291 /*! @brief SEMC ADV signal level control. */ 0292 typedef enum _semc_adv_level_control 0293 { 0294 kSEMC_AdvHigh = 0, /*!< Adv is high during address hold state. */ 0295 kSEMC_AdvLow, /*!< Adv is low during address hold state. */ 0296 } semc_adv_level_control_t; 0297 0298 /*! @brief SEMC RDY signal active polarity. */ 0299 typedef enum _semc_rdy_polarity 0300 { 0301 kSEMC_RdyActiveLow = 0, /*!< Adv active low. */ 0302 kSEMC_RdyActivehigh, /*!< Adv active low. */ 0303 } semc_rdy_polarity_t; 0304 0305 /*! @brief SEMC IP command for NAND: address mode. */ 0306 typedef enum _semc_ipcmd_nand_addrmode 0307 { 0308 kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */ 0309 kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */ 0310 kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */ 0311 kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */ 0312 kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */ 0313 kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */ 0314 } semc_ipcmd_nand_addrmode_t; 0315 0316 /*! @brief SEMC IP command for NAND： command mode. */ 0317 typedef enum _semc_ipcmd_nand_cmdmode 0318 { 0319 kSEMC_NANDCM_Command = 0x2U, /*!< command. */ 0320 kSEMC_NANDCM_CommandHold, /*!< Command hold. */ 0321 kSEMC_NANDCM_CommandAddress, /*!< Command address. */ 0322 kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */ 0323 kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */ 0324 kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */ 0325 kSEMC_NANDCM_CommandRead, /*!< Command read. */ 0326 kSEMC_NANDCM_CommandWrite, /*!< Command write. */ 0327 kSEMC_NANDCM_Read, /*!< Read. */ 0328 kSEMC_NANDCM_Write /*!< Write. */ 0329 } semc_ipcmd_nand_cmdmode_t; 0330 0331 /*! @brief SEMC NAND address option. */ 0332 typedef enum _semc_nand_address_option 0333 { 0334 kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */ 0335 kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */ 0336 kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */ 0337 kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */ 0338 kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */ 0339 kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */ 0340 } semc_nand_address_option_t; 0341 0342 /*! @brief SEMC IP command for NOR. */ 0343 typedef enum _semc_ipcmd_nor_dbi 0344 { 0345 kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */ 0346 kSEMC_NORDBICM_Write /*!< NOR write. */ 0347 } semc_ipcmd_nor_dbi_t; 0348 0349 /*! @brief SEMC IP command for SRAM. */ 0350 typedef enum _semc_ipcmd_sram 0351 { 0352 kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */ 0353 kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */ 0354 kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */ 0355 kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */ 0356 } semc_ipcmd_sram_t; 0357 0358 /*! @brief SEMC IP command for SDARM. */ 0359 typedef enum _semc_ipcmd_sdram 0360 { 0361 kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */ 0362 kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */ 0363 kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */ 0364 kSEMC_SDRAMCM_Active, /*!< SDRAM active. */ 0365 kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */ 0366 kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */ 0367 kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */ 0368 kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */ 0369 } semc_ipcmd_sdram_t; 0370 0371 /*! @brief SEMC SDRAM configuration structure. 0372 * 0373 * 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes 0374 * should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. 0375 * Take refer to BR0~BR3 register in RM for details. 0376 * 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, 0377 * it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, 0378 * The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. 0379 * idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are 0380 * similar to prescalePeriod_N16Cycle. 0381 * 0382 */ 0383 typedef struct _semc_sdram_config 0384 { 0385 semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */ 0386 uint32_t address; /*!< The base address. */ 0387 uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ 0388 smec_port_size_t portSize; /*!< Port size. */ 0389 sem_sdram_burst_len_t burstLen; /*!< Burst length. */ 0390 semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ 0391 semc_caslatency_t casLatency; /*!< CAS latency. */ 0392 uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */ 0393 uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */ 0394 uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */ 0395 uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */ 0396 uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */ 0397 uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */ 0398 uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */ 0399 uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */ 0400 uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */ 0401 uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */ 0402 uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */ 0403 uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */ 0404 uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */ 0405 uint8_t refreshBurstLen; /*!< Refresh burst length. */ 0406 #if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) 0407 uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than 0408 read data. */ 0409 #endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */ 0410 } semc_sdram_config_t; 0411 0412 /*! @brief SEMC NAND device timing configuration structure. */ 0413 typedef struct _semc_nand_timing_config 0414 { 0415 uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */ 0416 uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */ 0417 uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */ 0418 uint8_t tWeLow_Ns; /*!< WE low time: tWP. */ 0419 uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */ 0420 uint8_t tReLow_Ns; /*!< RE low time: tRP. */ 0421 uint8_t tReHigh_Ns; /*!< RE high time: tREH. */ 0422 uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */ 0423 uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */ 0424 uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */ 0425 uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */ 0426 uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */ 0427 uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */ 0428 } semc_nand_timing_config_t; 0429 0430 /*! @brief SEMC NAND configuration structure. */ 0431 typedef struct _semc_nand_config 0432 { 0433 semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */ 0434 uint32_t axiAddress; /*!< The base address for AXI nand. */ 0435 uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */ 0436 uint32_t ipgAddress; /*!< The base address for IPG nand . */ 0437 uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */ 0438 semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ 0439 bool edoModeEnabled; /*!< EDO mode enabled. */ 0440 semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ 0441 semc_nand_address_option_t arrayAddrOption; /*!< Address option. */ 0442 sem_nand_burst_len_t burstLen; /*!< Burst length. */ 0443 smec_port_size_t portSize; /*!< Port size. */ 0444 semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */ 0445 } semc_nand_config_t; 0446 0447 /*! @brief SEMC NOR configuration structure. */ 0448 typedef struct _semc_nor_config 0449 { 0450 semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ 0451 semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ 0452 uint32_t address; /*!< The base address. */ 0453 uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ 0454 uint8_t addrPortWidth; /*!< The address port width. */ 0455 semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ 0456 semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */ 0457 semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ 0458 semc_addr_mode_t addrMode; /*!< Address mode. */ 0459 sem_norsram_burst_len_t burstLen; /*!< Burst length. */ 0460 smec_port_size_t portSize; /*!< Port size. */ 0461 uint8_t tCeSetup_Ns; /*!< The CE setup time. */ 0462 uint8_t tCeHold_Ns; /*!< The CE hold time. */ 0463 uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ 0464 uint8_t tAddrSetup_Ns; /*!< The address setup time. */ 0465 uint8_t tAddrHold_Ns; /*!< The address hold time. */ 0466 uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ 0467 uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ 0468 uint8_t tReLow_Ns; /*!< RE low time for async mode. */ 0469 uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ 0470 uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ 0471 uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ 0472 #if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) 0473 uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ 0474 #endif 0475 #if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) 0476 uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ 0477 #endif 0478 #if defined(FSL_FEATURE_SEMC_HAS_NOR_LC_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_LC_TIME) 0479 uint8_t latencyCount; /*!< Latency count for sync mode. */ 0480 #endif 0481 #if defined(FSL_FEATURE_SEMC_HAS_NOR_RD_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_RD_TIME) 0482 uint8_t readCycle; /*!< Read cycle time for sync mode. */ 0483 #endif 0484 #if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) 0485 uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than 0486 read data. */ 0487 #endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */ 0488 } semc_nor_config_t; 0489 0490 /*! @brief SEMC SRAM configuration structure. */ 0491 typedef struct _semc_sram_config 0492 { 0493 semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ 0494 semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ 0495 uint32_t address; /*!< The base address. */ 0496 uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ 0497 uint8_t addrPortWidth; /*!< The address port width. */ 0498 semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */ 0499 semc_addr_mode_t addrMode; /*!< Address mode. */ 0500 sem_norsram_burst_len_t burstLen; /*!< Burst length. */ 0501 smec_port_size_t portSize; /*!< Port size. */ 0502 #if defined(SEMC_SRAMCR4_SYNCEN_MASK) && (SEMC_SRAMCR4_SYNCEN_MASK) 0503 semc_sync_mode_t syncMode; /*!< Sync mode. */ 0504 #endif /* SEMC_SRAMCR4_SYNCEN_MASK */ 0505 #if defined(SEMC_SRAMCR0_WAITEN_MASK) && (SEMC_SRAMCR0_WAITEN_MASK) 0506 bool waitEnable; /*!< Wait enable. */ 0507 #endif /* SEMC_SRAMCR0_WAITEN_MASK */ 0508 #if defined(SEMC_SRAMCR0_WAITSP_MASK) && (SEMC_SRAMCR0_WAITSP_MASK) 0509 uint8_t waitSample; /*!< Wait sample. */ 0510 #endif /* SEMC_SRAMCR0_WAITSP_MASK */ 0511 #if defined(SEMC_SRAMCR4_ADVH_MASK) && (SEMC_SRAMCR4_ADVH_MASK) 0512 semc_adv_level_control_t advLevelCtrl; /*!< ADV# level control during address hold state, 1: low, 0: high. */ 0513 #endif /* SEMC_SRAMCR4_ADVH_MASK */ 0514 uint8_t tCeSetup_Ns; /*!< The CE setup time. */ 0515 uint8_t tCeHold_Ns; /*!< The CE hold time. */ 0516 uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ 0517 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME) 0518 uint8_t readHoldTime_Ns; /*!< read hold time. */ 0519 #endif /* FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME */ 0520 uint8_t tAddrSetup_Ns; /*!< The address setup time. */ 0521 uint8_t tAddrHold_Ns; /*!< The address hold time. */ 0522 uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ 0523 uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ 0524 uint8_t tReLow_Ns; /*!< RE low time for async mode. */ 0525 uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ 0526 uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ 0527 uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ 0528 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_WDS_TIME) 0529 uint8_t tWriteSetup_Ns; /*!<Write data setup time for sync mode. */ 0530 #endif 0531 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_WDH_TIME) 0532 uint8_t tWriteHold_Ns; /*!<Write hold time for sync mode. */ 0533 #endif 0534 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_LC_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_LC_TIME) 0535 uint8_t latencyCount; /*!<Latency count for sync mode. */ 0536 #endif 0537 #if defined(FSL_FEATURE_SEMC_HAS_SRAM_RD_TIME) && (FSL_FEATURE_SEMC_HAS_SRAM_RD_TIME) 0538 uint8_t readCycle; /*!<Read cycle time for sync mode. */ 0539 #endif 0540 #if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) 0541 uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than 0542 read data. */ 0543 #endif /* FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL */ 0544 } semc_sram_config_t; 0545 0546 /*! @brief SEMC DBI configuration structure. */ 0547 typedef struct _semc_dbi_config 0548 { 0549 semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */ 0550 uint32_t address; /*!< The base address. */ 0551 uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */ 0552 semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ 0553 sem_dbi_burst_len_t burstLen; /*!< Burst length. */ 0554 smec_port_size_t portSize; /*!< Port size. */ 0555 uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */ 0556 uint8_t tCsxHold_Ns; /*!< The CSX hold time. */ 0557 uint8_t tWexLow_Ns; /*!< WEX low time. */ 0558 uint8_t tWexHigh_Ns; /*!< WEX high time. */ 0559 uint8_t tRdxLow_Ns; /*!< RDX low time. */ 0560 uint8_t tRdxHigh_Ns; /*!< RDX high time. */ 0561 uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/ 0562 } semc_dbi_config_t; 0563 0564 /*! @brief SEMC AXI queue a weight setting structure. */ 0565 typedef struct _semc_queuea_weight_struct 0566 { 0567 uint32_t qos : 4; /*!< weight of qos for queue 0 . */ 0568 uint32_t aging : 4; /*!< weight of aging for queue 0.*/ 0569 uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/ 0570 uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/ 0571 } semc_queuea_weight_struct_t; 0572 0573 /*! @brief SEMC AXI queue a weight setting union. */ 0574 typedef union _semc_queuea_weight 0575 { 0576 semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */ 0577 uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */ 0578 } semc_queuea_weight_t; 0579 0580 /*! @brief SEMC AXI queue b weight setting structure. */ 0581 typedef struct _semc_queueb_weight_struct 0582 { 0583 uint32_t qos : 4; /*!< weight of qos for queue 1. */ 0584 uint32_t aging : 4; /*!< weight of aging for queue 1.*/ 0585 uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/ 0586 uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/ 0587 uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/ 0588 } semc_queueb_weight_struct_t; 0589 0590 /*! @brief SEMC AXI queue b weight setting union. */ 0591 typedef union _semc_queueb_weight 0592 { 0593 semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */ 0594 uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */ 0595 } semc_queueb_weight_t; 0596 0597 /*! @brief SEMC AXI queue weight setting. */ 0598 typedef struct _semc_axi_queueweight 0599 { 0600 bool queueaEnable; /*!< Enable queue a. */ 0601 semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */ 0602 bool queuebEnable; /*!< Enable queue b. */ 0603 semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */ 0604 } semc_axi_queueweight_t; 0605 0606 /*! 0607 * @brief SEMC configuration structure. 0608 * 0609 * busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is 0610 * 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. 0611 * cmdTimeoutCycles: is used for command execution timeout cycles. it's 0612 * similar to the busTimeoutCycles. 0613 */ 0614 typedef struct _semc_config_t 0615 { 0616 semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */ 0617 uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */ 0618 uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */ 0619 semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */ 0620 } semc_config_t; 0621 0622 /******************************************************************************* 0623 * API 0624 ******************************************************************************/ 0625 0626 #if defined(__cplusplus) 0627 extern "C" { 0628 #endif 0629 0630 /*! 0631 * @name SEMC Initialization and De-initialization 0632 * @{ 0633 */ 0634 0635 /*! 0636 * @brief Gets the SEMC default basic configuration structure. 0637 * 0638 * The purpose of this API is to get the default SEMC 0639 * configure structure for SEMC_Init(). User may use the initialized 0640 * structure unchanged in SEMC_Init(), or modify some fields of the 0641 * structure before calling SEMC_Init(). 0642 * Example: 0643 @code 0644 semc_config_t config; 0645 SEMC_GetDefaultConfig(&config); 0646 @endcode 0647 * @param config The SEMC configuration structure pointer. 0648 */ 0649 void SEMC_GetDefaultConfig(semc_config_t *config); 0650 0651 /*! 0652 * @brief Initializes SEMC. 0653 * This function ungates the SEMC clock and initializes SEMC. 0654 * This function must be called before calling any other SEMC driver functions. 0655 * 0656 * @param base SEMC peripheral base address. 0657 * @param configure The SEMC configuration structure pointer. 0658 */ 0659 void SEMC_Init(SEMC_Type *base, semc_config_t *configure); 0660 0661 /*! 0662 * @brief Deinitializes the SEMC module and gates the clock. 0663 * 0664 * This function gates the SEMC clock. As a result, the SEMC module doesn't work after 0665 * calling this function, for some IDE, calling this API may cause the next downloading 0666 * operation failed. so, please call this API cautiously. Additional, users can 0667 * using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control 0668 * operation in drivers. 0669 * 0670 * @param base SEMC peripheral base address. 0671 */ 0672 void SEMC_Deinit(SEMC_Type *base); 0673 0674 /* @} */ 0675 0676 /*! 0677 * @name SEMC Configuration Operation For Each Memory Type 0678 * @{ 0679 */ 0680 0681 /*! 0682 * @brief Configures SDRAM controller in SEMC. 0683 * 0684 * @param base SEMC peripheral base address. 0685 * @param cs The chip selection. 0686 * @param config The sdram configuration. 0687 * @param clkSrc_Hz The SEMC clock frequency. 0688 */ 0689 status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz); 0690 0691 /*! 0692 * @brief Configures NAND controller in SEMC. 0693 * 0694 * @param base SEMC peripheral base address. 0695 * @param config The nand configuration. 0696 * @param clkSrc_Hz The SEMC clock frequency. 0697 */ 0698 status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz); 0699 0700 /*! 0701 * @brief Configures NOR controller in SEMC. 0702 * 0703 * @param base SEMC peripheral base address. 0704 * @param config The nor configuration. 0705 * @param clkSrc_Hz The SEMC clock frequency. 0706 */ 0707 status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz); 0708 0709 /*! 0710 * @brief Configures SRAM controller in SEMC. 0711 * 0712 * @param base SEMC peripheral base address. 0713 * @param cs The chip selection. 0714 * @param config The sram configuration. 0715 * @param clkSrc_Hz The SEMC clock frequency. 0716 */ 0717 status_t SEMC_ConfigureSRAMWithChipSelection(SEMC_Type *base, 0718 semc_sram_cs_t cs, 0719 semc_sram_config_t *config, 0720 uint32_t clkSrc_Hz); 0721 0722 /*! 0723 * @brief Configures SRAM controller in SEMC. 0724 * @deprecated Do not use this function. It has been superceded by @ref SEMC_ConfigureSRAMWithChipSelection. 0725 * @param base SEMC peripheral base address. 0726 * @param config The sram configuration. 0727 * @param clkSrc_Hz The SEMC clock frequency. 0728 */ 0729 status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz); 0730 0731 /*! 0732 * @brief Configures DBI controller in SEMC. 0733 * 0734 * @param base SEMC peripheral base address. 0735 * @param config The dbi configuration. 0736 * @param clkSrc_Hz The SEMC clock frequency. 0737 */ 0738 status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz); 0739 0740 /* @} */ 0741 0742 /*! 0743 * @name SEMC Interrupt Operation 0744 * @{ 0745 */ 0746 0747 /*! 0748 * @brief Enables the SEMC interrupt. 0749 * 0750 * This function enables the SEMC interrupts according to the provided mask. The mask 0751 * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. 0752 * For example, to enable the IP command done and error interrupt, do the following. 0753 * @code 0754 * SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); 0755 * @endcode 0756 * 0757 * @param base SEMC peripheral base address. 0758 * @param mask SEMC interrupts to enable. This is a logical OR of the 0759 * enumeration :: semc_interrupt_enable_t. 0760 */ 0761 static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask) 0762 { 0763 base->INTEN |= mask; 0764 } 0765 0766 /*! 0767 * @brief Disables the SEMC interrupt. 0768 * 0769 * This function disables the SEMC interrupts according to the provided mask. The mask 0770 * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. 0771 * For example, to disable the IP command done and error interrupt, do the following. 0772 * @code 0773 * SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); 0774 * @endcode 0775 * 0776 * @param base SEMC peripheral base address. 0777 * @param mask SEMC interrupts to disable. This is a logical OR of the 0778 * enumeration :: semc_interrupt_enable_t. 0779 */ 0780 static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask) 0781 { 0782 base->INTEN &= ~mask; 0783 } 0784 0785 /*! 0786 * @brief Gets the SEMC status. 0787 * 0788 * This function gets the SEMC interrupts event status. 0789 * User can use the a logical OR of enumeration member as a mask. 0790 * See @ref semc_interrupt_enable_t. 0791 * 0792 * @param base SEMC peripheral base address. 0793 * @return status flag, use status flag in semc_interrupt_enable_t to get the related status. 0794 */ 0795 static inline bool SEMC_GetStatusFlag(SEMC_Type *base) 0796 { 0797 return (base->INTR != 0x00U) ? true : false; 0798 } 0799 0800 /*! 0801 * @brief Clears the SEMC status flag state. 0802 * 0803 * The following status register flags can be cleared SEMC interrupt status. 0804 * 0805 * @param base SEMC base pointer 0806 * @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t. 0807 */ 0808 static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask) 0809 { 0810 base->INTR |= mask; 0811 } 0812 0813 /* @} */ 0814 0815 /*! 0816 * @name SEMC Memory Access Operation 0817 * @{ 0818 */ 0819 0820 /*! 0821 * @brief Check if SEMC is in idle. 0822 * 0823 * @param base SEMC peripheral base address. 0824 * @return True SEMC is in idle, false is not in idle. 0825 */ 0826 static inline bool SEMC_IsInIdle(SEMC_Type *base) 0827 { 0828 return ((base->STS0 & SEMC_STS0_IDLE_MASK) != 0x00U) ? true : false; 0829 } 0830 0831 /*! 0832 * @brief SEMC IP command access. 0833 * 0834 * @param base SEMC peripheral base address. 0835 * @param memType SEMC memory type. refer to "semc_mem_type_t" 0836 * @param address SEMC device address. 0837 * @param command SEMC IP command. 0838 * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. 0839 * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". 0840 * For SRAM device, take refer to "semc_ipcmd_sram_t". 0841 * For SDRAM device, take refer to "semc_ipcmd_sdram_t". 0842 * @param write Data for write access. 0843 * @param read Data pointer for read data out. 0844 */ 0845 status_t SEMC_SendIPCommand( 0846 SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read); 0847 0848 /*! 0849 * @brief Build SEMC IP command for NAND. 0850 * 0851 * This function build SEMC NAND IP command. The command is build of user command code, 0852 * SEMC address mode and SEMC command mode. 0853 * 0854 * @param userCommand NAND device normal command. 0855 * @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t". 0856 * @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t". 0857 */ 0858 static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand, 0859 semc_ipcmd_nand_addrmode_t addrMode, 0860 semc_ipcmd_nand_cmdmode_t cmdMode) 0861 { 0862 return ((uint16_t)userCommand << 8U) | ((uint16_t)addrMode << 4U) | ((uint16_t)cmdMode & 0x000FU); 0863 } 0864 0865 /*! 0866 * @brief Check if the NAND device is ready. 0867 * 0868 * @param base SEMC peripheral base address. 0869 * @return True NAND is ready, false NAND is not ready. 0870 */ 0871 static inline bool SEMC_IsNandReady(SEMC_Type *base) 0872 { 0873 return ((base->STS0 & SEMC_STS0_NARDY_MASK) != 0x00U) ? true : false; 0874 } 0875 0876 /*! 0877 * @brief SEMC NAND device memory write through IP command. 0878 * 0879 * @param base SEMC peripheral base address. 0880 * @param address SEMC NAND device address. 0881 * @param data Data for write access. 0882 * @param size_bytes Data length. 0883 */ 0884 status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); 0885 0886 /*! 0887 * @brief SEMC NAND device memory read through IP command. 0888 * 0889 * @param base SEMC peripheral base address. 0890 * @param address SEMC NAND device address. 0891 * @param data Data pointer for data read out. 0892 * @param size_bytes Data length. 0893 */ 0894 status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); 0895 0896 /*! 0897 * @brief SEMC NOR device memory write through IP command. 0898 * 0899 * @param base SEMC peripheral base address. 0900 * @param address SEMC NOR device address. 0901 * @param data Data for write access. 0902 * @param size_bytes Data length. 0903 */ 0904 status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); 0905 0906 /*! 0907 * @brief SEMC NOR device memory read through IP command. 0908 * 0909 * @param base SEMC peripheral base address. 0910 * @param address SEMC NOR device address. 0911 * @param data Data pointer for data read out. 0912 * @param size_bytes Data length. 0913 */ 0914 status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); 0915 0916 /* @} */ 0917 0918 #if defined(__cplusplus) 0919 } 0920 #endif 0921 0922 /*! @}*/ 0923 0924 #endif /* _FSL_SEMC_H_*/
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.3.7 LXR engine. The LXR team |
|