drivers/rdc_sema42/fsl_rdc_sema42.c

0001 /*
0002  * Copyright 2017-2020, 2022 NXP
0003  * All rights reserved.
0004  *
0005  * SPDX-License-Identifier: BSD-3-Clause
0006  */
0007
0008 #include "fsl_rdc_sema42.h"
0009
0010 /******************************************************************************
0011  * Definitions
0012  *****************************************************************************/
0013
0014 /* Component ID definition, used by tools. */
0015 #ifndef FSL_COMPONENT_ID
0016 #define FSL_COMPONENT_ID "platform.drivers.rdc_sema42"
0017 #endif
0018
0019 /* The first number write to RSTGDP when reset RDC_SEMA42 gate. */
0020 #define RDC_SEMA42_GATE_RESET_PATTERN_1 (0xE2U)
0021 /* The second number write to RSTGDP when reset RDC_SEMA42 gate. */
0022 #define RDC_SEMA42_GATE_RESET_PATTERN_2 (0x1DU)
0023
0024 #if !defined(RDC_SEMAPHORE_GATE_COUNT)
0025 /* Compatible remap. */
0026 #define RDC_SEMAPHORE_GATE_LDOM(x)    RDC_SEMAPHORE_GATE0_LDOM(x)
0027 #define RDC_SEMAPHORE_GATE_GTFSM(x)   RDC_SEMAPHORE_GATE0_GTFSM(x)
0028 #define RDC_SEMAPHORE_GATE_LDOM_MASK  RDC_SEMAPHORE_GATE0_LDOM_MASK
0029 #define RDC_SEMAPHORE_GATE_LDOM_SHIFT RDC_SEMAPHORE_GATE0_LDOM_SHIFT
0030 #endif
0031
0032 /*******************************************************************************
0033  * Prototypes
0034  ******************************************************************************/
0035
0036 /*!
0037  * @brief Get instance number for RDC_SEMA42 module.
0038  *
0039  * @param base RDC_SEMA42 peripheral base address.
0040  */
0041 uint32_t RDC_SEMA42_GetInstance(RDC_SEMAPHORE_Type *base);
0042
0043 /*******************************************************************************
0044  * Variables
0045  ******************************************************************************/
0046
0047 /*! @brief Pointers to sema42 bases for each instance. */
0048 static RDC_SEMAPHORE_Type *const s_sema42Bases[] = RDC_SEMAPHORE_BASE_PTRS;
0049
0050 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0051 #if defined(RDC_SEMA42_CLOCKS)
0052 /*! @brief Pointers to sema42 clocks for each instance. */
0053 static const clock_ip_name_t s_sema42Clocks[] = RDC_SEMA42_CLOCKS;
0054 #endif
0055 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0056
0057 /******************************************************************************
0058  * CODE
0059  *****************************************************************************/
0060
0061 uint32_t RDC_SEMA42_GetInstance(RDC_SEMAPHORE_Type *base)
0062 {
0063     uint32_t instance;
0064
0065     /* Find the instance index from base address mappings. */
0066     for (instance = 0; instance < ARRAY_SIZE(s_sema42Bases); instance++)
0067     {
0068         if (s_sema42Bases[instance] == base)
0069         {
0070             break;
0071         }
0072     }
0073
0074     assert(instance < ARRAY_SIZE(s_sema42Bases));
0075
0076     return instance;
0077 }
0078
0079 /*!
0080  * brief Initializes the RDC_SEMA42 module.
0081  *
0082  * This function initializes the RDC_SEMA42 module. It only enables the clock but does
0083  * not reset the gates because the module might be used by other processors
0084  * at the same time. To reset the gates, call either RDC_SEMA42_ResetGate or
0085  * RDC_SEMA42_ResetAllGates function.
0086  *
0087  * param base RDC_SEMA42 peripheral base address.
0088  */
0089 void RDC_SEMA42_Init(RDC_SEMAPHORE_Type *base)
0090 {
0091 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0092 #if defined(RDC_SEMA42_CLOCKS)
0093     CLOCK_EnableClock(s_sema42Clocks[RDC_SEMA42_GetInstance(base)]);
0094 #endif
0095 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0096 }
0097
0098 /*!
0099  * brief De-initializes the RDC_SEMA42 module.
0100  *
0101  * This function de-initializes the RDC_SEMA42 module. It only disables the clock.
0102  *
0103  * param base RDC_SEMA42 peripheral base address.
0104  */
0105 void RDC_SEMA42_Deinit(RDC_SEMAPHORE_Type *base)
0106 {
0107 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0108 #if defined(RDC_SEMA42_CLOCKS)
0109     CLOCK_DisableClock(s_sema42Clocks[RDC_SEMA42_GetInstance(base)]);
0110 #endif
0111 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0112 }
0113
0114 /*!
0115  * brief Tries to lock the RDC_SEMA42 gate.
0116  *
0117  * This function tries to lock the specific RDC_SEMA42 gate. If the gate has been
0118  * locked by another processor, this function returns an error code.
0119  *
0120  * param base RDC_SEMA42 peripheral base address.
0121  * param gateNum  Gate number to lock.
0122  * param masterIndex  Current processor master index.
0123  * param domainId  Current processor domain ID.
0124  *
0125  * retval kStatus_Success   Lock the sema42 gate successfully.
0126  * retval kStatus_Failed    Sema42 gate has been locked by another processor.
0127  */
0128 status_t RDC_SEMA42_TryLock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId)
0129 {
0130     assert(gateNum < RDC_SEMA42_GATE_COUNT);
0131
0132     status_t status = kStatus_Success;
0133     uint8_t regGate;
0134
0135     ++masterIndex;
0136
0137     regGate = (uint8_t)(RDC_SEMAPHORE_GATE_LDOM(domainId) | RDC_SEMAPHORE_GATE_GTFSM(masterIndex));
0138
0139     /* Try to lock. */
0140     RDC_SEMA42_GATEn(base, gateNum) = masterIndex;
0141
0142     /* Check locked or not. */
0143     if (regGate != RDC_SEMA42_GATEn(base, gateNum))
0144     {
0145         status = kStatus_Fail;
0146     }
0147
0148     return status;
0149 }
0150
0151 /*!
0152  * brief Locks the RDC_SEMA42 gate.
0153  *
0154  * This function locks the specific RDC_SEMA42 gate. If the gate has been
0155  * locked by other processors, this function waits until it is unlocked and then
0156  * lock it.
0157  *
0158  * param base RDC_SEMA42 peripheral base address.
0159  * param gateNum  Gate number to lock.
0160  * param masterIndex  Current processor master index.
0161  * param domainId  Current processor domain ID.
0162  */
0163 void RDC_SEMA42_Lock(RDC_SEMAPHORE_Type *base, uint8_t gateNum, uint8_t masterIndex, uint8_t domainId)
0164 {
0165     while (kStatus_Success != RDC_SEMA42_TryLock(base, gateNum, masterIndex, domainId))
0166     {
0167     }
0168 }
0169
0170 /*!
0171  * brief Gets which domain has currently locked the gate.
0172  *
0173  * param base RDC_SEMA42 peripheral base address.
0174  * param gateNum  Gate number.
0175  *
0176  * return Return -1 if the gate is not locked by any domain, otherwise return the
0177  * domain ID.
0178  */
0179 int32_t RDC_SEMA42_GetLockDomainID(RDC_SEMAPHORE_Type *base, uint8_t gateNum)
0180 {
0181     assert(gateNum < RDC_SEMA42_GATE_COUNT);
0182
0183     int32_t ret;
0184     uint8_t regGate = RDC_SEMA42_GATEn(base, gateNum);
0185
0186     /* Current gate is not locked. */
0187     if (0U == (regGate & RDC_SEMAPHORE_GATE_GTFSM_MASK))
0188     {
0189         ret = -1;
0190     }
0191     else
0192     {
0193         ret = (int32_t)((uint8_t)((regGate & RDC_SEMAPHORE_GATE_LDOM_MASK) >> RDC_SEMAPHORE_GATE_LDOM_SHIFT));
0194     }
0195
0196     return ret;
0197 }
0198
0199 /*!
0200  * brief Resets the RDC_SEMA42 gate to an unlocked status.
0201  *
0202  * This function resets a RDC_SEMA42 gate to an unlocked status.
0203  *
0204  * param base RDC_SEMA42 peripheral base address.
0205  * param gateNum  Gate number.
0206  *
0207  * retval kStatus_Success         RDC_SEMA42 gate is reset successfully.
0208  * retval kStatus_Failed Some other reset process is ongoing.
0209  */
0210 status_t RDC_SEMA42_ResetGate(RDC_SEMAPHORE_Type *base, uint8_t gateNum)
0211 {
0212     status_t status;
0213
0214     /*
0215      * Reset all gates if gateNum >= RDC_SEMA42_GATE_NUM_RESET_ALL
0216      * Reset specific gate if gateNum < RDC_SEMA42_GATE_COUNT
0217      */
0218
0219     /* Check whether some reset is ongoing. */
0220     if (0U != (base->RSTGT_R & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK))
0221     {
0222         status = kStatus_Fail;
0223     }
0224     else
0225     {
0226         /* First step. */
0227         base->RSTGT_W = RDC_SEMAPHORE_RSTGT_W_RSTGDP(RDC_SEMA42_GATE_RESET_PATTERN_1);
0228         /* Second step. */
0229         base->RSTGT_W =
0230             RDC_SEMAPHORE_RSTGT_W_RSTGDP(RDC_SEMA42_GATE_RESET_PATTERN_2) | RDC_SEMAPHORE_RSTGT_W_RSTGTN(gateNum);
0231
0232         status = kStatus_Success;
0233     }
0234
0235     return status;
0236 }