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File indexing completed on 2025-05-11 08:23:01

0001 /*
0002  * Copyright 2017-2022 NXP
0003  * All rights reserved.
0004  *
0005  * SPDX-License-Identifier: BSD-3-Clause
0006  */
0007 #ifndef _FSL_QTMR_H_
0008 #define _FSL_QTMR_H_
0009 
0010 #include "fsl_common.h"
0011 #ifdef __rtems__
0012 #include <rtems.h>
0013 #endif /* __rtems__ */
0014 
0015 /*!
0016  * @addtogroup qtmr
0017  * @{
0018  */
0019 
0020 /*******************************************************************************
0021  * Definitions
0022  ******************************************************************************/
0023 #ifndef TMR_CSCTRL_OFLAG_MASK
0024 #define TMR_CSCTRL_OFLAG_MASK (0x100UL)
0025 #endif
0026 
0027 #ifndef TMR_CSCTRL_OFLAG_SHIFT
0028 #define TMR_CSCTRL_OFLAG_SHIFT (8UL)
0029 #endif
0030 
0031 /*! @name Driver version */
0032 /*@{*/
0033 #define FSL_QTMR_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version */
0034 /*@}*/
0035 
0036 /*! @brief Quad Timer primary clock source selection*/
0037 typedef enum _qtmr_primary_count_source
0038 {
0039     kQTMR_ClockCounter0InputPin = 0, /*!< Use counter 0 input pin */
0040     kQTMR_ClockCounter1InputPin,     /*!< Use counter 1 input pin */
0041     kQTMR_ClockCounter2InputPin,     /*!< Use counter 2 input pin */
0042     kQTMR_ClockCounter3InputPin,     /*!< Use counter 3 input pin */
0043     kQTMR_ClockCounter0Output,       /*!< Use counter 0 output */
0044     kQTMR_ClockCounter1Output,       /*!< Use counter 1 output */
0045     kQTMR_ClockCounter2Output,       /*!< Use counter 2 output */
0046     kQTMR_ClockCounter3Output,       /*!< Use counter 3 output */
0047     kQTMR_ClockDivide_1,             /*!< IP bus clock divide by 1 prescaler */
0048     kQTMR_ClockDivide_2,             /*!< IP bus clock divide by 2 prescaler */
0049     kQTMR_ClockDivide_4,             /*!< IP bus clock divide by 4 prescaler */
0050     kQTMR_ClockDivide_8,             /*!< IP bus clock divide by 8 prescaler */
0051     kQTMR_ClockDivide_16,            /*!< IP bus clock divide by 16 prescaler */
0052     kQTMR_ClockDivide_32,            /*!< IP bus clock divide by 32 prescaler */
0053     kQTMR_ClockDivide_64,            /*!< IP bus clock divide by 64 prescaler */
0054     kQTMR_ClockDivide_128            /*!< IP bus clock divide by 128 prescaler */
0055 } qtmr_primary_count_source_t;
0056 
0057 /*! @brief Quad Timer input sources selection*/
0058 typedef enum _qtmr_input_source
0059 {
0060     kQTMR_Counter0InputPin = 0, /*!< Use counter 0 input pin */
0061     kQTMR_Counter1InputPin,     /*!< Use counter 1 input pin */
0062     kQTMR_Counter2InputPin,     /*!< Use counter 2 input pin */
0063     kQTMR_Counter3InputPin      /*!< Use counter 3 input pin */
0064 } qtmr_input_source_t;
0065 
0066 /*! @brief Quad Timer counting mode selection */
0067 typedef enum _qtmr_counting_mode
0068 {
0069     kQTMR_NoOperation = 0,          /*!< No operation */
0070     kQTMR_PriSrcRiseEdge,           /*!< Count rising edges of primary source */
0071     kQTMR_PriSrcRiseAndFallEdge,    /*!< Count rising and falling edges of primary source */
0072     kQTMR_PriSrcRiseEdgeSecInpHigh, /*!< Count rise edges of pri SRC while sec inp high active */
0073     kQTMR_QuadCountMode,            /*!< Quadrature count mode, uses pri and sec sources */
0074     kQTMR_PriSrcRiseEdgeSecDir,     /*!< Count rising edges of pri SRC; sec SRC specifies dir */
0075     kQTMR_SecSrcTrigPriCnt,         /*!< Edge of sec SRC trigger primary count until compare*/
0076     kQTMR_CascadeCount              /*!< Cascaded count mode (up/down) */
0077 } qtmr_counting_mode_t;
0078 
0079 /*! @brief Quad Timer PWM output state */
0080 typedef enum _qtmr_pwm_out_state
0081 {
0082     kQTMR_PwmLow = 0, /*!< The output state of PWM channel is low */
0083     kQTMR_PwmHigh,    /*!< The output state of PWM channel is low  */
0084 } qtmr_pwm_out_state_t;
0085 
0086 /*! @brief Quad Timer output mode selection*/
0087 typedef enum _qtmr_output_mode
0088 {
0089     kQTMR_AssertWhenCountActive = 0,    /*!< Assert OFLAG while counter is active*/
0090     kQTMR_ClearOnCompare,               /*!< Clear OFLAG on successful compare */
0091     kQTMR_SetOnCompare,                 /*!< Set OFLAG on successful compare */
0092     kQTMR_ToggleOnCompare,              /*!< Toggle OFLAG on successful compare */
0093     kQTMR_ToggleOnAltCompareReg,        /*!< Toggle OFLAG using alternating compare registers */
0094     kQTMR_SetOnCompareClearOnSecSrcInp, /*!< Set OFLAG on compare, clear on sec SRC input edge */
0095     kQTMR_SetOnCompareClearOnCountRoll, /*!< Set OFLAG on compare, clear on counter rollover */
0096     kQTMR_EnableGateClock               /*!< Enable gated clock output while count is active */
0097 } qtmr_output_mode_t;
0098 
0099 /*! @brief Quad Timer input capture edge mode, rising edge, or falling edge */
0100 typedef enum _qtmr_input_capture_edge
0101 {
0102     kQTMR_NoCapture = 0,       /*!< Capture is disabled */
0103     kQTMR_RisingEdge,          /*!< Capture on rising edge (IPS=0) or falling edge (IPS=1)*/
0104     kQTMR_FallingEdge,         /*!< Capture on falling edge (IPS=0) or rising edge (IPS=1)*/
0105     kQTMR_RisingAndFallingEdge /*!< Capture on both edges */
0106 } qtmr_input_capture_edge_t;
0107 
0108 /*! @brief Quad Timer input capture edge mode, rising edge, or falling edge */
0109 typedef enum _qtmr_preload_control
0110 {
0111     kQTMR_NoPreload = 0, /*!< Never preload */
0112     kQTMR_LoadOnComp1,   /*!< Load upon successful compare with value in COMP1 */
0113     kQTMR_LoadOnComp2    /*!< Load upon successful compare with value in COMP2*/
0114 } qtmr_preload_control_t;
0115 
0116 /*! @brief List of Quad Timer run options when in Debug mode */
0117 typedef enum _qtmr_debug_action
0118 {
0119     kQTMR_RunNormalInDebug = 0U, /*!< Continue with normal operation */
0120     kQTMR_HaltCounter,           /*!< Halt counter */
0121     kQTMR_ForceOutToZero,        /*!< Force output to logic 0 */
0122     kQTMR_HaltCountForceOutZero  /*!< Halt counter and force output to logic 0 */
0123 } qtmr_debug_action_t;
0124 
0125 /*! @brief List of Quad Timer interrupts */
0126 // typedef enum _qtmr_interrupt_enable
0127 typedef enum _qtmr_interrupt_enable
0128 {
0129     kQTMR_CompareInterruptEnable  = (1U << 0), /*!< Compare interrupt.*/
0130     kQTMR_Compare1InterruptEnable = (1U << 1), /*!< Compare 1 interrupt.*/
0131     kQTMR_Compare2InterruptEnable = (1U << 2), /*!< Compare 2 interrupt.*/
0132     kQTMR_OverflowInterruptEnable = (1U << 3), /*!< Timer overflow interrupt.*/
0133     kQTMR_EdgeInterruptEnable     = (1U << 4)  /*!< Input edge interrupt.*/
0134 } qtmr_interrupt_enable_t;
0135 
0136 /*! @brief List of Quad Timer flags */
0137 typedef enum _qtmr_status_flags
0138 {
0139     kQTMR_CompareFlag  = (1U << 0), /*!< Compare flag */
0140     kQTMR_Compare1Flag = (1U << 1), /*!< Compare 1 flag */
0141     kQTMR_Compare2Flag = (1U << 2), /*!< Compare 2 flag */
0142     kQTMR_OverflowFlag = (1U << 3), /*!< Timer overflow flag */
0143     kQTMR_EdgeFlag     = (1U << 4)  /*!< Input edge flag */
0144 } qtmr_status_flags_t;
0145 
0146 /*! @brief List of channel selection */
0147 typedef enum _qtmr_channel_selection
0148 {
0149     kQTMR_Channel_0 = 0U, /*!< TMR Channel 0 */
0150     kQTMR_Channel_1,      /*!< TMR Channel 1 */
0151     kQTMR_Channel_2,      /*!< TMR Channel 2 */
0152     kQTMR_Channel_3,      /*!< TMR Channel 3 */
0153 } qtmr_channel_selection_t;
0154 
0155 /*! @brief List of Quad Timer DMA enable */
0156 typedef enum _qtmr_dma_enable
0157 {
0158     kQTMR_InputEdgeFlagDmaEnable      = (1U << 0), /*!< Input Edge Flag DMA Enable.*/
0159     kQTMR_ComparatorPreload1DmaEnable = (1U << 1), /*!< Comparator Preload Register 1 DMA Enable.*/
0160     kQTMR_ComparatorPreload2DmaEnable = (1U << 2), /*!< Comparator Preload Register 2 DMA Enable.*/
0161 } qtmr_dma_enable_t;
0162 
0163 /*!
0164  * @brief Quad Timer config structure
0165  *
0166  * This structure holds the configuration settings for the Quad Timer peripheral. To initialize this
0167  * structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a
0168  * pointer to your config structure instance.
0169  *
0170  * The config struct can be made const so it resides in flash
0171  */
0172 typedef struct _qtmr_config
0173 {
0174     qtmr_primary_count_source_t primarySource; /*!< Specify the primary count source */
0175     qtmr_input_source_t secondarySource;       /*!< Specify the secondary count source */
0176     bool enableMasterMode;                     /*!< true: Broadcast compare function output to other counters;
0177                                                     false no broadcast */
0178     bool enableExternalForce;                  /*!< true: Compare from another counter force state of OFLAG signal
0179                                                     false: OFLAG controlled by local counter */
0180     uint8_t faultFilterCount;                  /*!< Fault filter count */
0181     uint8_t faultFilterPeriod;                 /*!< Fault filter period;value of 0 will bypass the filter */
0182     qtmr_debug_action_t debugMode;             /*!< Operation in Debug mode */
0183 } qtmr_config_t;
0184 
0185 /*******************************************************************************
0186  * API
0187  ******************************************************************************/
0188 
0189 #if defined(__cplusplus)
0190 extern "C" {
0191 #endif
0192 
0193 /*!
0194  * @name Initialization and deinitialization
0195  * @{
0196  */
0197 #ifdef __rtems__
0198 /*!
0199  * @brief Return the timer base based on a FDT node.
0200  *
0201  * @param fdt      Pointer to the fdt
0202  * @param node     The FDT node
0203  *
0204  * @return Pointer to the timer. NULL on error (for example if node isn't
0205  *         compatible).
0206  */
0207 TMR_Type *QTMR_get_regs_from_fdt(const void *fdt, int node);
0208 
0209 /*!
0210  * @brief Return the timer IRQ vector based on a FDT node.
0211  *
0212  * @param fdt      Pointer to the fdt
0213  * @param node     The FDT node
0214  *
0215  * @return IRQ vector number. BSP_INTERRUPT_VECTOR_INVALID on error.
0216  */
0217 rtems_vector_number QTMR_get_IRQ_from_fdt(const void *fdt, int node);
0218 
0219 /*!
0220  * @brief Return the clock source frequency of the quad timer.
0221  *
0222  * @param base     Quad Timer peripheral base address.
0223  *
0224  * @return Clock frequency value in hertz.
0225  */
0226 uint32_t QTMR_get_src_clk(TMR_Type *base);
0227 #endif /* __rtems__ */
0228 
0229 /*!
0230  * @brief Ungates the Quad Timer clock and configures the peripheral for basic operation.
0231  *
0232  * @note This API should be called at the beginning of the application using the Quad Timer driver.
0233  *
0234  * @param base     Quad Timer peripheral base address
0235  * @param channel  Quad Timer channel number
0236  * @param config   Pointer to user's Quad Timer config structure
0237  */
0238 void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config);
0239 
0240 /*!
0241  * @brief Stops the counter and gates the Quad Timer clock
0242  *
0243  * @param base     Quad Timer peripheral base address
0244  * @param channel  Quad Timer channel number
0245  */
0246 void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel);
0247 
0248 /*!
0249  * @brief  Fill in the Quad Timer config struct with the default settings
0250  *
0251  * The default values are:
0252  * @code
0253  *    config->debugMode = kQTMR_RunNormalInDebug;
0254  *    config->enableExternalForce = false;
0255  *    config->enableMasterMode = false;
0256  *    config->faultFilterCount = 0;
0257  *    config->faultFilterPeriod = 0;
0258  *    config->primarySource = kQTMR_ClockDivide_2;
0259  *    config->secondarySource = kQTMR_Counter0InputPin;
0260  * @endcode
0261  * @param config Pointer to user's Quad Timer config structure.
0262  */
0263 void QTMR_GetDefaultConfig(qtmr_config_t *config);
0264 
0265 /*! @}*/
0266 
0267 /*!
0268  * @brief Sets up Quad timer module for PWM signal output.
0269  *
0270  * The function initializes the timer module according to the parameters passed in by the user. The
0271  * function also sets up the value compare registers to match the PWM signal requirements.
0272  *
0273  * @param base             Quad Timer peripheral base address
0274  * @param channel          Quad Timer channel number
0275  * @param pwmFreqHz        PWM signal frequency in Hz
0276  * @param dutyCyclePercent PWM pulse width, value should be between 0 to 100
0277  *                         0=inactive signal(0% duty cycle)...
0278  *                         100=active signal (100% duty cycle)
0279  * @param outputPolarity   true: invert polarity of the output signal, false: no inversion
0280  * @param srcClock_Hz      Main counter clock in Hz.
0281  *
0282  * @return Returns an error if there was error setting up the signal.
0283  */
0284 status_t QTMR_SetupPwm(TMR_Type *base,
0285                        qtmr_channel_selection_t channel,
0286                        uint32_t pwmFreqHz,
0287                        uint8_t dutyCyclePercent,
0288                        bool outputPolarity,
0289                        uint32_t srcClock_Hz);
0290 
0291 /*!
0292  * @brief Allows the user to count the source clock cycles until a capture event arrives.
0293  *
0294  * The count is stored in the capture register.
0295  *
0296  * @param base            Quad Timer peripheral base address
0297  * @param channel         Quad Timer channel number
0298  * @param capturePin      Pin through which we receive the input signal to trigger the capture
0299  * @param inputPolarity   true: invert polarity of the input signal, false: no inversion
0300  * @param reloadOnCapture true: reload the counter when an input capture occurs, false: no reload
0301  * @param captureMode     Specifies which edge of the input signal  triggers a capture
0302  */
0303 void QTMR_SetupInputCapture(TMR_Type *base,
0304                             qtmr_channel_selection_t channel,
0305                             qtmr_input_source_t capturePin,
0306                             bool inputPolarity,
0307                             bool reloadOnCapture,
0308                             qtmr_input_capture_edge_t captureMode);
0309 
0310 /*!
0311  * @name Interrupt Interface
0312  * @{
0313  */
0314 
0315 /*!
0316  * @brief Enables the selected Quad Timer interrupts
0317  *
0318  * @param base      Quad Timer peripheral base address
0319  * @param channel   Quad Timer channel number
0320  * @param mask      The interrupts to enable. This is a logical OR of members of the
0321  *                  enumeration ::qtmr_interrupt_enable_t
0322  */
0323 void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask);
0324 
0325 /*!
0326  * @brief Disables the selected Quad Timer interrupts
0327  *
0328  * @param base     Quad Timer peripheral base addres
0329  * @param channel  Quad Timer channel number
0330  * @param mask The interrupts to enable. This is a logical OR of members of the
0331  *             enumeration ::qtmr_interrupt_enable_t
0332  */
0333 void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask);
0334 
0335 /*!
0336  * @brief Gets the enabled Quad Timer interrupts
0337  *
0338  * @param base    Quad Timer peripheral base address
0339  * @param channel Quad Timer channel number
0340  *
0341  * @return The enabled interrupts. This is the logical OR of members of the
0342  *         enumeration ::qtmr_interrupt_enable_t
0343  */
0344 uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel);
0345 
0346 /*! @}*/
0347 
0348 /*!
0349  * @name Status Interface
0350  * @{
0351  */
0352 
0353 /*!
0354  * @brief Gets the Quad Timer status flags
0355  *
0356  * @param base     Quad Timer peripheral base address
0357  * @param channel  Quad Timer channel number
0358  *
0359  * @return The status flags. This is the logical OR of members of the
0360  *         enumeration ::qtmr_status_flags_t
0361  */
0362 uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel);
0363 
0364 /*!
0365  * @brief Clears the Quad Timer status flags.
0366  *
0367  * @param base     Quad Timer peripheral base address
0368  * @param channel  Quad Timer channel number
0369  * @param mask The status flags to clear. This is a logical OR of members of the
0370  *             enumeration ::qtmr_status_flags_t
0371  */
0372 void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask);
0373 
0374 /*! @}*/
0375 
0376 /*!
0377  * @name Read and Write the timer period
0378  * @{
0379  */
0380 
0381 /*!
0382  * @brief Sets the timer period in ticks.
0383  *
0384  * Timers counts from initial value till it equals the count value set here. The counter
0385  * will then reinitialize to the value specified in the Load register.
0386  *
0387  * @note
0388  * 1. This function will write the time period in ticks to COMP1 or COMP2 register
0389  *    depending on the count direction
0390  * 2. User can call the utility macros provided in fsl_common.h to convert to ticks
0391  * 3. This function supports cases, providing only primary source clock without secondary source clock.
0392  *
0393  * @param base     Quad Timer peripheral base address
0394  * @param channel  Quad Timer channel number
0395  * @param ticks Timer period in units of ticks
0396  */
0397 void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks);
0398 
0399 /*!
0400  * @brief Set compare value.
0401  *
0402  * This function sets the value used for comparison with the counter value.
0403  *
0404  * @param base     Quad Timer peripheral base address
0405  * @param channel  Quad Timer channel number
0406  * @param ticks    Timer period in units of ticks.
0407  */
0408 void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks);
0409 
0410 /*!
0411  * @brief Set load value.
0412  *
0413  * This function sets the value used to initialize the counter after a counter comparison.
0414  *
0415  * @param base     Quad Timer peripheral base address
0416  * @param channel  Quad Timer channel number
0417  * @param value    Load register initialization value.
0418  */
0419 static inline void QTMR_SetLoadValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t value)
0420 {
0421     base->CHANNEL[channel].LOAD &= (uint16_t)(~TMR_LOAD_LOAD_MASK);
0422     base->CHANNEL[channel].LOAD = value;
0423 }
0424 
0425 /*!
0426  * @brief Reads the current timer counting value.
0427  *
0428  * This function returns the real-time timer counting value, in a range from 0 to a
0429  * timer period.
0430  *
0431  * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
0432  *
0433  * @param base     Quad Timer peripheral base address
0434  * @param channel  Quad Timer channel number
0435  *
0436  * @return Current counter value in ticks
0437  */
0438 static inline uint16_t QTMR_GetCurrentTimerCount(TMR_Type *base, qtmr_channel_selection_t channel)
0439 {
0440     return base->CHANNEL[channel].CNTR;
0441 }
0442 
0443 /*! @}*/
0444 
0445 /*!
0446  * @name Timer Start and Stop
0447  * @{
0448  */
0449 
0450 /*!
0451  * @brief Starts the Quad Timer counter.
0452  *
0453  *
0454  * @param base        Quad Timer peripheral base address
0455  * @param channel     Quad Timer channel number
0456  * @param clockSource Quad Timer clock source
0457  */
0458 static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_counting_mode_t clockSource)
0459 {
0460     uint16_t reg = base->CHANNEL[channel].CTRL;
0461 
0462     reg &= (uint16_t)(~(TMR_CTRL_CM_MASK));
0463     reg |= TMR_CTRL_CM(clockSource);
0464     base->CHANNEL[channel].CTRL = reg;
0465 }
0466 
0467 /*!
0468  * @brief Stops the Quad Timer counter.
0469  *
0470  * @param base     Quad Timer peripheral base address
0471  * @param channel  Quad Timer channel number
0472  */
0473 static inline void QTMR_StopTimer(TMR_Type *base, qtmr_channel_selection_t channel)
0474 {
0475     base->CHANNEL[channel].CTRL &= (uint16_t)(~TMR_CTRL_CM_MASK);
0476 }
0477 
0478 /*! @}*/
0479 
0480 /*!
0481  * @name Enable and Disable the Quad Timer DMA
0482  * @{
0483  */
0484 
0485 /*!
0486  * @brief Enable the Quad Timer DMA.
0487  *
0488  * @param base     Quad Timer peripheral base address
0489  * @param channel  Quad Timer channel number
0490  * @param mask     The DMA to enable. This is a logical OR of members of the
0491  *                  enumeration ::qtmr_dma_enable_t
0492  */
0493 void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask);
0494 
0495 /*!
0496  * @brief Disable the Quad Timer DMA.
0497  *
0498  * @param base     Quad Timer peripheral base address
0499  * @param channel  Quad Timer channel number
0500  * @param mask     The DMA to enable. This is a logical OR of members of the
0501  *                  enumeration ::qtmr_dma_enable_t
0502  */
0503 void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask);
0504 
0505 /*!
0506  * @brief Set PWM output in idle status (high or low).
0507  *
0508  * @note When the PWM is set again, the counting needs to be restarted.
0509  *
0510  * @param base     Quad Timer peripheral base address
0511  * @param channel  Quad Timer channel number
0512  * @param idleStatus   True: PWM output is high in idle status; false: PWM output is low in idle status.
0513  */
0514 void QTMR_SetPwmOutputToIdle(TMR_Type *base, qtmr_channel_selection_t channel, bool idleStatus);
0515 
0516 /*!
0517  * @brief Get the channel output status
0518  *
0519  * @param base     Quad Timer peripheral base address
0520  * @param channel  Quad Timer channel number
0521  *
0522  * @return Current channel output status.
0523  */
0524 static inline qtmr_pwm_out_state_t QTMR_GetPwmOutputStatus(TMR_Type *base, qtmr_channel_selection_t channel)
0525 {
0526     if (0U != ((base->CHANNEL[channel].CSCTRL) & TMR_CSCTRL_OFLAG_MASK))
0527     {
0528         return kQTMR_PwmHigh;
0529     }
0530     else
0531     {
0532         return kQTMR_PwmLow;
0533     }
0534 }
0535 
0536 /*!
0537  * @brief Get the PWM channel dutycycle value.
0538  *
0539  * @param base     Quad Timer peripheral base address
0540  * @param channel  Quad Timer channel number
0541  *
0542  * @return Current channel dutycycle value.
0543  */
0544 uint8_t QTMR_GetPwmChannelStatus(TMR_Type *base, qtmr_channel_selection_t channel);
0545 
0546 /*!
0547  * @brief This function set the value of the prescaler on QTimer channels.
0548  *
0549  * @param base         Quad Timer peripheral base address
0550  * @param channel      Quad Timer channel number
0551  * @param prescaler    Set prescaler value
0552  */
0553 void QTMR_SetPwmClockMode(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_primary_count_source_t prescaler);
0554 
0555 /*! @}*/
0556 
0557 #if defined(__cplusplus)
0558 }
0559 #endif
0560 
0561 /*! @}*/
0562 
0563 #endif /* _FSL_QTMR_H_ */