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0001 /* 0002 * Copyright 2017-2022 NXP 0003 * All rights reserved. 0004 * 0005 * 0006 * SPDX-License-Identifier: BSD-3-Clause 0007 */ 0008 0009 #ifndef _FSL_PXP_H_ 0010 #define _FSL_PXP_H_ 0011 0012 #include "fsl_common.h" 0013 0014 /* Compatibility macro map. */ 0015 #if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA0_INVERT_MASK)) 0016 #define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK 0017 #endif 0018 0019 #if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA_INVERT_MASK)) 0020 #define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK 0021 #endif 0022 0023 #if defined(PXP_STAT_IRQ_MASK) && (!defined(PXP_STAT_IRQ0_MASK)) 0024 #define PXP_STAT_IRQ0_MASK PXP_STAT_IRQ_MASK 0025 #endif 0026 0027 #if defined(PXP_STAT_AXI_READ_ERROR_MASK) && (!defined(PXP_STAT_AXI_READ_ERROR_0_MASK)) 0028 #define PXP_STAT_AXI_READ_ERROR_0_MASK PXP_STAT_AXI_READ_ERROR_MASK 0029 #endif 0030 0031 #if defined(PXP_STAT_AXI_WRITE_ERROR_MASK) && (!defined(PXP_STAT_AXI_WRITE_ERROR_0_MASK)) 0032 #define PXP_STAT_AXI_WRITE_ERROR_0_MASK PXP_STAT_AXI_WRITE_ERROR_MASK 0033 #endif 0034 0035 /*! 0036 * @addtogroup pxp_driver 0037 * @{ 0038 */ 0039 0040 /******************************************************************************* 0041 * Definitions 0042 ******************************************************************************/ 0043 0044 /* PXP global LUT table is 16K. */ 0045 #define PXP_LUT_TABLE_BYTE (16UL * 1024UL) 0046 /* Intenral memory for LUT, the size is 256 bytes. */ 0047 #define PXP_INTERNAL_RAM_LUT_BYTE (256) 0048 0049 /*! @name Driver version */ 0050 /*@{*/ 0051 #define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) 0052 /*@}*/ 0053 0054 /* This macto indicates whether the rotate sub module is shared by process surface and output buffer. */ 0055 #if defined(PXP_CTRL_ROT_POS_MASK) 0056 #define PXP_SHARE_ROTATE 1 0057 #else 0058 #define PXP_SHARE_ROTATE 0 0059 #endif 0060 0061 /* This macto indicates whether PXP needs mux the process path. */ 0062 #if defined(PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK) 0063 #define PXP_USE_PATH 1 0064 #else 0065 #define PXP_USE_PATH 0 0066 #endif 0067 0068 #if PXP_USE_PATH 0069 #define PXP_PATH(mux, sel) (((mux) << 8U) | (sel)) 0070 #define PXP_GET_MUX_FROM_PATH(path) ((path) >> 8U) 0071 #define PXP_GET_SEL_FROM_PATH(path) ((path)&0x03U) 0072 #endif /* PXP_USE_PATH */ 0073 0074 /*! @brief PXP interrupts to enable. */ 0075 enum _pxp_interrupt_enable 0076 { 0077 kPXP_CompleteInterruptEnable = PXP_CTRL_IRQ_ENABLE_MASK, /*!< PXP process completed. bit 1 */ 0078 kPXP_CommandLoadInterruptEnable = PXP_CTRL_NEXT_IRQ_ENABLE_MASK, /*!< Interrupt to show that the command set by @ref 0079 PXP_SetNextCommand has been loaded. bit 2 */ 0080 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) 0081 kPXP_LutDmaLoadInterruptEnable = 0082 PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK, /*!< The LUT table has been loaded by DMA. bit 3 */ 0083 #endif 0084 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 0085 kPXP_CompressDoneInterruptEnable = 0086 PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_MASK >> 16U, /*!< Compress done interrupt enable. bit 15 */ 0087 kPXP_InputFetchCh0InterruptEnable = PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_MASK 0088 << 16U, /*!< Input fetch channel 0 completed. bit 16 */ 0089 kPXP_InputFetchCh1InterruptEnable = PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_MASK 0090 << 16U, /*!< Input fetch channel 1 completed. bit 17 */ 0091 kPXP_InputStoreCh0InterruptEnable = PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_MASK 0092 << 16U, /*!< Input store channel 0 completed. bit 18 */ 0093 kPXP_InputStoreCh1InterruptEnable = PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_MASK 0094 << 16U, /*!< Input store channel 1 completed. bit 19 */ 0095 kPXP_DitherFetchCh0InterruptEnable = PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_MASK 0096 << 16U, /*!< Dither fetch channel 0 completed. bit 20 */ 0097 kPXP_DitherFetchCh1InterruptEnable = PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_MASK 0098 << 16U, /*!< Dither fetch channel 1 completed. bit 21 */ 0099 kPXP_DitherStoreCh0InterruptEnable = PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_MASK 0100 << 16U, /*!< Dither store channle 0 completed. bit 22 */ 0101 kPXP_DitherStoreCh1InterruptEnable = PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_MASK 0102 << 16U, /*!< Dither store channle 1 completed. bit 23 */ 0103 kPXP_WfeaStoreCh0InterruptEnable = PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_MASK 0104 << 16U, /*!< WFE-A store channel 0 completed. bit 24 */ 0105 kPXP_WfeaStoreCh1InterruptEnable = PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_MASK 0106 << 16U, /*!< WFE-A store channel 1 completed. bit 25 */ 0107 kPXP_WfebStoreCh0InterruptEnable = PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK 0108 << 16U, /*!< WFE-B store channel 0 completed. bit 26 */ 0109 kPXP_WfebStoreCh1InterruptEnable = PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK 0110 << 16U, /*!< WFE-B store channel 1 completed. bit 27 */ 0111 kPXP_InputStoreInterruptEnable = PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_MASK << 16U, /*!< Input store completed. bit 28 */ 0112 kPXP_DitherStoreInterruptEnable = PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_MASK 0113 << 16U, /*!< Dither store completed. bit 29 */ 0114 kPXP_WfeaStoreInterruptEnable = PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_MASK << 16U, /*!< WFE-A store completed. bit 30 */ 0115 kPXP_WfebStoreInterruptEnable = PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK << 16U, /*!< WFE-B store completed. bit 31 */ 0116 #endif /* FSL_FEATURE_PXP_V3 */ 0117 }; 0118 0119 /*! 0120 * @brief PXP status flags. 0121 * 0122 * @note These enumerations are meant to be OR'd together to form a bit mask. 0123 */ 0124 enum _pxp_flags 0125 { 0126 kPXP_CompleteFlag = PXP_STAT_IRQ0_MASK, /*!< PXP process completed. bit 0 */ 0127 kPXP_Axi0WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_0_MASK, /*!< PXP encountered an AXI write error and processing 0128 has been terminated. bit 1*/ 0129 kPXP_Axi0ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_0_MASK, /*!< PXP encountered an AXI read error and processing has 0130 been terminated. bit 2 */ 0131 kPXP_CommandLoadFlag = PXP_STAT_NEXT_IRQ_MASK, /*!< The command set by @ref PXP_SetNextCommand has been loaded, 0132 could set new command. bit 3 */ 0133 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) 0134 kPXP_LutDmaLoadFlag = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK, /*!< The LUT table has been loaded by DMA. bit 8 */ 0135 #endif 0136 #if defined(PXP_STAT_AXI_READ_ERROR_1_MASK) 0137 kPXP_Axi1WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_1_MASK, /*!< PXP encountered an AXI write error and processing 0138 has been terminated. bit 9 */ 0139 kPXP_Axi1ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_1_MASK, /*!< PXP encountered an AXI read error and processing has 0140 been terminated. bit 10 */ 0141 #endif 0142 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 0143 kPXP_CompressDoneFlag = PXP_IRQ_COMPRESS_DONE_IRQ_MASK >> 16U, /*!< Compress done. bit 15 */ 0144 kPXP_InputFetchCh0CompleteFlag = PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_MASK 0145 << 16U, /*!< Input fetch channel 0 completed. bit 16 */ 0146 kPXP_InputFetchCh1CompleteFlag = PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_MASK 0147 << 16U, /*!< Input fetch channel 1 completed. bit 17 */ 0148 kPXP_InputStoreCh0CompleteFlag = PXP_IRQ_FIRST_CH0_STORE_IRQ_MASK 0149 << 16U, /*!< Input store channel 0 completed. bit 18 */ 0150 kPXP_InputStoreCh1CompleteFlag = PXP_IRQ_FIRST_CH1_STORE_IRQ_MASK 0151 << 16U, /*!< Input store channel 1 completed. bit 19 */ 0152 kPXP_DitherFetchCh0CompleteFlag = PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_MASK 0153 << 16U, /*!< Dither fetch channel 0 completed. bit 20 */ 0154 kPXP_DitherFetchCh1CompleteFlag = PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_MASK 0155 << 16U, /*!< Dither fetch channel 1 completed. bit 21 */ 0156 kPXP_DitherStoreCh0CompleteFlag = PXP_IRQ_DITHER_CH0_STORE_IRQ_MASK 0157 << 16U, /*!< Dither store channel 0 completed. bit 22 */ 0158 kPXP_DitherStoreCh1CompleteFlag = PXP_IRQ_DITHER_CH1_STORE_IRQ_MASK 0159 << 16U, /*!< Dither store channel 1 completed. bit 23 */ 0160 kPXP_WfeaStoreCh0CompleteFlag = PXP_IRQ_WFE_A_CH0_STORE_IRQ_MASK 0161 << 16U, /*!< WFE-A store channel 0 completed. bit 24 */ 0162 kPXP_WfeaStoreCh1CompleteFlag = PXP_IRQ_WFE_A_CH1_STORE_IRQ_MASK 0163 << 16U, /*!< WFE-A store channel 1 completed. bit 25 */ 0164 kPXP_WfebStoreCh0CompleteFlag = PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK 0165 << 16U, /*!< WFE-B store channel 0 completed. bit 26 */ 0166 kPXP_WfebStoreCh1CompleteFlag = PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK 0167 << 16U, /*!< WFE-B store channel 1 completed. bit 27 */ 0168 kPXP_InputStoreCompleteFlag = PXP_IRQ_FIRST_STORE_IRQ_MASK << 16U, /*!< Input store completed. bit 28 */ 0169 kPXP_DitherStoreCompleteFlag = PXP_IRQ_DITHER_STORE_IRQ_MASK << 16U, /*!< Dither store completed. bit 29 */ 0170 kPXP_WfeaStoreCompleteFlag = PXP_IRQ_WFE_A_STORE_IRQ_MASK << 16U, /*!< WFE-A store completed. bit 30 */ 0171 kPXP_WfebStoreCompleteFlag = PXP_IRQ_WFE_B_STORE_IRQ_MASK << 16U, /*!< WFE-B store completed. bit 31 */ 0172 #endif /* FSL_FEATURE_PXP_V3 */ 0173 }; 0174 0175 #if PXP_USE_PATH 0176 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 0177 typedef enum _pxp_path 0178 { 0179 kPXP_Mux0SelectProcessSurfaceEngine = PXP_PATH(0U, 0U), /*!< MUX0 select Process Surface engine. */ 0180 kPXP_Mux0SelectInputFetchEngineChannel0 = PXP_PATH(0U, 1U), /*!< MUX0 select input Fetch engine channel 0. */ 0181 kPXP_Mux0SelectInputFetchEngineChannel1 = PXP_PATH(0U, 2U), /*!< MUX0 select input Fetch engine channel 1. */ 0182 kPXP_Mux0SelectNone = PXP_PATH(0U, 3U), /*!< MUX0 select no output. */ 0183 kPXP_Mux1SelectInputFetchEngineChannel0 = PXP_PATH(1U, 0U), /*!< MUX1 select input Fetch engine channel 0. */ 0184 kPXP_Mux1SelectRotation1Engine = PXP_PATH(1U, 1U), /*!< MUX1 select Rotation1 engine output. */ 0185 kPXP_Mux1SelectNone = PXP_PATH(1U, 2U), /*!< MUX1 select no output. */ 0186 kPXP_Mux2SelectInputFetchEngineChannel1 = PXP_PATH(2U, 0U), /*!< MUX2 select input Fetch engine channel 1. */ 0187 kPXP_Mux2SelectRotation1Engine = PXP_PATH(2U, 1U), /*!< MUX2 select Rotation1 engine output. */ 0188 kPXP_Mux2SelectNone = PXP_PATH(2U, 2U), /*!< MUX2 select no output. */ 0189 kPXP_Mux3SelectCsc1Engine = PXP_PATH(3U, 0U), /*!< MUX3 select output of CSC1 engine. */ 0190 kPXP_Mux3SelectRotation1Engine = PXP_PATH(3U, 1U), /*!< MUX3 select output of Rotation1 engine. */ 0191 kPXP_Mux3SelectNone = PXP_PATH(3U, 2U), /*!< MUX3 select no output. */ 0192 kPXP_Mux5SelectMux1 = PXP_PATH(5U, 0U), /*!< MUX5 select output of MUX1. */ 0193 kPXP_Mux5SelectAlphaBlending1 = PXP_PATH(5U, 1U), /*!< MUX5 select output of alpha blending / color key 1. */ 0194 kPXP_Mux5SelectNone = PXP_PATH(5U, 2U), /*!< MUX5 select no output. */ 0195 kPXP_Mux6SelectAlphaBlending1 = PXP_PATH(6U, 0U), /*!< MUX6 select output of alpha blending / color key 1. */ 0196 kPXP_Mux6SelectAlphaBlending0 = PXP_PATH(6U, 1U), /*!< MUX6 select output of alpha blending / color key 0. */ 0197 kPXP_Mux6SelectNone = PXP_PATH(6U, 2U), /*!< MUX6 select no output. */ 0198 kPXP_Mux7SelectMux5 = PXP_PATH(7U, 0U), /*!< MUX7 select output of MUX5. */ 0199 kPXP_Mux7SelectCsc2Engine = PXP_PATH(7U, 1U), /*!< MUX7 select output of CSC2 engine. */ 0200 kPXP_Mux7SelectNone = PXP_PATH(7U, 2U), /*!< MUX7 select no output. */ 0201 kPXP_Mux8SelectCsc2Engine = PXP_PATH(8U, 0U), /*!< MUX8 select output of CSC2 engine. */ 0202 kPXP_Mux8SelectAlphaBlending0 = PXP_PATH(8U, 1U), /*!< MUX8 select output of alpha blending / color key 0. */ 0203 kPXP_Mux8SelectNone = PXP_PATH(8U, 2U), /*!< MUX8 select no output. */ 0204 kPXP_Mux9SelectMux7 = PXP_PATH(9U, 0U), /*!< MUX9 select output of MUX7. */ 0205 kPXP_Mux9SelectMux8 = PXP_PATH(9U, 1U), /*!< MUX9 select output of MUX8. */ 0206 kPXP_Mux9SelectNone = PXP_PATH(9U, 2U), /*!< MUX9 select no output. */ 0207 kPXP_Mux10SelectMux7 = PXP_PATH(10U, 0U), /*!< MUX10 select output of MUX7. */ 0208 kPXP_Mux10SelectLut = PXP_PATH(10U, 1U), /*!< MUX10 select output of LUT. */ 0209 kPXP_Mux10SelectNone = PXP_PATH(10U, 2U), /*!< MUX10 select no output. */ 0210 kPXP_Mux11SelectLut = PXP_PATH(11U, 0U), /*!< MUX11 select output of LUT. */ 0211 kPXP_Mux11SelectMux8 = PXP_PATH(11U, 1U), /*!< MUX11 select output of MUX8. */ 0212 kPXP_Mux11SelectNone = PXP_PATH(11U, 2U), /*!< MUX11 select no output. */ 0213 kPXP_Mux12SelectMux10 = PXP_PATH(12U, 0U), /*!< MUX12 select output of MUX10. */ 0214 kPXP_Mux12SelectMux11 = PXP_PATH(12U, 1U), /*!< MUX12 select output of MUX11. */ 0215 kPXP_Mux12SelectNone = PXP_PATH(12U, 2U), /*!< MUX12 select no output. */ 0216 kPXP_Mux13SelectNone = PXP_PATH(13U, 0U), /*!< MUX13 select no output. */ 0217 kPXP_Mux13SelectFetchEngineChannel1 = PXP_PATH(13U, 1U), /*!< MUX13 select input Fetch engine channel 1. */ 0218 kPXP_Mux14SelectRotation0Engine = PXP_PATH(14U, 0U), /*!< MUX14 select output of Rotation0 engine. */ 0219 kPXP_Mux14SelectMux11 = PXP_PATH(14U, 1U), /*!< MUX14 select output of MUX11. */ 0220 kPXP_Mux14SelectNone = PXP_PATH(14U, 2U), /*!< MUX14 select no output. */ 0221 kPXP_Mux15SelectFetchEngineChannel0 = PXP_PATH(15U, 0U), /*!< MUX15 select input Fetch engine channel 0. */ 0222 kPXP_Mux15SelectMux10 = PXP_PATH(15U, 1U), /*!< MUX15 select output of MUX10. */ 0223 kPXP_Mux15SelectNone = PXP_PATH(15U, 2U), /*!< MUX15 select no output. */ 0224 kPXP_Mux16SelectAluA = PXP_PATH(16U, 0U), /*!< MUX16 select output of ALU A. */ 0225 kPXP_Mux16SelectOutput = PXP_PATH(16U, 1U), /*!< MUX16 select output of legacy output. */ 0226 kPXP_Mux16SelectAluB = PXP_PATH(16U, 2U), /*!< MUX16 select output of ALU B. */ 0227 kPXP_Mux16SelectNone = PXP_PATH(16U, 3U), /*!< MUX16 select no output. */ 0228 kPXP_Mux17SelectAluA = PXP_PATH(17U, 0U), /*!< MUX17 select output of ALU A. */ 0229 kPXP_Mux17SelectAluB = PXP_PATH(17U, 1U), /*!< MUX17 select output of ALU B. */ 0230 kPXP_Mux17SelectNone = PXP_PATH(17U, 2U), /*!< MUX17 select no output. */ 0231 } pxp_path_t; 0232 #else 0233 typedef enum _pxp_path 0234 { 0235 kPXP_Mux0SelectFetchDataArray = PXP_PATH(0U, 0U), /*!< MUX0 select Fetch Data Array. */ 0236 kPXP_Mux0SelectAlu = PXP_PATH(0U, 1U), /*!< MUX0 select output of ALU. */ 0237 kPXP_Mux0SelectNone = PXP_PATH(0U, 2U), /*!< MUX0 select no output. */ 0238 kPXP_Mux1SelectLut = PXP_PATH(1U, 0U), /*!< MUX1 select output of LUT. */ 0239 kPXP_Mux1SelectMux0 = PXP_PATH(1U, 1U), /*!< MUX1 select output of MUX0. */ 0240 kPXP_Mux1SelectNone = PXP_PATH(1U, 2U), /*!< MUX1 select no output. */ 0241 kPXP_Mux3SelectRotation1Engine = PXP_PATH(3U, 0U), /*!< MUX3 select output of Rotation1 engine. */ 0242 kPXP_Mux3SelectCsc1Engine = PXP_PATH(3U, 1U), /*!< MUX3 select output of CSC1 engine. */ 0243 kPXP_Mux3SelectNone = PXP_PATH(3U, 2U), /*!< MUX3 select no output. */ 0244 kPXP_Mux8SelectCsc2Engine = PXP_PATH(8U, 0U), /*!< MUX8 select output of CSC2 engine. */ 0245 kPXP_Mux8SelectAlphaBlending0 = PXP_PATH(8U, 1U), /*!< MUX8 select output of alpha blending / color key 0. */ 0246 kPXP_Mux8SelectNone = PXP_PATH(8U, 2U), /*!< MUX8 select no output. */ 0247 kPXP_Mux9SelectMux0 = PXP_PATH(9U, 0U), /*!< MUX9 select output of MUX0. */ 0248 kPXP_Mux9SelectMux8 = PXP_PATH(9U, 1U), /*!< MUX9 select output of MUX8. */ 0249 kPXP_Mux9SelectNone = PXP_PATH(9U, 2U), /*!< MUX9 select no output. */ 0250 kPXP_Mux11SelectLut = PXP_PATH(11U, 0U), /*!< MUX11 select output of LUT. */ 0251 kPXP_Mux11SelectMux8 = PXP_PATH(11U, 1U), /*!< MUX11 select output of MUX8. */ 0252 kPXP_Mux11SelectNone = PXP_PATH(11U, 2U), /*!< MUX11 select no output. */ 0253 kPXP_Mux12SelectRotation0Engine = PXP_PATH(12U, 0U), /*!< MUX12 select output of Rotation0 engine. */ 0254 kPXP_Mux12SelectMux11 = PXP_PATH(12U, 1U), /*!< MUX12 select output of MUX11. */ 0255 kPXP_Mux12SelectNone = PXP_PATH(12U, 2U), /*!< MUX12 select no output. */ 0256 kPXP_Mux14SelectDitherEngine = PXP_PATH(14U, 0U), /*!< MUX14 select output of Dither engine. */ 0257 kPXP_Mux14SelectMux12 = PXP_PATH(14U, 1U), /*!< MUX14 select output of MUX12. */ 0258 kPXP_Mux14SelectNone = PXP_PATH(14U, 2U), /*!< MUX14 select no output. */ 0259 kPXP_Mux16SelectOutputBuffer = PXP_PATH(16U, 0U), /*!< MUX16 select output of output buffer. */ 0260 kPXP_Mux16SelectStoreEngine = PXP_PATH(16U, 1U), /*!< MUX16 select output of store engine. */ 0261 kPXP_Mux16SelectNone = PXP_PATH(16U, 2U), /*!< MUX16 select no output. */ 0262 kPXP_Mux17SelectOutputBuffer = PXP_PATH(17U, 0U), /*!< MUX17 select output of output buffer. */ 0263 kPXP_Mux17SelectStoreEngine = PXP_PATH(17U, 1U), /*!< MUX17 select output of store engine. */ 0264 kPXP_Mux17SelectNone = PXP_PATH(17U, 2U), /*!< MUX17 select no output. */ 0265 } pxp_path_t; 0266 #endif /* FSL_FEATURE_PXP_V3 */ 0267 #endif /* PXP_USE_PATH */ 0268 0269 /*! @brief PXP output flip mode. */ 0270 typedef enum _pxp_flip_mode 0271 { 0272 kPXP_FlipDisable = 0U, /*!< Flip disable. */ 0273 kPXP_FlipHorizontal = 0x01U, /*!< Horizontal flip. */ 0274 kPXP_FlipVertical = 0x02U, /*!< Vertical flip. */ 0275 kPXP_FlipBoth = 0x03U, /*!< Flip both directions. */ 0276 } pxp_flip_mode_t; 0277 0278 /*! @brief PXP rotate mode. */ 0279 typedef enum _pxp_rotate_position 0280 { 0281 kPXP_RotateOutputBuffer = 0U, /*!< Rotate the output buffer. */ 0282 kPXP_RotateProcessSurface, /*!< Rotate the process surface. */ 0283 } pxp_rotate_position_t; 0284 0285 /*! @brief PXP rotate degree. */ 0286 typedef enum _pxp_rotate_degree 0287 { 0288 kPXP_Rotate0 = 0U, /*!< Clock wise rotate 0 deg. */ 0289 kPXP_Rotate90, /*!< Clock wise rotate 90 deg. */ 0290 kPXP_Rotate180, /*!< Clock wise rotate 180 deg. */ 0291 kPXP_Rotate270, /*!< Clock wise rotate 270 deg. */ 0292 } pxp_rotate_degree_t; 0293 0294 /*! @brief PXP interlaced output mode. */ 0295 typedef enum _pxp_interlaced_output_mode 0296 { 0297 kPXP_OutputProgressive = 0U, /*!< All data written in progressive format to output buffer 0. */ 0298 kPXP_OutputField0, /*!< Only write field 0 data to output buffer 0. */ 0299 kPXP_OutputField1, /*!< Only write field 1 data to output buffer 0. */ 0300 kPXP_OutputInterlaced, /*!< Field 0 write to buffer 0, field 1 write to buffer 1. */ 0301 } pxp_interlaced_output_mode_t; 0302 0303 /*! @brief PXP output buffer format. */ 0304 typedef enum _pxp_output_pixel_format 0305 { 0306 kPXP_OutputPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */ 0307 kPXP_OutputPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ 0308 kPXP_OutputPixelFormatRGB888P = 0x5, /*!< 24-bit pixels without alpha (packed 24-bit format) */ 0309 kPXP_OutputPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */ 0310 kPXP_OutputPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */ 0311 kPXP_OutputPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ 0312 kPXP_OutputPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ 0313 kPXP_OutputPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ 0314 kPXP_OutputPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */ 0315 kPXP_OutputPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */ 0316 kPXP_OutputPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */ 0317 kPXP_OutputPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */ 0318 kPXP_OutputPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */ 0319 kPXP_OutputPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */ 0320 kPXP_OutputPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */ 0321 kPXP_OutputPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */ 0322 kPXP_OutputPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */ 0323 } pxp_output_pixel_format_t; 0324 0325 /*! @brief PXP output buffer configuration. */ 0326 typedef struct _pxp_output_buffer_config 0327 { 0328 pxp_output_pixel_format_t pixelFormat; /*!< Output buffer pixel format. */ 0329 pxp_interlaced_output_mode_t interlacedMode; /*!< Interlaced output mode. */ 0330 uint32_t buffer0Addr; /*!< Output buffer 0 address. */ 0331 uint32_t buffer1Addr; /*!< Output buffer 1 address, used for UV data in YUV 2-plane mode, or 0332 field 1 in output interlaced mode. */ 0333 uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */ 0334 uint16_t width; /*!< Pixels per line. */ 0335 uint16_t height; /*!< How many lines in output buffer. */ 0336 } pxp_output_buffer_config_t; 0337 0338 /*! @brief PXP process surface buffer pixel format. */ 0339 typedef enum _pxp_ps_pixel_format 0340 { 0341 kPXP_PsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ 0342 kPXP_PsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ 0343 kPXP_PsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ 0344 kPXP_PsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ 0345 kPXP_PsPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */ 0346 kPXP_PsPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */ 0347 kPXP_PsPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */ 0348 kPXP_PsPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */ 0349 kPXP_PsPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */ 0350 kPXP_PsPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */ 0351 kPXP_PsPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */ 0352 kPXP_PsPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */ 0353 kPXP_PsPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */ 0354 kPXP_PsPixelFormatYVU422 = 0x1E, /*!< 16-bit pixels (3-plane) */ 0355 kPXP_PsPixelFormatYVU420 = 0x1F, /*!< 16-bit pixels (3-plane) */ 0356 } pxp_ps_pixel_format_t; 0357 0358 /*! @brief PXP process surface buffer YUV format. */ 0359 typedef enum _pxp_ps_yuv_format 0360 { 0361 kPXP_PsYUVFormatYUV = 0U, /*!< YUV format. */ 0362 kPXP_PsYUVFormatYCbCr, /*!< YCbCr format. */ 0363 } pxp_ps_yuv_format_t; 0364 0365 /*! @brief PXP process surface buffer configuration. */ 0366 typedef struct _pxp_ps_buffer_config 0367 { 0368 pxp_ps_pixel_format_t pixelFormat; /*!< PS buffer pixel format. */ 0369 bool swapByte; /*!< For each 16 bit word, set true to swap the two bytes. */ 0370 uint32_t bufferAddr; /*!< Input buffer address for the first panel. */ 0371 uint32_t bufferAddrU; /*!< Input buffer address for the second panel. */ 0372 uint32_t bufferAddrV; /*!< Input buffer address for the third panel. */ 0373 uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */ 0374 } pxp_ps_buffer_config_t; 0375 0376 /*! @brief PXP alpha surface buffer pixel format. */ 0377 typedef enum _pxp_as_pixel_format 0378 { 0379 kPXP_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */ 0380 kPXP_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */ 0381 kPXP_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */ 0382 kPXP_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */ 0383 kPXP_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */ 0384 kPXP_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */ 0385 kPXP_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */ 0386 } pxp_as_pixel_format_t; 0387 0388 /*! @brief PXP alphs surface buffer configuration. */ 0389 typedef struct _pxp_as_buffer_config 0390 { 0391 pxp_as_pixel_format_t pixelFormat; /*!< AS buffer pixel format. */ 0392 uint32_t bufferAddr; /*!< Input buffer address. */ 0393 uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */ 0394 } pxp_as_buffer_config_t; 0395 0396 /*! 0397 * @brief PXP alpha mode during blending. 0398 */ 0399 typedef enum _pxp_alpha_mode 0400 { 0401 kPXP_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */ 0402 kPXP_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */ 0403 kPXP_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined 0404 alpha value will be used for blend, for example, pixel alpha set 0405 set to 200, user defined alpha set to 100, then the reault alpha 0406 is 200 * 100 / 255. */ 0407 kPXP_AlphaRop /*!< Raster operation. */ 0408 } pxp_alpha_mode_t; 0409 0410 /*! 0411 * @brief PXP ROP mode during blending. 0412 * 0413 * Explanation: 0414 * - AS: Alpha surface 0415 * - PS: Process surface 0416 * - nAS: Alpha surface NOT value 0417 * - nPS: Process surface NOT value 0418 */ 0419 typedef enum _pxp_rop_mode 0420 { 0421 kPXP_RopMaskAs = 0x0, /*!< AS AND PS. */ 0422 kPXP_RopMaskNotAs = 0x1, /*!< nAS AND PS. */ 0423 kPXP_RopMaskAsNot = 0x2, /*!< AS AND nPS. */ 0424 kPXP_RopMergeAs = 0x3, /*!< AS OR PS. */ 0425 kPXP_RopMergeNotAs = 0x4, /*!< nAS OR PS. */ 0426 kPXP_RopMergeAsNot = 0x5, /*!< AS OR nPS. */ 0427 kPXP_RopNotCopyAs = 0x6, /*!< nAS. */ 0428 kPXP_RopNot = 0x7, /*!< nPS. */ 0429 kPXP_RopNotMaskAs = 0x8, /*!< AS NAND PS. */ 0430 kPXP_RopNotMergeAs = 0x9, /*!< AS NOR PS. */ 0431 kPXP_RopXorAs = 0xA, /*!< AS XOR PS. */ 0432 kPXP_RopNotXorAs = 0xB /*!< AS XNOR PS. */ 0433 } pxp_rop_mode_t; 0434 0435 /*! 0436 * @brief PXP alpha surface blending configuration. 0437 */ 0438 typedef struct _pxp_as_blend_config 0439 { 0440 uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kPXP_AlphaOverride or @ref 0441 kPXP_AlphaRop. */ 0442 bool invertAlpha; /*!< Set true to invert the alpha. */ 0443 pxp_alpha_mode_t alphaMode; /*!< Alpha mode. */ 0444 pxp_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kPXP_AlphaRop. */ 0445 } pxp_as_blend_config_t; 0446 0447 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 0448 /*! 0449 * @brief PXP secondary alpha surface blending engine configuration. 0450 */ 0451 typedef struct _pxp_as_blend_secondary_config 0452 { 0453 bool invertAlpha; /*!< Set true to invert the alpha. */ 0454 bool ropEnable; /*!< Enable rop mode. */ 0455 pxp_rop_mode_t ropMode; /*!< ROP mode, only valid when ropEnable is true. */ 0456 } pxp_as_blend_secondary_config_t; 0457 #endif /* FSL_FEATURE_PXP_V3 */ 0458 0459 /*! @brief PXP process block size. */ 0460 typedef enum _pxp_block_size 0461 { 0462 kPXP_BlockSize8 = 0U, /*!< Process 8x8 pixel blocks. */ 0463 kPXP_BlockSize16, /*!< Process 16x16 pixel blocks. */ 0464 } pxp_block_size_t; 0465 0466 /*! @brief PXP CSC1 mode. */ 0467 typedef enum _pxp_csc1_mode 0468 { 0469 kPXP_Csc1YUV2RGB = 0U, /*!< YUV to RGB. */ 0470 kPXP_Csc1YCbCr2RGB, /*!< YCbCr to RGB. */ 0471 } pxp_csc1_mode_t; 0472 0473 /*! @brief PXP CSC2 mode. */ 0474 typedef enum _pxp_csc2_mode 0475 { 0476 kPXP_Csc2YUV2RGB = 0U, /*!< YUV to RGB. */ 0477 kPXP_Csc2YCbCr2RGB, /*!< YCbCr to RGB. */ 0478 kPXP_Csc2RGB2YUV, /*!< RGB to YUV. */ 0479 kPXP_Csc2RGB2YCbCr, /*!< RGB to YCbCr. */ 0480 } pxp_csc2_mode_t; 0481 0482 /*! 0483 * @brief PXP CSC2 configuration. 0484 * 0485 * Converting from YUV/YCbCr color spaces to the RGB color space uses the 0486 * following equation structure: 0487 * 0488 * R = A1(Y+D1) + A2(U+D2) + A3(V+D3) 0489 * G = B1(Y+D1) + B2(U+D2) + B3(V+D3) 0490 * B = C1(Y+D1) + C2(U+D2) + C3(V+D3) 0491 * 0492 * Converting from the RGB color space to YUV/YCbCr color spaces uses the 0493 * following equation structure: 0494 * 0495 * Y = A1*R + A2*G + A3*B + D1 0496 * U = B1*R + B2*G + B3*B + D2 0497 * V = C1*R + C2*G + C3*B + D3 0498 */ 0499 typedef struct _pxp_csc2_config 0500 { 0501 pxp_csc2_mode_t mode; /*!< Convertion mode. */ 0502 float A1; /*!< A1. */ 0503 float A2; /*!< A2. */ 0504 float A3; /*!< A3. */ 0505 float B1; /*!< B1. */ 0506 float B2; /*!< B2. */ 0507 float B3; /*!< B3. */ 0508 float C1; /*!< C1. */ 0509 float C2; /*!< C2. */ 0510 float C3; /*!< C3. */ 0511 int16_t D1; /*!< D1. */ 0512 int16_t D2; /*!< D2. */ 0513 int16_t D3; /*!< D3. */ 0514 } pxp_csc2_config_t; 0515 0516 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) 0517 /*! @brief PXP LUT lookup mode. */ 0518 typedef enum _pxp_lut_lookup_mode 0519 { 0520 kPXP_LutCacheRGB565 = 0U, /*!< LUT ADDR = R[7:3],G[7:2],B[7:3]. Use all 16KB of LUT 0521 for indirect cached 128KB lookup. */ 0522 kPXP_LutDirectY8, /*!< LUT ADDR = 16'b0,Y[7:0]. Use the first 256 bytes of LUT. 0523 Only third data path byte is tranformed. */ 0524 kPXP_LutDirectRGB444, /*!< LUT ADDR = R[7:4],G[7:4],B[7:4]. Use one 8KB bank of LUT 0525 selected by @ref PXP_Select8kLutBank. */ 0526 kPXP_LutDirectRGB454, /*!< LUT ADDR = R[7:4],G[7:3],B[7:4]. Use all 16KB of LUT. */ 0527 } pxp_lut_lookup_mode_t; 0528 0529 /*! @brief PXP LUT output mode. */ 0530 typedef enum _pxp_lut_out_mode 0531 { 0532 kPXP_LutOutY8 = 1U, /*!< R/Y byte lane 2 lookup, bytes 1,0 bypassed. */ 0533 kPXP_LutOutRGBW4444CFA, /*!< Byte lane 2 = CFA_Y8, byte lane 1,0 = RGBW4444. */ 0534 kPXP_LutOutRGB888, /*!< RGB565->RGB888 conversion for Gamma correction. */ 0535 } pxp_lut_out_mode_t; 0536 0537 /*! @brief PXP LUT 8K bank index used when lookup mode is @ref kPXP_LutDirectRGB444. */ 0538 typedef enum _pxp_lut_8k_bank 0539 { 0540 kPXP_Lut8kBank0 = 0U, /*!< The first 8K bank used. */ 0541 kPXP_Lut8kBank1, /*!< The second 8K bank used. */ 0542 } pxp_lut_8k_bank_t; 0543 0544 /*! @brief PXP LUT configuration. */ 0545 typedef struct _pxp_lut_config 0546 { 0547 pxp_lut_lookup_mode_t lookupMode; /*!< Look up mode. */ 0548 pxp_lut_out_mode_t outMode; /*!< Out mode. */ 0549 uint32_t cfaValue; /*!< The CFA value used when look up mode is @ref kPXP_LutOutRGBW4444CFA. */ 0550 } pxp_lut_config_t; 0551 #endif /* FSL_FEATURE_PXP_HAS_NO_LUT */ 0552 0553 /*! @brief PXP internal memory. */ 0554 typedef enum _pxp_ram 0555 { 0556 kPXP_RamDither0Lut = 0U, /*!< Dither 0 LUT memory. */ 0557 kPXP_RamDither1Lut = 3U, /*!< Dither 1 LUT memory. */ 0558 kPXP_RamDither2Lut = 4U, /*!< Dither 2 LUT memory. */ 0559 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 0560 kPXP_RamDither0Err0 = 1U, /*!< Dither 0 ERR0 memory. */ 0561 kPXP_RamDither0Err1 = 2U, /*!< Dither 0 ERR1 memory. */ 0562 kPXP_RamAluA = 5U, /*!< ALU A instr memory. */ 0563 kPXP_RamAluB = 6U, /*!< ALU B instr memory. */ 0564 kPXP_WfeAFetch = 7U, /*!< WFE-A fetch memory. */ 0565 kPXP_WfeBFetch = 8U, /*!< WFE-B fetch memory. */ 0566 #endif /* FSL_FEATURE_PXP_V3 */ 0567 } pxp_ram_t; 0568 0569 /*! @brief PXP dither mode. */ 0570 enum _pxp_dither_mode 0571 { 0572 kPXP_DitherPassThrough = 0U, /*!< Pass through, no dither. */ 0573 kPXP_DitherFloydSteinberg = 1U, /*!< Floyd-Steinberg. For dither engine 0 only. */ 0574 kPXP_DitherAtkinson = 2U, /*!< Atkinson. For dither engine 0 only. */ 0575 kPXP_DitherOrdered = 3U, /*!< Ordered dither. */ 0576 kPXP_DitherQuantOnly = 4U, /*!< No dithering, only quantization. */ 0577 kPXP_DitherSierra = 5U, /*!< Sierra. For dither engine 0 only. */ 0578 }; 0579 0580 /*! @brief PXP dither LUT mode. */ 0581 enum _pxp_dither_lut_mode 0582 { 0583 kPXP_DitherLutOff = 0U, /*!< The LUT memory is not used for LUT, could be used as ordered dither index matrix. */ 0584 kPXP_DitherLutPreDither, /*!< Use LUT at the pre-dither stage, The pre-dither LUT could only be used in Floyd mode 0585 or Atkinson mode, which are not supported by current PXP module. */ 0586 kPXP_DitherLutPostDither, /*!< Use LUT at the post-dither stage. */ 0587 }; 0588 0589 /*! @brief PXP dither matrix size. */ 0590 enum _pxp_dither_matrix_size 0591 { 0592 kPXP_DitherMatrix4 = 0, /*!< The dither index matrix is 4x4. */ 0593 kPXP_DitherMatrix8, /*!< The dither index matrix is 8x8. */ 0594 kPXP_DitherMatrix16, /*!< The dither index matrix is 16x16. */ 0595 }; 0596 0597 /*! @brief PXP dither final LUT data. */ 0598 typedef struct _pxp_dither_final_lut_data 0599 { 0600 uint32_t data_3_0; /*!< Data 3 to data 0. Data 0 is the least significant byte. */ 0601 uint32_t data_7_4; /*!< Data 7 to data 4. Data 4 is the least significant byte. */ 0602 uint32_t data_11_8; /*!< Data 11 to data 8. Data 8 is the least significant byte. */ 0603 uint32_t data_15_12; /*!< Data 15 to data 12. Data 12 is the least significant byte. */ 0604 } pxp_dither_final_lut_data_t; 0605 0606 /*! @brief PXP dither configuration. */ 0607 typedef struct _pxp_dither_config 0608 { 0609 uint32_t enableDither0 : 1; /*!< Enable dither engine 0 or not, set 1 to enable, 0 to disable. */ 0610 uint32_t enableDither1 : 1; /*!< Enable dither engine 1 or not, set 1 to enable, 0 to disable. */ 0611 uint32_t enableDither2 : 1; /*!< Enable dither engine 2 or not, set 1 to enable, 0 to disable. */ 0612 uint32_t ditherMode0 : 3; /*!< Dither mode for dither engine 0. See @ref _pxp_dither_mode. */ 0613 uint32_t ditherMode1 : 3; /*!< Dither mode for dither engine 1. See @ref _pxp_dither_mode. */ 0614 uint32_t ditherMode2 : 3; /*!< Dither mode for dither engine 2. See @ref _pxp_dither_mode. */ 0615 uint32_t quantBitNum : 3; /*!< Number of bits quantize down to, the valid value is 1~7. */ 0616 uint32_t lutMode : 2; /*!< How to use the memory LUT, see @ref _pxp_dither_lut_mode. This must be set to @ref 0617 kPXP_DitherLutOff 0618 if any dither engine uses @ref kPXP_DitherOrdered mode. */ 0619 uint32_t idxMatrixSize0 : 2; /*!< Size of index matrix used for dither for dither engine 0, see @ref 0620 _pxp_dither_matrix_size. */ 0621 uint32_t idxMatrixSize1 : 2; /*!< Size of index matrix used for dither for dither engine 1, see @ref 0622 _pxp_dither_matrix_size. */ 0623 uint32_t idxMatrixSize2 : 2; /*!< Size of index matrix used for dither for dither engine 2, see @ref 0624 _pxp_dither_matrix_size. */ 0625 uint32_t enableFinalLut : 1; /*!< Enable the final LUT, set 1 to enable, 0 to disable. */ 0626 uint32_t : 8; 0627 } pxp_dither_config_t; 0628 0629 /*! 0630 * @brief Porter Duff factor mode. 0631 * @anchor pxp_porter_duff_factor_mode 0632 */ 0633 enum 0634 { 0635 kPXP_PorterDuffFactorOne = 0U, /*!< Use 1. */ 0636 kPXP_PorterDuffFactorZero, /*!< Use 0. */ 0637 kPXP_PorterDuffFactorStraight, /*!< Use straight alpha. */ 0638 kPXP_PorterDuffFactorInversed, /*!< Use inversed alpha. */ 0639 }; 0640 0641 /*! 0642 * @brief Porter Duff global alpha mode. 0643 * @anchor pxp_porter_duff_global_alpha_mode 0644 */ 0645 enum 0646 { 0647 kPXP_PorterDuffGlobalAlpha = 0U, /*!< Use global alpha. */ 0648 kPXP_PorterDuffLocalAlpha, /*!< Use local alpha in each pixel. */ 0649 kPXP_PorterDuffScaledAlpha, /*!< Use global alpha * local alpha. */ 0650 }; 0651 0652 /*! 0653 * @brief Porter Duff alpha mode. 0654 * @anchor pxp_porter_duff_alpha_mode 0655 */ 0656 enum 0657 { 0658 kPXP_PorterDuffAlphaStraight = 0U, /*!< Use straight alpha, s0_alpha' = s0_alpha. */ 0659 kPXP_PorterDuffAlphaInversed /*!< Use inversed alpha, s0_alpha' = 0xFF - s0_alpha. */ 0660 }; 0661 0662 /*! 0663 * @brief Porter Duff color mode. 0664 * @anchor pxp_porter_duff_color_mode 0665 */ 0666 enum 0667 { 0668 kPXP_PorterDuffColorStraight = 0, /*!< @deprecated Use kPXP_PorterDuffColorNoAlpha. */ 0669 kPXP_PorterDuffColorInversed = 1, /*!< @deprecated Use kPXP_PorterDuffColorWithAlpha. */ 0670 kPXP_PorterDuffColorNoAlpha = 0, /*!< s0_pixel' = s0_pixel. */ 0671 kPXP_PorterDuffColorWithAlpha = 1, /*!< s0_pixel' = s0_pixel * s0_alpha". */ 0672 }; 0673 0674 /*! @brief PXP Porter Duff configuration. */ 0675 typedef struct 0676 { 0677 uint32_t enable : 1; /*!< Enable or disable Porter Duff. */ 0678 uint32_t srcFactorMode : 2; /*!< Source layer (or AS, s1) factor mode, see @ref pxp_porter_duff_factor_mode. */ 0679 uint32_t dstGlobalAlphaMode : 2; /*!< Destination layer (or PS, s0) global alpha mode, see 0680 @ref pxp_porter_duff_global_alpha_mode. */ 0681 uint32_t dstAlphaMode : 1; /*!< Destination layer (or PS, s0) alpha mode, see @ref pxp_porter_duff_alpha_mode. */ 0682 uint32_t dstColorMode : 1; /*!< Destination layer (or PS, s0) color mode, see @ref pxp_porter_duff_color_mode. */ 0683 uint32_t : 1; 0684 uint32_t dstFactorMode : 2; /*!< Destination layer (or PS, s0) factor mode, see @ref pxp_porter_duff_factor_mode. */ 0685 uint32_t srcGlobalAlphaMode : 2; /*!< Source layer (or AS, s1) global alpha mode, see 0686 @ref pxp_porter_duff_global_alpha_mode. */ 0687 uint32_t srcAlphaMode : 1; /*!< Source layer (or AS, s1) alpha mode, see @ref pxp_porter_duff_alpha_mode. */ 0688 uint32_t srcColorMode : 1; /*!< Source layer (or AS, s1) color mode, see @ref pxp_porter_duff_color_mode. */ 0689 uint32_t : 2; 0690 uint32_t dstGlobalAlpha : 8; /*!< Destination layer (or PS, s0) global alpha value, 0~255. */ 0691 uint32_t srcGlobalAlpha : 8; /*!< Source layer (or AS, s1) global alpha value, 0~255. */ 0692 } pxp_porter_duff_config_t; 0693 0694 /*! @brief PXP Porter Duff blend mode. Note: don't change the enum item value */ 0695 typedef enum _pxp_porter_duff_blend_mode 0696 { 0697 kPXP_PorterDuffSrc = 0, /*!< Source Only */ 0698 kPXP_PorterDuffAtop, /*!< Source Atop */ 0699 kPXP_PorterDuffOver, /*!< Source Over */ 0700 kPXP_PorterDuffIn, /*!< Source In. */ 0701 kPXP_PorterDuffOut, /*!< Source Out. */ 0702 kPXP_PorterDuffDst, /*!< Destination Only. */ 0703 kPXP_PorterDuffDstAtop, /*!< Destination Atop. */ 0704 kPXP_PorterDuffDstOver, /*!< Destination Over. */ 0705 kPXP_PorterDuffDstIn, /*!< Destination In. */ 0706 kPXP_PorterDuffDstOut, /*!< Destination Out. */ 0707 kPXP_PorterDuffXor, /*!< XOR. */ 0708 kPXP_PorterDuffClear, /*!< Clear. */ 0709 kPXP_PorterDuffMax, 0710 } pxp_porter_duff_blend_mode_t; 0711 0712 /*! @brief PXP Porter Duff blend mode. Note: don't change the enum item value */ 0713 typedef struct _pxp_pic_copy_config 0714 { 0715 uint32_t srcPicBaseAddr; /*!< Source picture base address. */ 0716 uint16_t srcPitchBytes; /*!< Pitch of the source buffer. */ 0717 uint16_t srcOffsetX; /*!< Copy position in source picture. */ 0718 uint16_t srcOffsetY; /*!< Copy position in source picture. */ 0719 uint32_t destPicBaseAddr; /*!< Destination picture base address. */ 0720 uint16_t destPitchBytes; /*!< Pitch of the destination buffer. */ 0721 uint16_t destOffsetX; /*!< Copy position in destination picture. */ 0722 uint16_t destOffsetY; /*!< Copy position in destination picture. */ 0723 uint16_t width; /*!< Pixel number each line to copy. */ 0724 uint16_t height; /*!< Lines to copy. */ 0725 pxp_as_pixel_format_t pixelFormat; /*!< Buffer pixel format. */ 0726 } pxp_pic_copy_config_t; 0727 0728 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 0729 0730 /*! 0731 * @brief PXP process engine enumeration 0732 */ 0733 typedef enum _pxp_process_engine_name 0734 { 0735 kPXP_PsAsOutEngine = PXP_CTRL_ENABLE_PS_AS_OUT_MASK, 0736 kPXP_DitherEngine = PXP_CTRL_ENABLE_DITHER_MASK, 0737 kPXP_WfeaEngine = PXP_CTRL_ENABLE_WFE_A_MASK, 0738 kPXP_WfebEngine = PXP_CTRL_ENABLE_WFE_B_MASK, 0739 kPXP_InputFetchStoreEngine = PXP_CTRL_ENABLE_INPUT_FETCH_STORE_MASK, 0740 kPXP_Alpha1Engine = PXP_CTRL_ENABLE_ALPHA_B_MASK, 0741 kPXP_Csc2Engine = PXP_CTRL_ENABLE_CSC2_MASK, 0742 kPXP_LutEngine = PXP_CTRL_ENABLE_LUT_MASK, 0743 kPXP_Rotate0Engine = PXP_CTRL_ENABLE_ROTATE0_MASK, 0744 kPXP_Rotate1Engine = PXP_CTRL_ENABLE_ROTATE1_MASK, 0745 } pxp_process_engine_name_t; 0746 0747 /* Fetch engine configuration. */ 0748 /*! 0749 * @brief PXP fetch engine enumeration 0750 * 0751 * There are actually 4 fetch engine implemented, the others are WFE-A fetch engine and WFE-B fetch engine, 0752 * whose registers are reserved from developer. 0753 */ 0754 typedef enum _pxp_fetch_engine_name 0755 { 0756 kPXP_FetchInput, 0757 kPXP_FetchDither, 0758 } pxp_fetch_engine_name_t; 0759 0760 /*! @brief PXP fetch engine interface mode with the upstream store engine. */ 0761 typedef enum _pxp_fetch_interface_mode 0762 { 0763 kPXP_FetchModeNormal = 0U, 0764 kPXP_FetchModeHandshake = 0x1U, 0765 kPXP_FetchModeBypass = 0x2U, 0766 } pxp_fetch_interface_mode_t; 0767 0768 /*! @brief PXP fetch/store engine burst length for scanline mode. */ 0769 typedef enum _pxp_scanline_burst 0770 { 0771 kPXP_Scanline8bytes, 0772 kPXP_Scanline16bytes, 0773 kPXP_Scanline32bytes, 0774 kPXP_Scanline64bytes, 0775 } pxp_scanline_burst_t; 0776 0777 /*! @brief PXP fetch engine block configuration. */ 0778 typedef struct _pxp_block_format_config 0779 { 0780 bool 0781 enableblock; /*!< Enable to use block mode instead of scanline mode. Note: 1.Make sure to enable if rotate or 0782 flip mode is enabled. 2.Block mode cannot work on 64bpp data stream where activeBits = 64. 3. If 0783 LUT processing is in the path between the fetch and store engind, block mode must be enabled. */ 0784 bool blockSize16; /*!< Enable to use 16*16 block, otherwise it will be 8*8 block. */ 0785 pxp_scanline_burst_t burstLength; /*!< When using scanline mode, configure this for burst length. */ 0786 } pxp_block_config_t; 0787 0788 /*! 0789 * @brief PXP fetch/store engine input/output active bits configuration. 0790 * 0791 * Since fetch engine is 64-bit input and 32-bit output per channel, need to configure both channels to use 64-bit input 0792 * mode. And expand configuration will have no effect. 0793 */ 0794 typedef enum _pxp_activeBits 0795 { 0796 kPXP_Active8Bits = 0x0, 0797 kPXP_Active16Bits = 0x1, 0798 kPXP_Active32Bits = 0x2, 0799 kPXP_Active64Bits = 0x3, 0800 } pxp_active_bits_t; 0801 0802 /*! @brief PXP fetch engine output word order when using 2 channels for 64-bit mode. */ 0803 typedef enum _pxp_fetch_output_word_order 0804 { 0805 kPXP_FetchOutputChannel1channel0 = 0x0, /*!< In 64bit mode, channel 1 output high byte. */ 0806 kPXP_FetchOutputChannel0channel1 = 0x1, /*!< In 64bit mode, channel 0 output high byte. */ 0807 } pxp_fetch_output_word_order_t; 0808 0809 /*! 0810 * @brief PXP fetch engine shift component configuration. 0811 * 0812 * Fetch engine can divded each word into 4 components and shift them. 0813 */ 0814 typedef struct _pxp_fetch_shift_component 0815 { 0816 uint8_t offset; 0817 uint8_t width; 0818 } pxp_fetch_shift_component_t; 0819 0820 /*! 0821 * @brief PXP fetch engine shift configuration. 0822 * 0823 * Fetch engine can divded each word into 4 components and shift them. 0824 * For example, to change YUV444 to YVU444, U and V positions need to be shifted: OFFSET0=8, OFFSET1=0, OFFSET2=16, 0825 * OFFSET3=24, WIDTH0/1/2/3=8 0826 */ 0827 typedef struct _pxp_fetch_shift_config 0828 { 0829 bool shiftBypass; /* Bypass the shift */ 0830 pxp_fetch_shift_component_t component0; 0831 pxp_fetch_shift_component_t component1; 0832 pxp_fetch_shift_component_t component2; 0833 pxp_fetch_shift_component_t component3; 0834 } pxp_fetch_shift_config_t; 0835 0836 /*! @brief PXP fetch engine input pixel format. */ 0837 typedef enum _pxp_fetch_pixel_format 0838 { 0839 kPXP_FetchFormatRGB565 = 0x0, 0840 kPXP_FetchFormatRGB555 = 0x1, 0841 kPXP_FetchFormatARGB1555 = 0x2, 0842 kPXP_FetchFormatRGB444 = 0x3, 0843 kPXP_FetchFormatARGB4444 = 0x4, 0844 kPXP_FetchFormatYUYVorYVYU = 0x5, 0845 kPXP_FetchFormatUYVYorVYUY = 0x6, 0846 kPXP_FetchFormatYUV422_2P = 0x7, 0847 } pxp_fetch_pixel_format_t; 0848 0849 /*! @brief PXP fetch engine configuration for one of the channel. */ 0850 typedef struct _pxp_fetch_engine_config 0851 { 0852 bool channelEnable; /*!< Enable channel. */ 0853 /* Address configuration */ 0854 uint32_t inputBaseAddr0; /*!< The input base address. Used for Y plane input when pixel format is YUV422_2p. */ 0855 uint32_t inputBaseAddr1; /*!< Must configure this for UV plane when input pixel format is YUV422_2p. */ 0856 /* Size configuration */ 0857 uint16_t totalHeight; /*!< Total height for the actual fetch size. */ 0858 uint16_t totalWidth; /*!< Total width for the actual fetch size. */ 0859 uint16_t pitchBytes; /*!< Channel input pitch */ 0860 uint16_t 0861 ulcX; /*!< X coordinate of upper left coordinate in pixels of the active surface of the total input memory */ 0862 uint16_t 0863 ulcY; /*!< Y coordinate of upper left coordinate in pixels of the active surface of the total input memory */ 0864 uint16_t 0865 lrcX; /*!< X coordinate of Lower right coordinate in pixels of the active surface of the total input memory */ 0866 uint16_t 0867 lrcY; /*!< Y coordinate of Lower right coordinate in pixels of the active surface of the total input memory */ 0868 /* Interface configuration */ 0869 pxp_fetch_interface_mode_t interface; /*!< Interface mode, normal/bypass/handshake */ 0870 /* Pixel configuration */ 0871 pxp_active_bits_t activeBits; /*!< Input active bits. */ 0872 pxp_fetch_pixel_format_t pixelFormat; /*!< Input pixel fetch format */ 0873 bool expandEnable; /*!< If enabled, input pixel will be expanded to ARGB8888, RGB888 or YUV444 of 32-bit format at 0874 the output. */ 0875 /* Fetch format configuration */ 0876 pxp_flip_mode_t flipMode; /*!< Flip the fetched input. */ 0877 pxp_rotate_degree_t rotateDegree; /*!< Rotate the fetched input. */ 0878 pxp_block_config_t 0879 fetchFormat; /*!< Block mode configuration. Make sure to enable block if rotate or flip mode is enabled. */ 0880 /* Output configuration. */ 0881 pxp_fetch_shift_config_t shiftConfig; /*!< Shift operation configuration. */ 0882 pxp_fetch_output_word_order_t wordOrder; /*!< Output word order when using 2 channels for 64-bit mode. */ 0883 } pxp_fetch_engine_config_t; 0884 0885 /* Store engine configuration. */ 0886 0887 /*! 0888 * @brief PXP store engine enumeration 0889 * 0890 * There are actually 4 store engine implemented, the others are WFE-A store engine and WFE-B store engine, 0891 * whose registers are reserved from developer. 0892 */ 0893 typedef enum _pxp_store_engine_name 0894 { 0895 kPXP_StoreInput, 0896 kPXP_StoreDither, 0897 } pxp_store_engine_name_t; 0898 0899 /*! @brief PXP store engine interface mode with the downstream fetch engine. */ 0900 typedef enum _pxp_store_interface_mode 0901 { 0902 kPXP_StoreModeBypass = 0x20U, 0903 kPXP_StoreModeNormal = 0x40U, 0904 kPXP_StoreModeHandshake = 0x43U, 0905 kPXP_StoreModeDual = 0x60U, /*!< Store engine outputs data directly to downstream fetch engine(Bypass) but also 0906 storing it to memory at the same time. */ 0907 } pxp_store_interface_mode_t; 0908 0909 /*! @brief PXP store engine YUV output mode. */ 0910 typedef enum _pxp_store_yuv_mode 0911 { 0912 kPXP_StoreYUVDisable = 0U, /*!< Do not output YUV pixel format. */ 0913 kPXP_StoreYUVPlane1 = 0914 0x1U, /*!< Use channel to output YUV422_1p pixel format, need to use shift operation to make sure each pixel 0915 component in its proper position: 64-bits of pixel data format and each 32 bits as {Y0, U0, Y1, V0}. */ 0916 kPXP_StoreYUVPlane2 = 0917 0x2U, /*!< Use channel to output YUV422_2p pixel format, need to use shift operation to make sure each pixel 0918 component in its proper position: channel 0 {Y0,Y1}, channel 1 {U0,V0}. */ 0919 } pxp_store_yuv_mode_t; 0920 0921 /*! @brief Shift configuration for PXP store engine. */ 0922 typedef struct _pxp_store_shift_config 0923 { 0924 /* Data/Flag shift */ 0925 bool shiftBypass; /*!< Bypass the data shift */ 0926 uint64_t *pDataShiftMask; /*!< Pointer to mask0~mask7 to mask the 64-bit of output data, data is masked first then 0927 shifted according to width. */ 0928 uint8_t *pDataShiftWidth; /*!< Pointer to width0~width7. Bit 7 is for shifted direction, 0 to right. Bit0~5 is for 0929 shift width. */ 0930 uint8_t *pFlagShiftMask; /*!< Pointer to mask0~mask7 to mask the 8-bit of output flag, flag is masked first then 0931 shifted according to width. */ 0932 uint8_t *pFlagShiftWidth; /*!< Pointer to width0~width7. Bit 6 is for shifted direction, 0 to right. Bit0~5 is for 0933 shift width. */ 0934 } pxp_store_shift_config_t; 0935 0936 /*! @brief PXP store engine configuration for one of the channel. */ 0937 typedef struct _pxp_store_engine_config 0938 { 0939 bool channelEnable; /*!< Enable channel. */ 0940 /* Address configuration */ 0941 uint32_t outputBaseAddr0; /*!< The channel 0 output address if using 2 channels. If using 1 channel(must be channel 0942 0) and YUV422_2p output format, is for Y plane address. */ 0943 uint32_t outputBaseAddr1; /*!< The channel 1 output address if using 2 channels. If using 1 channel(must be channel 0944 0) and YUV422_2p output format, is for UV plane address. */ 0945 /* Size configuration */ 0946 uint16_t totalHeight; /*!< Total height for the actual store size. */ 0947 uint16_t totalWidth; /*!< Total width for the actual store size. */ 0948 uint16_t pitchBytes; /*!< Channel input pitch */ 0949 /* Interface configuration */ 0950 pxp_store_interface_mode_t interface; /*!< Interface mode, normal/bypass/handshake/dual. Make sure 2 channels use 0951 the same mode if both enabled. */ 0952 /* pxp_store_handshake_array_t arraySize; !< If interfase mode is handshake, need to configure the array size. When 0953 block is disabled, the scanline can only be 1. TODO no need now. */ 0954 /* Pixel configuration */ 0955 pxp_active_bits_t activeBits; /*!< Output active bits. */ 0956 pxp_store_yuv_mode_t yuvMode; /*!< Whether to output YUV pixel format. */ 0957 /* Fixed data configuration, only apply for channel 0. */ 0958 bool useFixedData; /*!< Whether to use fixed value for the output data. Can be used to write fixed value to specific 0959 memory location for memory initialization. */ 0960 uint32_t fixedData; /*!< The value of the fixed data. */ 0961 /* Data packing */ 0962 bool packInSelect; /*!< When enabled, channel 0 will select low 32 bit shift out data to pack while channel i select 0963 high 32 bit, otherwise all 64bit of data will be selected. */ 0964 /* Data store format */ 0965 pxp_block_config_t storeFormat; /*!< The format to store data, block or otherwise. */ 0966 pxp_store_shift_config_t shiftConfig; /*!< Shift operation configuration. */ 0967 } pxp_store_engine_config_t; 0968 0969 /* Pre-dither CFA engine configuration */ 0970 0971 /*! @brief PXP pre-dither CFA engine input pixel format. */ 0972 typedef enum _pxp_cfa_input_format 0973 { 0974 kPXP_CfaRGB888, 0975 kPXP_CfaRGB444, 0976 } pxp_cfa_input_format_t; 0977 0978 /*! @brief PXP pre-dither CFA engine configuration. */ 0979 typedef struct _pxp_cfa_config 0980 { 0981 bool bypass; /*!< Bypass the CFA process */ 0982 pxp_cfa_input_format_t pixelInFormat; /*!< The pixel input format for CFA. */ 0983 uint8_t arrayWidth; /*!< CFA array vertical size in pixels, min 3 max 15. */ 0984 uint8_t arrayHeight; /*!< CFA array horizontal size in pixels, min 3 max 15. */ 0985 uint16_t totalHeight; /*!< Total height for the buffer size, make sure it is aligned with the dither fetch engine 0986 and dither engine. */ 0987 uint16_t totalWidth; /*!< Total width for the buffer size, make sure it is aligned with the dither fetch engine and 0988 dither engine. */ 0989 uint32_t *cfaValue; /*!< Pointer to the value for the CFA array. 2-bit per component: 00-R,01-G,10-B,11-W. For a 4x4 0990 array, 32 bits are need. */ 0991 } pxp_cfa_config_t; 0992 0993 /* Histogram configuration and status */ 0994 0995 /*! @brief PXP histogram mask condition. */ 0996 typedef enum _pxp_histogram_mask_condition 0997 { 0998 kPXP_HistogramMaskEqual = 0x0U, /*!< Value that equal to value0 will pass the mask operation. */ 0999 kPXP_HistogramMaskNotequal = 0x1U, /*!< Value that not equal to value0 will pass the mask operation. */ 1000 kPXP_HistogramMaskIn = 0x2U, /*!< Value that within the range of value0-value1 will pass the mask operation. */ 1001 kPXP_HistogramMaskOut = 0x3U, /*!< Value that without the range of value0-value1 will pass the mask operation. */ 1002 } pxp_histogram_mask_condition_t; 1003 1004 /*! @brief PXP Histogram configuration. */ 1005 typedef struct _pxp_histogram_config 1006 { 1007 bool enable; /*!< Enable histogram process. */ 1008 uint8_t *pParamValue; /*!< Pointer to the 62(2+4+8+16+32) byte of param value for 2-level, 4-level.....32-level 1009 parameters. Only low 5-bit of each byte is valid. */ 1010 uint8_t lutValueOffset; /*!< The starting bit position of the LUT value. */ 1011 uint8_t lutValueWidth; /*!< The bit width of the LUT value, should be no more than 6 bits since only 63 LUTs are 1012 supported. */ 1013 /* Mask configuration */ 1014 bool enableMask; /*!< Enable mask operation. */ 1015 uint8_t maskValue0; /*!< Value 0 for the condition judgement. */ 1016 uint8_t maskValue1; /*!< Value 1 for the condition judgement. */ 1017 uint8_t maskOffset; /*!< The starting bit position of the field to be checked against mask condition. */ 1018 uint8_t maskWidth; /*!< The width of the field to be checked against mask condition. */ 1019 pxp_histogram_mask_condition_t condition; /*!< The mask condition. */ 1020 /* Size configuration */ 1021 uint16_t totalHeight; /*!< Total height for the buffer size, make sure it is aligned with the output of legacy flow 1022 or the WFE-A/B engine. */ 1023 uint16_t totalWidth; /*!< Total width for the buffer size, make sure it is aligned with the output of legacy flow or 1024 the WFE-A/B engine. */ 1025 } pxp_histogram_config_t; 1026 1027 /*! @brief PXP Histogram mask result. */ 1028 typedef struct _pxp_histogram_mask_result 1029 { 1030 uint32_t pixelCount; /*!< The total count of the pixels that pass the mask(collided pixels). */ 1031 uint32_t minX; /*!< The x offset of the ULC of the minimal histogram that covers all passed pixels. */ 1032 uint32_t minY; /*!< The y offset of the ULC of the minimal histogram that covers all passed pixels. */ 1033 uint32_t maxX; /*!< The x offset of the LRC of the minimal histogram that covers all passed pixels. */ 1034 uint32_t maxY; /*!< The y offset of the LRC of the minimal histogram that covers all passed pixels. */ 1035 uint64_t lutlist; /*!< The 64-bit LUT list of collided pixels, if pixel of LUT17 is collided, bit17 in the list is 1036 set. */ 1037 } pxp_histogram_mask_result_t; 1038 1039 /*! @brief PXP Histogram operation result flags. */ 1040 enum _pxp_histgram_flags 1041 { 1042 kPXP_Histogram2levelMatch = 1 << 0U, /* Bitmap pixels are fully contained within the HIST2 histogram. */ 1043 kPXP_Histogram4levelMatch = 1 << 1U, /* Bitmap pixels are fully contained within the HIST4 histogram. */ 1044 kPXP_Histogram8levelMatch = 1 << 2U, /* Bitmap pixels are fully contained within the HIST8 histogram. */ 1045 kPXP_Histogram16levelMatch = 1 << 3U, /* Bitmap pixels are fully contained within the HIST16 histogram. */ 1046 kPXP_Histogram32levelMatch = 1 << 4U, /* Bitmap pixels are fully contained within the HIST32 histogram. */ 1047 }; 1048 1049 /*! @brief PXP WFE-A engine configuration. */ 1050 typedef struct _pxp_wfea_engine_config 1051 { 1052 uint32_t y4Addr; /*!< Address for Y4 buffer. */ 1053 uint32_t y4cAddr; /*!< Address for Y4C buffer, {Y4[3:0],3'b000,collision}, 8bpp. */ 1054 uint32_t wbAddr; /*!< Address for EPDC working buffer. */ 1055 uint16_t updateWidth; /*!< Width of the update area. */ 1056 uint16_t updateHeight; /*!< Height of the update area. */ 1057 uint16_t updatePitch; /*!< Pitch of the update area. */ 1058 uint16_t ulcX; /*!< X coordinate of upper left coordinate of the total input memory */ 1059 uint16_t ulcY; /*!< Y coordinate of upper left coordinate of the total input memory */ 1060 uint16_t resX; /*!< Horizontal resolution in pixels. */ 1061 uint8_t lutNum; /*!< The EPDC LUT number for the update. */ 1062 bool fullUpdateEnable; /*!< Enable full update. */ 1063 bool alphaEnable; /*!< Enable alpha field, upd is {Y4[3:0],3'b000,alpha} format, otherwise its {Y4[3:0],4'b0000}. */ 1064 bool detectionOnly; /*!< Detection only, do not write working buffer. */ 1065 } pxp_wfea_engine_config_t; 1066 1067 #endif /* FSL_FEATURE_PXP_V3 */ 1068 1069 /******************************************************************************* 1070 * API 1071 ******************************************************************************/ 1072 1073 #if defined(__cplusplus) 1074 extern "C" { 1075 #endif 1076 1077 /*! 1078 * @name Initialization and deinitialization 1079 * @{ 1080 */ 1081 1082 /*! 1083 * @brief Initialize the PXP. 1084 * 1085 * This function enables the PXP peripheral clock, and resets the PXP registers 1086 * to default status. 1087 * 1088 * @param base PXP peripheral base address. 1089 */ 1090 void PXP_Init(PXP_Type *base); 1091 1092 /*! 1093 * @brief De-initialize the PXP. 1094 * 1095 * This function disables the PXP peripheral clock. 1096 * 1097 * @param base PXP peripheral base address. 1098 */ 1099 void PXP_Deinit(PXP_Type *base); 1100 1101 /*! 1102 * @brief Reset the PXP. 1103 * 1104 * This function resets the PXP peripheral registers to default status. 1105 * 1106 * @param base PXP peripheral base address. 1107 */ 1108 void PXP_Reset(PXP_Type *base); 1109 1110 /*! 1111 * @brief Reset the PXP and the control register to initialized state. 1112 * 1113 * @param base PXP peripheral base address. 1114 */ 1115 void PXP_ResetControl(PXP_Type *base); 1116 /* @} */ 1117 1118 /*! 1119 * @name Global operations 1120 * @{ 1121 */ 1122 1123 /*! 1124 * @brief Start process. 1125 * 1126 * Start PXP process using current configuration. 1127 * 1128 * @param base PXP peripheral base address. 1129 */ 1130 static inline void PXP_Start(PXP_Type *base) 1131 { 1132 base->CTRL_SET = PXP_CTRL_ENABLE_MASK; 1133 } 1134 1135 /*! 1136 * @brief Enable or disable LCD hand shake. 1137 * 1138 * @param base PXP peripheral base address. 1139 * @param enable True to enable, false to disable. 1140 */ 1141 static inline void PXP_EnableLcdHandShake(PXP_Type *base, bool enable) 1142 { 1143 #if defined(PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK) 1144 if (enable) 1145 { 1146 base->CTRL_SET = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK; 1147 } 1148 else 1149 { 1150 base->CTRL_CLR = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK; 1151 } 1152 #else 1153 if (enable) 1154 { 1155 base->CTRL_SET = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK; 1156 } 1157 else 1158 { 1159 base->CTRL_CLR = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK; 1160 } 1161 #endif 1162 } 1163 1164 #if (defined(FSL_FEATURE_PXP_HAS_EN_REPEAT) && FSL_FEATURE_PXP_HAS_EN_REPEAT) 1165 /*! 1166 * @brief Enable or disable continous run. 1167 * 1168 * If continous run not enabled, @ref PXP_Start starts the PXP process. When completed, 1169 * PXP enters idle mode and flag @ref kPXP_CompleteFlag asserts. 1170 * 1171 * If continous run enabled, the PXP will repeat based on the current configuration register 1172 * settings. 1173 * 1174 * @param base PXP peripheral base address. 1175 * @param enable True to enable, false to disable. 1176 */ 1177 static inline void PXP_EnableContinousRun(PXP_Type *base, bool enable) 1178 { 1179 if (enable) 1180 { 1181 base->CTRL_SET = PXP_CTRL_EN_REPEAT_MASK; 1182 } 1183 else 1184 { 1185 base->CTRL_CLR = PXP_CTRL_EN_REPEAT_MASK; 1186 } 1187 } 1188 #endif /* FSL_FEATURE_PXP_HAS_EN_REPEAT */ 1189 1190 /*! 1191 * @brief Set the PXP processing block size 1192 * 1193 * This function chooses the pixel block size that PXP using during process. 1194 * Larger block size means better performace, but be careful that when PXP is 1195 * rotating, the output must be divisible by the block size selected. 1196 * 1197 * @param base PXP peripheral base address. 1198 * @param size The pixel block size. 1199 */ 1200 static inline void PXP_SetProcessBlockSize(PXP_Type *base, pxp_block_size_t size) 1201 { 1202 base->CTRL = (base->CTRL & ~PXP_CTRL_BLOCK_SIZE_MASK) | PXP_CTRL_BLOCK_SIZE(size); 1203 } 1204 1205 #if PXP_USE_PATH 1206 /*! 1207 * @brief Sets the path for one of the MUX 1208 * 1209 * @param base PXP peripheral base address. 1210 * @param path the path configuration for one of the mux. 1211 */ 1212 void PXP_SetPath(PXP_Type *base, pxp_path_t path); 1213 #endif /* PXP_USE_PATH */ 1214 1215 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 1216 /*! 1217 * @brief Enables or disables PXP engines in the process flow. 1218 * 1219 * @param base PXP peripheral base address. 1220 * @param mask The engines to enable. Logical OR of @ref pxp_process_engine_name_t. 1221 * @param enable true to enable, false to disable. 1222 */ 1223 static inline void PXP_EnableProcessEngine(PXP_Type *base, uint32_t mask, bool enable) 1224 { 1225 mask &= 0xF3F0000UL; 1226 1227 if (enable) 1228 { 1229 base->CTRL_SET = mask; 1230 } 1231 else 1232 { 1233 base->CTRL_CLR = mask; 1234 } 1235 } 1236 #endif /* FSL_FEATURE_PXP_V3 */ 1237 1238 /* @} */ 1239 1240 /*! 1241 * @name Status 1242 * @{ 1243 */ 1244 1245 /*! 1246 * @brief Gets PXP status flags. 1247 * 1248 * This function gets all PXP status flags. The flags are returned as the logical 1249 * OR value of the enumerators @ref _pxp_flags. To check a specific status, 1250 * compare the return value with enumerators in @ref _pxp_flags. 1251 * For example, to check whether the PXP has completed process, use like this: 1252 * @code 1253 if (kPXP_CompleteFlag & PXP_GetStatusFlags(PXP)) 1254 { 1255 ... 1256 } 1257 @endcode 1258 * 1259 * @param base PXP peripheral base address. 1260 * @return PXP status flags which are OR'ed by the enumerators in the _pxp_flags. 1261 */ 1262 static inline uint32_t PXP_GetStatusFlags(PXP_Type *base) 1263 { 1264 #if defined(PXP_STAT_AXI_READ_ERROR_1_MASK) 1265 uint32_t status = base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK | 1266 PXP_STAT_AXI_WRITE_ERROR_0_MASK | PXP_STAT_AXI_READ_ERROR_1_MASK | 1267 PXP_STAT_AXI_WRITE_ERROR_1_MASK); 1268 #else 1269 uint32_t status = base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK | 1270 PXP_STAT_AXI_WRITE_ERROR_0_MASK); 1271 #endif 1272 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 1273 status |= (base->IRQ >> 16U | base->IRQ << 16U); 1274 #endif /* FSL_FEATURE_PXP_V3 */ 1275 return status; 1276 } 1277 1278 /*! 1279 * @brief Clears status flags with the provided mask. 1280 * 1281 * This function clears PXP status flags with a provided mask. 1282 * 1283 * @param base PXP peripheral base address. 1284 * @param statusMask The status flags to be cleared; it is logical OR value of @ref _pxp_flags. 1285 */ 1286 static inline void PXP_ClearStatusFlags(PXP_Type *base, uint32_t statusMask) 1287 { 1288 base->STAT_CLR = statusMask; 1289 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 1290 statusMask &= 0xFFFF8000UL; 1291 base->IRQ_CLR = (statusMask >> 16U | statusMask << 16U); 1292 #endif /* FSL_FEATURE_PXP_V3 */ 1293 } 1294 1295 /*! 1296 * @brief Gets the AXI ID of the failing bus operation. 1297 * 1298 * @param base PXP peripheral base address. 1299 * @param axiIndex Whitch AXI to get 1300 * - 0: AXI0 1301 * - 1: AXI1 1302 * @return The AXI ID of the failing bus operation. 1303 */ 1304 static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex) 1305 { 1306 #if defined(PXP_STAT_AXI_ERROR_ID_1_MASK) 1307 if (0U == axiIndex) 1308 { 1309 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_0_MASK) >> PXP_STAT_AXI_ERROR_ID_0_SHIFT); 1310 } 1311 else 1312 { 1313 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_1_MASK) >> PXP_STAT_AXI_ERROR_ID_1_SHIFT); 1314 } 1315 #else 1316 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_MASK) >> PXP_STAT_AXI_ERROR_ID_SHIFT); 1317 #endif 1318 } 1319 1320 /* @} */ 1321 1322 /*! 1323 * @name Interrupts 1324 * @{ 1325 */ 1326 1327 /*! 1328 * @brief Enables PXP interrupts according to the provided mask. 1329 * 1330 * This function enables the PXP interrupts according to the provided mask. The mask 1331 * is a logical OR of enumeration members. See @ref _pxp_interrupt_enable. 1332 * For example, to enable PXP process complete interrupt and command loaded 1333 * interrupt, do the following. 1334 * @code 1335 PXP_EnableInterrupts(PXP, kPXP_CommandLoadInterruptEnable | kPXP_CompleteInterruptEnable); 1336 @endcode 1337 * 1338 * @param base PXP peripheral base address. 1339 * @param mask The interrupts to enable. Logical OR of @ref _pxp_interrupt_enable. 1340 */ 1341 static inline void PXP_EnableInterrupts(PXP_Type *base, uint32_t mask) 1342 { 1343 base->CTRL_SET = (mask & 0xEUL); 1344 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 1345 mask &= 0xFFFF8000UL; 1346 base->IRQ_MASK_SET = (mask >> 16U | mask << 16U); 1347 #endif /* FSL_FEATURE_PXP_V3 */ 1348 } 1349 1350 /*! 1351 * @brief Disables PXP interrupts according to the provided mask. 1352 * 1353 * This function disables the PXP interrupts according to the provided mask. The mask 1354 * is a logical OR of enumeration members. See @ref _pxp_interrupt_enable. 1355 * 1356 * @param base PXP peripheral base address. 1357 * @param mask The interrupts to disable. Logical OR of @ref _pxp_interrupt_enable. 1358 */ 1359 static inline void PXP_DisableInterrupts(PXP_Type *base, uint32_t mask) 1360 { 1361 base->CTRL_CLR = (mask & 0xEUL); 1362 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 1363 mask &= 0xFFFF8000UL; 1364 base->IRQ_MASK_CLR = (mask >> 16U | mask << 16U); 1365 #endif /* FSL_FEATURE_PXP_V3 */ 1366 } 1367 1368 /* @} */ 1369 1370 /*! 1371 * @name Alpha surface 1372 * @{ 1373 */ 1374 1375 /*! 1376 * @brief Set the alpha surface input buffer configuration. 1377 * 1378 * @param base PXP peripheral base address. 1379 * @param config Pointer to the configuration. 1380 */ 1381 void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config); 1382 1383 /*! 1384 * @brief Set the alpha surface blending configuration. 1385 * 1386 * @param base PXP peripheral base address. 1387 * @param config Pointer to the configuration structure. 1388 */ 1389 void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config); 1390 1391 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 1392 /*! 1393 * @brief Set the alpha surface blending configuration for the secondary engine. 1394 * 1395 * @param base PXP peripheral base address. 1396 * @param config Pointer to the configuration structure. 1397 */ 1398 void PXP_SetAlphaSurfaceBlendSecondaryConfig(PXP_Type *base, const pxp_as_blend_secondary_config_t *config); 1399 1400 /*! 1401 * @brief Set the alpha surface overlay color key. 1402 * 1403 * If a pixel in the current overlay image with a color that falls in the range 1404 * from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface 1405 * pixel value for that location. If no PS image is present or if the PS image also 1406 * matches its colorkey range, the PS background color is used. 1407 * 1408 * @param base PXP peripheral base address. 1409 * @param num instance number. 0 for alpha engine A, 1 for alpha engine B. 1410 * @param colorKeyLow Color key low range. 1411 * @param colorKeyHigh Color key high range. 1412 * 1413 * @note Colorkey operations are higher priority than alpha or ROP operations 1414 */ 1415 void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh); 1416 1417 /*! 1418 * @brief Enable or disable the alpha surface color key. 1419 * 1420 * @param base PXP peripheral base address. 1421 * @param num instance number. 0 for alpha engine A, 1 for alpha engine B. 1422 * @param enable True to enable, false to disable. 1423 */ 1424 static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t num, bool enable) 1425 { 1426 switch (num) 1427 { 1428 case 0: 1429 base->AS_CTRL = 1430 (base->AS_CTRL & ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK) | PXP_AS_CTRL_ENABLE_COLORKEY((uint32_t)enable); 1431 break; 1432 1433 case 1: 1434 base->ALPHA_B_CTRL_1 = (base->ALPHA_B_CTRL_1 & ~PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_MASK) | 1435 PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE((uint32_t)enable); 1436 break; 1437 1438 default: 1439 /* Only 2 alpha process engine instances are supported. */ 1440 assert(false); 1441 break; 1442 } 1443 } 1444 #else 1445 /*! 1446 * @brief Set the alpha surface overlay color key. 1447 * 1448 * If a pixel in the current overlay image with a color that falls in the range 1449 * from the p colorKeyLow to p colorKeyHigh range, it will use the process surface 1450 * pixel value for that location. If no PS image is present or if the PS image also 1451 * matches its colorkey range, the PS background color is used. 1452 * 1453 * @param base PXP peripheral base address. 1454 * @param colorKeyLow Color key low range. 1455 * @param colorKeyHigh Color key high range. 1456 * 1457 * @note Colorkey operations are higher priority than alpha or ROP operations 1458 */ 1459 void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh); 1460 1461 /*! 1462 * @brief Enable or disable the alpha surface color key. 1463 * 1464 * @param base PXP peripheral base address. 1465 * @param enable True to enable, false to disable. 1466 */ 1467 static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, bool enable) 1468 { 1469 if (enable) 1470 { 1471 base->AS_CTRL |= PXP_AS_CTRL_ENABLE_COLORKEY_MASK; 1472 } 1473 else 1474 { 1475 base->AS_CTRL &= ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK; 1476 } 1477 } 1478 #endif /* FSL_FEATURE_PXP_V3 */ 1479 1480 /*! 1481 * @brief Set the alpha surface position in output buffer. 1482 * 1483 * @param base PXP peripheral base address. 1484 * @param upperLeftX X of the upper left corner. 1485 * @param upperLeftY Y of the upper left corner. 1486 * @param lowerRightX X of the lower right corner. 1487 * @param lowerRightY Y of the lower right corner. 1488 */ 1489 void PXP_SetAlphaSurfacePosition( 1490 PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY); 1491 /* @} */ 1492 1493 /*! 1494 * @name Process surface 1495 * @{ 1496 */ 1497 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 1498 /*! 1499 * @brief Set the back ground color of PS. 1500 * 1501 * @param base PXP peripheral base address. 1502 * @param num instance number. 0 for alpha engine A, 1 for alpha engine B. 1503 * @param backGroundColor Pixel value of the background color. 1504 */ 1505 static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint8_t num, uint32_t backGroundColor) 1506 { 1507 switch (num) 1508 { 1509 case 0: 1510 base->PS_BACKGROUND_0 = backGroundColor; 1511 break; 1512 1513 case 1: 1514 base->PS_BACKGROUND_1 = backGroundColor; 1515 break; 1516 1517 default: 1518 /* Only 2 alpha process engine instances are supported. */ 1519 assert(false); 1520 break; 1521 } 1522 } 1523 #else 1524 /*! 1525 * @brief Set the back ground color of PS. 1526 * 1527 * @param base PXP peripheral base address. 1528 * @param backGroundColor Pixel value of the background color. 1529 */ 1530 static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint32_t backGroundColor) 1531 { 1532 #if defined(PXP_PS_BACKGROUND_0_COLOR_MASK) 1533 base->PS_BACKGROUND_0 = backGroundColor; 1534 #else 1535 base->PS_BACKGROUND = backGroundColor; 1536 #endif 1537 } 1538 #endif /* FSL_FEATURE_PXP_V3 */ 1539 1540 /*! 1541 * @brief Set the process surface input buffer configuration. 1542 * 1543 * @param base PXP peripheral base address. 1544 * @param config Pointer to the configuration. 1545 */ 1546 void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config); 1547 1548 /*! 1549 * @brief Set the process surface scaler configuration. 1550 * 1551 * The valid down scale fact is 1/(2^12) ~ 16. 1552 * 1553 * @param base PXP peripheral base address. 1554 * @param inputWidth Input image width. 1555 * @param inputHeight Input image height. 1556 * @param outputWidth Output image width. 1557 * @param outputHeight Output image height. 1558 */ 1559 void PXP_SetProcessSurfaceScaler( 1560 PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight); 1561 1562 /*! 1563 * @brief Set the process surface position in output buffer. 1564 * 1565 * @param base PXP peripheral base address. 1566 * @param upperLeftX X of the upper left corner. 1567 * @param upperLeftY Y of the upper left corner. 1568 * @param lowerRightX X of the lower right corner. 1569 * @param lowerRightY Y of the lower right corner. 1570 */ 1571 void PXP_SetProcessSurfacePosition( 1572 PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY); 1573 1574 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 1575 /*! 1576 * @brief Set the process surface color key. 1577 * 1578 * If the PS image matches colorkey range, the PS background color is output. Set 1579 * @p colorKeyLow to 0xFFFFFFFF and p colorKeyHigh to 0 will disable the colorkeying. 1580 * 1581 * @param base PXP peripheral base address. 1582 * @param num instance number. 0 for alpha engine A, 1 for alpha engine B. 1583 * @param colorKeyLow Color key low range. 1584 * @param colorKeyHigh Color key high range. 1585 */ 1586 void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh); 1587 #else 1588 /*! 1589 * @brief Set the process surface color key. 1590 * 1591 * If the PS image matches colorkey range, the PS background color is output. Set 1592 * @p colorKeyLow to 0xFFFFFFFF and @p colorKeyHigh to 0 will disable the colorkeying. 1593 * 1594 * @param base PXP peripheral base address. 1595 * @param colorKeyLow Color key low range. 1596 * @param colorKeyHigh Color key high range. 1597 */ 1598 void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh); 1599 #endif /* FSL_FEATURE_PXP_V3 */ 1600 1601 /*! 1602 * @brief Set the process surface input pixel format YUV or YCbCr. 1603 * 1604 * If process surface input pixel format is YUV and CSC1 is not enabled, 1605 * in other words, the process surface output pixel format is also YUV, 1606 * then this function should be called to set whether input pixel format 1607 * is YUV or YCbCr. 1608 * 1609 * @param base PXP peripheral base address. 1610 * @param format The YUV format. 1611 */ 1612 static inline void PXP_SetProcessSurfaceYUVFormat(PXP_Type *base, pxp_ps_yuv_format_t format) 1613 { 1614 if (kPXP_PsYUVFormatYUV == format) 1615 { 1616 base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_YCBCR_MODE_MASK; 1617 } 1618 else 1619 { 1620 base->CSC1_COEF0 |= PXP_CSC1_COEF0_YCBCR_MODE_MASK; 1621 } 1622 } 1623 /* @} */ 1624 1625 /*! 1626 * @name Output buffer 1627 * @{ 1628 */ 1629 1630 /*! 1631 * @brief Set the PXP outpt buffer configuration. 1632 * 1633 * @param base PXP peripheral base address. 1634 * @param config Pointer to the configuration. 1635 */ 1636 void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config); 1637 1638 /*! 1639 * @brief Set the global overwritten alpha value. 1640 * 1641 * If global overwritten alpha is enabled, the alpha component in output buffer pixels 1642 * will be overwritten, otherwise the computed alpha value is used. 1643 * 1644 * @param base PXP peripheral base address. 1645 * @param alpha The alpha value. 1646 */ 1647 static inline void PXP_SetOverwrittenAlphaValue(PXP_Type *base, uint8_t alpha) 1648 { 1649 base->OUT_CTRL = (base->OUT_CTRL & ~PXP_OUT_CTRL_ALPHA_MASK) | PXP_OUT_CTRL_ALPHA(alpha); 1650 } 1651 1652 /*! 1653 * @brief Enable or disable the global overwritten alpha value. 1654 * 1655 * If global overwritten alpha is enabled, the alpha component in output buffer pixels 1656 * will be overwritten, otherwise the computed alpha value is used. 1657 * 1658 * @param base PXP peripheral base address. 1659 * @param enable True to enable, false to disable. 1660 */ 1661 static inline void PXP_EnableOverWrittenAlpha(PXP_Type *base, bool enable) 1662 { 1663 if (enable) 1664 { 1665 base->OUT_CTRL_SET = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK; 1666 } 1667 else 1668 { 1669 base->OUT_CTRL_CLR = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK; 1670 } 1671 } 1672 1673 /*! 1674 * @brief Set the rotation configuration. 1675 * 1676 * The PXP could rotate the process surface or the output buffer. There are 1677 * two PXP versions: 1678 * - Version 1: Only has one rotate sub module, the output buffer and process 1679 * surface share the same rotate sub module, which means the process surface 1680 * and output buffer could not be rotate at the same time. When pass in 1681 * @ref kPXP_RotateOutputBuffer, the process surface could not use the rotate, 1682 * Also when pass in @ref kPXP_RotateProcessSurface, output buffer could not 1683 * use the rotate. 1684 * - Version 2: Has two seperate rotate sub modules, the output buffer and 1685 * process surface could configure the rotation independently. 1686 * 1687 * Upper layer could use the macro PXP_SHARE_ROTATE to check which version is. 1688 * PXP_SHARE_ROTATE=1 means version 1. 1689 * 1690 * @param base PXP peripheral base address. 1691 * @param position Rotate process surface or output buffer. 1692 * @param degree Rotate degree. 1693 * @param flipMode Flip mode. 1694 * 1695 * @note This function is different depends on the macro PXP_SHARE_ROTATE. 1696 */ 1697 static inline void PXP_SetRotateConfig(PXP_Type *base, 1698 pxp_rotate_position_t position, 1699 pxp_rotate_degree_t degree, 1700 pxp_flip_mode_t flipMode) 1701 { 1702 #if PXP_SHARE_ROTATE 1703 base->CTRL = 1704 (base->CTRL & ~(PXP_CTRL_ROTATE_MASK | PXP_CTRL_ROT_POS_MASK | PXP_CTRL_VFLIP_MASK | PXP_CTRL_HFLIP_MASK)) | 1705 PXP_CTRL_ROTATE(degree) | PXP_CTRL_ROT_POS(position) | ((uint32_t)flipMode << PXP_CTRL_HFLIP_SHIFT); 1706 #else 1707 uint32_t ctrl = base->CTRL; 1708 1709 if (kPXP_RotateOutputBuffer == position) 1710 { 1711 ctrl &= ~(PXP_CTRL_HFLIP0_MASK | PXP_CTRL_VFLIP0_MASK | PXP_CTRL_ROTATE0_MASK); 1712 ctrl |= (PXP_CTRL_ROTATE0(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP0_SHIFT)); 1713 } 1714 else 1715 { 1716 ctrl &= ~(PXP_CTRL_HFLIP1_MASK | PXP_CTRL_VFLIP1_MASK | PXP_CTRL_ROTATE1_MASK); 1717 ctrl |= (PXP_CTRL_ROTATE1(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP1_SHIFT)); 1718 } 1719 1720 base->CTRL = ctrl; 1721 #endif 1722 } 1723 1724 /*! 1725 * @brief Build a solid rectangle of given pixel value. 1726 * 1727 * @param base PXP peripheral base address. 1728 * @param outFormat output pixel format. 1729 * @param value The value of the pixel to be filled in the rectangle in ARGB8888 format. 1730 * @param width width of the rectangle. 1731 * @param height height of the rectangle. 1732 * @param pitch output pitch in byte. 1733 * @param outAddr address of the memory to store the rectangle. 1734 */ 1735 void PXP_BuildRect(PXP_Type *base, 1736 pxp_output_pixel_format_t outFormat, 1737 uint32_t value, 1738 uint16_t width, 1739 uint16_t height, 1740 uint16_t pitch, 1741 uint32_t outAddr); 1742 /* @} */ 1743 1744 /*! 1745 * @name Command queue 1746 * @{ 1747 */ 1748 1749 /*! 1750 * @brief Set the next command. 1751 * 1752 * The PXP supports a primitive ability to queue up one operation while the current 1753 * operation is running. Workflow: 1754 * 1755 * 1. Prepare the PXP register values except STAT, CSCCOEFn, NEXT in the memory 1756 * in the order they appear in the register map. 1757 * 2. Call this function sets the new operation to PXP. 1758 * 3. There are two methods to check whether the PXP has loaded the new operation. 1759 * The first method is using @ref PXP_IsNextCommandPending. If there is new operation 1760 * not loaded by the PXP, this function returns true. The second method is checking 1761 * the flag @ref kPXP_CommandLoadFlag, if command loaded, this flag asserts. User 1762 * could enable interrupt @ref kPXP_CommandLoadInterruptEnable to get the loaded 1763 * signal in interrupt way. 1764 * 4. When command loaded by PXP, a new command could be set using this function. 1765 * 1766 * @code 1767 uint32_t pxp_command1[48]; 1768 uint32_t pxp_command2[48]; 1769 1770 pxp_command1[0] = ...; 1771 pxp_command1[1] = ...; 1772 ... 1773 pxp_command2[0] = ...; 1774 pxp_command2[1] = ...; 1775 ... 1776 1777 while (PXP_IsNextCommandPending(PXP)) 1778 { 1779 } 1780 1781 PXP_SetNextCommand(PXP, pxp_command1); 1782 1783 while (PXP_IsNextCommandPending(PXP)) 1784 { 1785 } 1786 1787 PXP_SetNextCommand(PXP, pxp_command2); 1788 @endcode 1789 * 1790 * @param base PXP peripheral base address. 1791 * @param commandAddr Address of the new command. 1792 */ 1793 void PXP_SetNextCommand(PXP_Type *base, void *commandAddr); 1794 1795 /*! 1796 * @brief Check whether the next command is pending. 1797 * 1798 * @param base UART peripheral base address. 1799 * @return True is pending, false is not. 1800 */ 1801 static inline bool PXP_IsNextCommandPending(PXP_Type *base) 1802 { 1803 return (bool)(base->NEXT & PXP_NEXT_ENABLED_MASK); 1804 } 1805 1806 /*! 1807 * @brief Cancel command set by @ref PXP_SetNextCommand 1808 * 1809 * @param base UART peripheral base address. 1810 */ 1811 static inline void PXP_CancelNextCommand(PXP_Type *base) 1812 { 1813 /* Write PXP_NEXT_ENABLED_MASK to the register NEXT_CLR to canel the command. */ 1814 uint32_t regAddr = (uint32_t) & (base->NEXT); 1815 regAddr += 8U; 1816 *(uint32_t *)regAddr = PXP_NEXT_ENABLED_MASK; 1817 } 1818 1819 /* @} */ 1820 1821 /*! 1822 * @name Color space conversion 1823 * @{ 1824 */ 1825 1826 #if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2) 1827 /*! 1828 * @brief Set the CSC2 configuration. 1829 * 1830 * The CSC2 module receives pixels in any color space and can convert the pixels 1831 * into any of RGB, YUV, or YCbCr color spaces. The output pixels are passed 1832 * onto the LUT and rotation engine for further processing 1833 * 1834 * @param base PXP peripheral base address. 1835 * @param config Pointer to the configuration. 1836 */ 1837 void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config); 1838 1839 /*! 1840 * @brief Enable or disable the CSC2. 1841 * 1842 * @param base PXP peripheral base address. 1843 * @param enable True to enable, false to disable. 1844 */ 1845 static inline void PXP_EnableCsc2(PXP_Type *base, bool enable) 1846 { 1847 if (enable) 1848 { 1849 base->CSC2_CTRL &= ~PXP_CSC2_CTRL_BYPASS_MASK; 1850 } 1851 else 1852 { 1853 base->CSC2_CTRL |= PXP_CSC2_CTRL_BYPASS_MASK; 1854 } 1855 } 1856 #endif /* FSL_FEATURE_PXP_HAS_NO_CSC2 */ 1857 1858 /*! 1859 * @brief Set the CSC1 mode. 1860 * 1861 * The CSC1 module receives scaled YUV/YCbCr444 pixels from the scale engine and 1862 * converts the pixels to the RGB888 color space. It could only be used by process 1863 * surface. 1864 * 1865 * @param base PXP peripheral base address. 1866 * @param mode The conversion mode. 1867 */ 1868 void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode); 1869 1870 /*! 1871 * @brief Enable or disable the CSC1. 1872 * 1873 * @param base PXP peripheral base address. 1874 * @param enable True to enable, false to disable. 1875 */ 1876 static inline void PXP_EnableCsc1(PXP_Type *base, bool enable) 1877 { 1878 if (enable) 1879 { 1880 base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_BYPASS_MASK; 1881 } 1882 else 1883 { 1884 base->CSC1_COEF0 |= PXP_CSC1_COEF0_BYPASS_MASK; 1885 } 1886 } 1887 /* @} */ 1888 1889 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT) 1890 /*! 1891 * @name LUT operations 1892 * @{ 1893 */ 1894 1895 /*! 1896 * @brief Set the LUT configuration. 1897 * 1898 * The lookup table (LUT) is used to modify pixels in a manner that is not linear 1899 * and that cannot be achieved by the color space conversion modules. To setup 1900 * the LUT, the complete workflow is: 1901 * 1. Use @ref PXP_SetLutConfig to set the configuration, such as the lookup mode. 1902 * 2. Use @ref PXP_LoadLutTable to load the lookup table to PXP. 1903 * 3. Use @ref PXP_EnableLut to enable the function. 1904 * 1905 * @param base PXP peripheral base address. 1906 * @param config Pointer to the configuration. 1907 */ 1908 void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config); 1909 1910 /*! 1911 * @brief Set the look up table to PXP. 1912 * 1913 * If lookup mode is DIRECT mode, this function loads @p bytesNum of values 1914 * from the address @p memAddr into PXP LUT address @p lutStartAddr. So this 1915 * function allows only update part of the PXP LUT. 1916 * 1917 * If lookup mode is CACHE mode, this function sets the new address to @p memAddr 1918 * and invalid the PXP LUT cache. 1919 * 1920 * @param base PXP peripheral base address. 1921 * @param lookupMode Which lookup mode is used. Note that this parameter is only 1922 * used to distinguish DIRECT mode and CACHE mode, it does not change the register 1923 * value PXP_LUT_CTRL[LOOKUP_MODE]. To change that value, use function @ref PXP_SetLutConfig. 1924 * @param bytesNum How many bytes to set. This value must be divisable by 8. 1925 * @param memAddr Address of look up table to set. 1926 * @param lutStartAddr The LUT value will be loaded to LUT from index lutAddr. It should 1927 * be 8 bytes aligned. 1928 * 1929 * @retval kStatus_Success Load successfully. 1930 * @retval kStatus_InvalidArgument Failed because of invalid argument. 1931 */ 1932 status_t PXP_LoadLutTable( 1933 PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr); 1934 1935 /*! 1936 * @brief Enable or disable the LUT. 1937 * 1938 * @param base PXP peripheral base address. 1939 * @param enable True to enable, false to disable. 1940 */ 1941 static inline void PXP_EnableLut(PXP_Type *base, bool enable) 1942 { 1943 if (enable) 1944 { 1945 base->LUT_CTRL &= ~PXP_LUT_CTRL_BYPASS_MASK; 1946 } 1947 else 1948 { 1949 base->LUT_CTRL |= PXP_LUT_CTRL_BYPASS_MASK; 1950 } 1951 } 1952 1953 /*! 1954 * @brief Select the 8kB LUT bank in DIRECT_RGB444 mode. 1955 * 1956 * @param base PXP peripheral base address. 1957 * @param bank The bank to select. 1958 */ 1959 static inline void PXP_Select8kLutBank(PXP_Type *base, pxp_lut_8k_bank_t bank) 1960 { 1961 base->LUT_CTRL = (base->LUT_CTRL & ~PXP_LUT_CTRL_SEL_8KB_MASK) | PXP_LUT_CTRL_SEL_8KB(bank); 1962 } 1963 /* @} */ 1964 #endif /* FSL_FEATURE_PXP_HAS_NO_LUT */ 1965 1966 #if (defined(FSL_FEATURE_PXP_HAS_DITHER) && FSL_FEATURE_PXP_HAS_DITHER) 1967 /*! 1968 * @name Dither 1969 * @{ 1970 */ 1971 1972 /*! 1973 * @brief Write data to the PXP internal memory. 1974 * 1975 * @param base PXP peripheral base address. 1976 * @param ram Which internal memory to write. 1977 * @param bytesNum How many bytes to write. 1978 * @param data Pointer to the data to write. 1979 * @param memStartAddr The start address in the internal memory to write the data. 1980 */ 1981 void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr); 1982 1983 /*! 1984 * @brief Set the dither final LUT data. 1985 * 1986 * The dither final LUT is only applicble to dither engine 0. It takes the bits[7:4] 1987 * of the output pixel and looks up and 8 bit value from the 16 value LUT to generate 1988 * the final output pixel to the next process module. 1989 * 1990 * @param base PXP peripheral base address. 1991 * @param data Pointer to the LUT data to set. 1992 */ 1993 void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data); 1994 1995 /*! 1996 * @brief Set the configuration for the dither block. 1997 * 1998 * If the pre-dither LUT, post-dither LUT or ordered dither is used, please call 1999 * @ref PXP_SetInternalRamData to set the LUT data to internal memory. 2000 * 2001 * If the final LUT is used, please call @ref PXP_SetDitherFinalLutData to set 2002 * the LUT data. 2003 * 2004 * @param base PXP peripheral base address. 2005 * @param config Pointer to the configuration. 2006 * 2007 * @note When using ordered dithering, please set the PXP process block size same 2008 * with the ordered dithering matrix size using function @ref PXP_SetProcessBlockSize. 2009 */ 2010 static inline void PXP_SetDitherConfig(PXP_Type *base, const pxp_dither_config_t *config) 2011 { 2012 typedef union 2013 { 2014 pxp_dither_config_t _dither_config; 2015 uint32_t _u32; 2016 } pxp_reg_convert_t; 2017 2018 pxp_reg_convert_t pid; 2019 2020 pid._dither_config = *config; 2021 base->DITHER_CTRL = pid._u32 & 0x00FFFFFFU; 2022 } 2023 2024 /*! 2025 * @brief Enable or disable dither engine in the PXP process path. 2026 * 2027 * After the initialize function @ref PXP_Init, the dither engine is disabled and not 2028 * use in the PXP processing path. This function enables the dither engine and 2029 * routes the dither engine output to the output buffer. When the dither engine 2030 * is enabled using this function, @ref PXP_SetDitherConfig must be called to 2031 * configure dither engine correctly, otherwise there is not output to the output 2032 * buffer. 2033 * 2034 * @param base PXP peripheral base address. 2035 * @param enable Pass in true to enable, false to disable. 2036 */ 2037 void PXP_EnableDither(PXP_Type *base, bool enable); 2038 2039 /* @} */ 2040 2041 #endif /* FSL_FEATURE_PXP_HAS_DITHER */ 2042 2043 /*! 2044 * @name Porter Duff 2045 * @{ 2046 */ 2047 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 2048 /*! 2049 * @brief Set the Porter Duff configuration for one of the alpha process engine. 2050 * 2051 * @param base PXP peripheral base address. 2052 * @param num instance number. 2053 * @param config Pointer to the configuration. 2054 */ 2055 void PXP_SetPorterDuffConfig(PXP_Type *base, uint8_t num, const pxp_porter_duff_config_t *config); 2056 #endif /* FSL_FEATURE_PXP_V3 */ 2057 2058 #if !(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) 2059 /*! 2060 * @brief Set the Porter Duff configuration. 2061 * 2062 * @param base PXP peripheral base address. 2063 * @param config Pointer to the configuration. 2064 */ 2065 void PXP_SetPorterDuffConfig(PXP_Type *base, const pxp_porter_duff_config_t *config); 2066 #endif /* FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */ 2067 2068 #if (!(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL)) || \ 2069 (defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3) 2070 /*! 2071 * @brief Get the Porter Duff configuration by blend mode. 2072 * 2073 * The FactorMode are selected based on blend mode, the AlphaMode are set to 2074 * @ref kPXP_PorterDuffAlphaStraight, the ColorMode are set to 2075 * @ref kPXP_PorterDuffColorWithAlpha, the GlobalAlphaMode are set to 2076 * @ref kPXP_PorterDuffLocalAlpha. These values could be modified after calling 2077 * this function. 2078 * 2079 * @param mode The blend mode. 2080 * @param config Pointer to the configuration. 2081 * @retval kStatus_Success Successfully get the configuratoin. 2082 * @retval kStatus_InvalidArgument The blend mode not supported. 2083 */ 2084 status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_duff_config_t *config); 2085 2086 /* @} */ 2087 #endif /* FSL_FEATURE_PXP_V3 || FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */ 2088 2089 /* @} */ 2090 2091 /*! 2092 * @name Buffer copy 2093 * @{ 2094 */ 2095 2096 /*! 2097 * @brief Copy picture from one buffer to another buffer. 2098 * 2099 * This function copies a rectangle from one buffer to another buffer. 2100 * 2101 * @verbatim 2102 Source buffer: 2103 srcPicBaseAddr 2104 +-----------------------------------------------------------+ 2105 | | 2106 | (srcOffsetX, srcOffsetY) | 2107 | +-------------------+ | 2108 | | | | 2109 | | | | 2110 | | | height | 2111 | | | | 2112 | | | | 2113 | +-------------------+ | 2114 | width | 2115 | | 2116 | srcPicthBytes | 2117 +-----------------------------------------------------------+ 2118 2119 Destination buffer: 2120 destPicBaseAddr 2121 +-------------------------------------------+ 2122 | | 2123 | | 2124 | | 2125 | (destOffsetX, destOffsetY) | 2126 | +-------------------+ | 2127 | | | | 2128 | | | | 2129 | | | height | 2130 | | | | 2131 | | | | 2132 | +-------------------+ | 2133 | width | 2134 | | 2135 | | 2136 | | 2137 | destPicthBytes | 2138 +-------------------------------------------+ 2139 @endverbatim 2140 * 2141 * @note This function resets the old PXP settings, which means the settings 2142 * like rotate, flip, will be reseted to disabled status. 2143 * 2144 * @param base PXP peripheral base address. 2145 * @param config Pointer to the picture copy configuration structure. 2146 * @retval kStatus_Success Successfully started the copy process. 2147 * @retval kStatus_InvalidArgument Invalid argument. 2148 */ 2149 status_t PXP_StartPictureCopy(PXP_Type *base, const pxp_pic_copy_config_t *config); 2150 2151 /*! 2152 * @brief Copy continous memory. 2153 * 2154 * @note The copy size should be 512 byte aligned. 2155 * @note This function resets the old PXP settings, which means the settings 2156 * like rotate, flip, will be reseted to disabled status. 2157 * 2158 * @param base PXP peripheral base address. 2159 * @param srcAddr Source memory address. 2160 * @param destAddr Destination memory address. 2161 * @param size How many bytes to copy, should be 512 byte aligned. 2162 * @retval kStatus_Success Successfully started the copy process. 2163 * @retval kStatus_InvalidArgument Invalid argument. 2164 */ 2165 status_t PXP_StartMemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size); 2166 2167 /*! 2168 * @brief Copy continous memory. 2169 * 2170 * @note This function resets the old PXP settings, which means the settings 2171 * like rotate, flip, will be reseted to disabled status. 2172 * 2173 * @note Compare with @PXP_StartMemCopy, this function supports size not aligned to 2174 * 512 bytes. This function returns when copy finished, upper layer doesn't need to 2175 * wait @ref kPXP_CompleteFlag. 2176 * 2177 * @param base PXP peripheral base address. 2178 * @param srcAddr Source memory address. 2179 * @param destAddr Destination memory address. 2180 * @param size How many bytes to copy, should be 512 byte aligned. 2181 * @retval kStatus_Success Successfully started the copy process. 2182 * @retval kStatus_InvalidArgument Invalid argument. 2183 */ 2184 status_t PXP_MemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size); 2185 2186 /* @} */ 2187 2188 #if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3 2189 2190 /*! 2191 * @name Fetch engine 2192 * @{ 2193 */ 2194 /*! 2195 * @brief Configures one channel of some block's fetch engine. 2196 * 2197 * Fetch engine is 64-bit input and 32-bit output per channel 2198 * 2199 * @param base PXP peripheral base address. 2200 * @param name which block the fetch engine belongs to. 2201 * @param channel channel number. 2202 * @param config pointer to the configuration structure. 2203 * @retval kStatus_Success Successfully configured the engine. 2204 * @retval kStatus_InvalidArgument Invalid argument. 2205 */ 2206 status_t PXP_SetFetchEngineConfig(PXP_Type *base, 2207 pxp_fetch_engine_name_t name, 2208 uint8_t channel, 2209 const pxp_fetch_engine_config_t *config); 2210 2211 /*! 2212 * @brief Enables/disables the fetch engine. 2213 * 2214 * @param base PXP peripheral base address. 2215 * @param name which block the fetch engine belongs to. 2216 * @param channel channel number. 2217 * @param enable true to enable, false to disable. 2218 */ 2219 static inline void PXP_EnableFetchEngine(PXP_Type *base, pxp_fetch_engine_name_t name, uint8_t channel, bool enable) 2220 { 2221 if (enable) 2222 { 2223 if (name == kPXP_FetchInput) 2224 { 2225 switch (channel) 2226 { 2227 case 0: 2228 base->INPUT_FETCH_CTRL_CH0_SET = PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK; 2229 break; 2230 2231 case 1: 2232 base->INPUT_FETCH_CTRL_CH1_SET = PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK; 2233 break; 2234 2235 default: 2236 /* Only 2 channels are supported per fetch engine. */ 2237 assert(false); 2238 break; 2239 } 2240 } 2241 else 2242 { 2243 switch (channel) 2244 { 2245 case 0: 2246 base->DITHER_FETCH_CTRL_CH0_SET = PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK; 2247 break; 2248 2249 case 1: 2250 base->DITHER_FETCH_CTRL_CH1_SET = PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK; 2251 break; 2252 2253 default: 2254 /* Only 2 channels are supported per fetch engine. */ 2255 assert(false); 2256 break; 2257 } 2258 } 2259 } 2260 else 2261 { 2262 if (name == kPXP_FetchInput) 2263 { 2264 switch (channel) 2265 { 2266 case 0: 2267 base->INPUT_FETCH_CTRL_CH0_CLR = PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK; 2268 break; 2269 2270 case 1: 2271 base->INPUT_FETCH_CTRL_CH1_CLR = PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK; 2272 break; 2273 2274 default: 2275 /* Only 2 channels are supported per fetch engine. */ 2276 assert(false); 2277 break; 2278 } 2279 } 2280 else 2281 { 2282 switch (channel) 2283 { 2284 case 0: 2285 base->DITHER_FETCH_CTRL_CH0_CLR = PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK; 2286 break; 2287 2288 case 1: 2289 base->DITHER_FETCH_CTRL_CH1_CLR = PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK; 2290 break; 2291 2292 default: 2293 /* Only 2 channels are supported per fetch engine. */ 2294 assert(false); 2295 break; 2296 } 2297 } 2298 } 2299 } 2300 /* @} */ 2301 2302 /*! 2303 * @name Store engine 2304 * @{ 2305 */ 2306 2307 /*! 2308 * @brief Configures one channel of some block's store engine. 2309 * 2310 * Store engine is 32-bit input and 64-bit output per channel. 2311 * @note: If there is only one channel used for data input, channel 0 must be used rather than channel 1. 2312 * 2313 * @param base PXP peripheral base address. 2314 * @param name the store engine belongs to which block. 2315 * @param channel channel number. 2316 * @param config pointer to the configuration structure. 2317 * @retval kStatus_Success Successfully configured the engine. 2318 * @retval kStatus_InvalidArgument Invalid argument. 2319 */ 2320 status_t PXP_SetStoreEngineConfig(PXP_Type *base, 2321 pxp_store_engine_name_t name, 2322 uint8_t channel, 2323 const pxp_store_engine_config_t *config); 2324 2325 /*! 2326 * @brief Enables/disables the store engine. 2327 * 2328 * @param base PXP peripheral base address. 2329 * @param name which block the store engine belongs to. 2330 * @param channel channel number. 2331 * @param enable true to enable, false to disable. 2332 */ 2333 static inline void PXP_EnableStoreEngine(PXP_Type *base, pxp_store_engine_name_t name, uint8_t channel, bool enable) 2334 { 2335 if (enable) 2336 { 2337 if (name == kPXP_StoreInput) 2338 { 2339 switch (channel) 2340 { 2341 case 0: 2342 base->INPUT_STORE_CTRL_CH0_SET = PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK; 2343 break; 2344 2345 case 1: 2346 base->INPUT_STORE_CTRL_CH1_SET = PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK; 2347 break; 2348 2349 default: 2350 /* Only 2 channels are supported per fetch engine. */ 2351 assert(false); 2352 break; 2353 } 2354 } 2355 else 2356 { 2357 switch (channel) 2358 { 2359 case 0: 2360 base->DITHER_STORE_CTRL_CH0_SET = PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK; 2361 break; 2362 2363 case 1: 2364 base->DITHER_STORE_CTRL_CH1_SET = PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK; 2365 break; 2366 2367 default: 2368 /* Only 2 channels are supported per fetch engine. */ 2369 assert(false); 2370 break; 2371 } 2372 } 2373 } 2374 else 2375 { 2376 if (name == kPXP_StoreInput) 2377 { 2378 switch (channel) 2379 { 2380 case 0: 2381 base->INPUT_STORE_CTRL_CH0_CLR = PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK; 2382 break; 2383 2384 case 1: 2385 base->INPUT_STORE_CTRL_CH1_CLR = PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK; 2386 break; 2387 2388 default: 2389 /* Only 2 channels are supported per fetch engine. */ 2390 assert(false); 2391 break; 2392 } 2393 } 2394 else 2395 { 2396 switch (channel) 2397 { 2398 case 0: 2399 base->DITHER_STORE_CTRL_CH0_CLR = PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK; 2400 break; 2401 2402 case 1: 2403 base->DITHER_STORE_CTRL_CH1_CLR = PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK; 2404 break; 2405 2406 default: 2407 /* Only 2 channels are supported per fetch engine. */ 2408 assert(false); 2409 break; 2410 } 2411 } 2412 } 2413 } 2414 2415 /*! 2416 * @brief Combines the 2 channels of some store engine. 2417 * 2418 * Store engine is 32-bit input and 64-bit output per channel. If both channels of store engine's 2419 * input and 8 bits flag contain valid data, then need set combine to true to support total 64-bit input. 2420 * 2421 * @param base PXP peripheral base address. 2422 * @param name the store engine belongs to which block. 2423 * @param combine true to combine the 2 channels. 2424 */ 2425 static inline void PXP_CombineStoreEngineChannel(PXP_Type *base, pxp_store_engine_name_t name, bool combine) 2426 { 2427 if (name == kPXP_StoreInput) 2428 { 2429 if (combine) 2430 { 2431 base->INPUT_STORE_CTRL_CH0_SET = PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK; 2432 } 2433 else 2434 { 2435 base->INPUT_STORE_CTRL_CH0_CLR = PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK; 2436 } 2437 } 2438 else 2439 { 2440 if (combine) 2441 { 2442 base->DITHER_STORE_CTRL_CH0_SET = PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK; 2443 } 2444 else 2445 { 2446 base->DITHER_STORE_CTRL_CH0_CLR = PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK; 2447 } 2448 } 2449 } 2450 /* @} */ 2451 2452 /*! 2453 * @name Pre-dither CFA engine 2454 * @{ 2455 */ 2456 /*! 2457 * @brief Configures the pre-dither CFA engine. 2458 * 2459 * @param base PXP peripheral base address. 2460 * @param config pointer to the configuration structure. 2461 * @retval kStatus_Success Successfully configured the engine. 2462 * @retval kStatus_InvalidArgument Invalid argument. 2463 */ 2464 status_t PXP_SetCfaConfig(PXP_Type *base, const pxp_cfa_config_t *config); 2465 2466 /*! 2467 * @brief Enables/disables the CFA block. 2468 * 2469 * @param base PXP peripheral base address. 2470 * @param enable true to enable, false to disable. 2471 */ 2472 static inline void PXP_EnableCfa(PXP_Type *base, bool enable) 2473 { 2474 if (enable) 2475 { 2476 base->CFA_CTRL_CLR = PXP_CFA_CTRL_CFA_BYPASS_MASK; 2477 } 2478 else 2479 { 2480 base->CFA_CTRL_SET = PXP_CFA_CTRL_CFA_BYPASS_MASK; 2481 } 2482 } 2483 /* @} */ 2484 2485 /*! 2486 * @name Histogram engine 2487 * @{ 2488 */ 2489 /*! 2490 * @brief Configures histogram engine. 2491 * 2492 * @param base PXP peripheral base address. 2493 * @param num instance number. 2494 * @param config pointer to the configuration structure. 2495 * @retval kStatus_Success Successfully configured the engine. 2496 * @retval kStatus_InvalidArgument Invalid argument. 2497 */ 2498 status_t PXP_SetHistogramConfig(PXP_Type *base, uint8_t num, const pxp_histogram_config_t *config); 2499 2500 /*! 2501 * @brief Enables/disables the histogram engine. 2502 * 2503 * @param base PXP peripheral base address. 2504 * @param num instance number. 2505 * @param enable true to enable, false to disable. 2506 */ 2507 static inline void PXP_EnableHistogram(PXP_Type *base, uint8_t num, bool enable) 2508 { 2509 switch (num) 2510 { 2511 case 0: 2512 base->HIST_A_CTRL = 2513 (base->HIST_A_CTRL & ~PXP_HIST_A_CTRL_ENABLE_MASK) | PXP_HIST_A_CTRL_ENABLE((uint32_t)enable); 2514 break; 2515 2516 case 1: 2517 base->HIST_B_CTRL = 2518 (base->HIST_B_CTRL & ~PXP_HIST_B_CTRL_ENABLE_MASK) | PXP_HIST_B_CTRL_ENABLE((uint32_t)enable); 2519 break; 2520 2521 default: 2522 /* Only 2 instances are supported per fetch engine. */ 2523 assert(false); 2524 break; 2525 } 2526 } 2527 2528 /*! 2529 * @brief Gets the results of histogram mask operation. 2530 * 2531 * @param base PXP peripheral base address. 2532 * @param num instance number. 2533 * @param result pointer to the result structure. 2534 */ 2535 void PXP_GetHistogramMaskResult(PXP_Type *base, uint8_t num, pxp_histogram_mask_result_t *result); 2536 2537 /*! 2538 * @brief Gets the PXP Histogram operation result 2539 * 2540 * @param base PXP peripheral base address. 2541 * @param num instance number. 2542 * @return bit map of the match result in @ref _pxp_histgram_flags ORed together 2543 */ 2544 static inline uint8_t PXP_GetHistogramMatchResult(PXP_Type *base, uint8_t num) 2545 { 2546 uint8_t result = 0U; 2547 switch (num) 2548 { 2549 case 0: 2550 result = (uint8_t)((base->HIST_A_CTRL & PXP_HIST_A_CTRL_STATUS_MASK) >> PXP_HIST_A_CTRL_STATUS_SHIFT); 2551 break; 2552 2553 case 1: 2554 result = (uint8_t)((base->HIST_B_CTRL & PXP_HIST_B_CTRL_STATUS_MASK) >> PXP_HIST_B_CTRL_STATUS_SHIFT); 2555 break; 2556 2557 default: 2558 /* Only 2 histogram instances are supported. */ 2559 assert(false); 2560 break; 2561 } 2562 2563 return result; 2564 } 2565 2566 /*! 2567 * @brief Clears the current histogram operation result. 2568 * 2569 * Clears the current histogram operation result, including mask operation result and from 2-level to 32-level match 2570 * result. 2571 * 2572 * @param base PXP peripheral base address. 2573 * @param num instance number. 2574 */ 2575 static inline void PXP_ClearHistogramResult(PXP_Type *base, uint8_t num) 2576 { 2577 switch (num) 2578 { 2579 case 0: 2580 base->HIST_A_CTRL |= PXP_HIST_A_CTRL_CLEAR_MASK; 2581 break; 2582 2583 case 1: 2584 base->HIST_B_CTRL |= PXP_HIST_B_CTRL_CLEAR_MASK; 2585 break; 2586 2587 default: 2588 /* Only 2 histogram instances are supported. */ 2589 assert(false); 2590 break; 2591 } 2592 } 2593 2594 /*! 2595 * @brief Gets the results of histogram mask operation. 2596 * 2597 * @param base PXP peripheral base address. 2598 * @param num instance number. 2599 * @param width the width of the updated block 2600 * @param height the height of the updated block 2601 */ 2602 static inline void PXP_SetHistogramSize(PXP_Type *base, uint8_t num, uint16_t width, uint16_t height) 2603 { 2604 switch (num) 2605 { 2606 case 0: 2607 base->HIST_A_BUF_SIZE = ((uint32_t)height << 16U) | (uint32_t)width; 2608 break; 2609 2610 case 1: 2611 base->HIST_B_BUF_SIZE = ((uint32_t)height << 16U) | (uint32_t)width; 2612 break; 2613 2614 default: 2615 /* Only 2 histogram instances are supported. */ 2616 assert(false); 2617 break; 2618 } 2619 } 2620 /* @} */ 2621 2622 /*! 2623 * @name WFE engine 2624 * @{ 2625 */ 2626 2627 /*! 2628 * @brief Initializes the WFE-A engine for waveform process. 2629 * 2630 * @param base PXP peripheral base address. 2631 * @param ditherHandshake true to enable handshake mode with upstream dither store engine. 2632 */ 2633 void PXP_WfeaInit(PXP_Type *base, bool ditherHandshake); 2634 2635 /*! 2636 * @brief Enables/disables hanshake mode with upstream dither engine. 2637 * 2638 * @param base PXP peripheral base address. 2639 * @param enable true to enable handshake mode with upstream dither store engine. 2640 */ 2641 static inline void PXP_WfeaEnableDitherHandshake(PXP_Type *base, bool enable) 2642 { 2643 if (enable) 2644 { 2645 base->WFA_FETCH_CTRL |= PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_MASK; 2646 } 2647 else 2648 { 2649 base->WFA_FETCH_CTRL &= ~PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_MASK; 2650 } 2651 } 2652 2653 /*! 2654 * @brief Configure the WFE-A engine 2655 * 2656 * @param base PXP peripheral base address. 2657 * @param config pointer to the configuration structure. 2658 */ 2659 void PXP_SetWfeaConfig(PXP_Type *base, const pxp_wfea_engine_config_t *config); 2660 2661 /*! 2662 * @brief Sets the LUT usage status for waveform engine. 2663 * 2664 * If any EPDC LUT(s) has been occupied, use this API to set its usage for PXP WFE-A. 2665 * 2666 * @param base PXP base pointer 2667 * @param lutStatus the status mask of the LUT(s) to be set, can be a single flag or several flags up to all 64 LUTs. 2668 * If user wants to set LUT17 usage, set bit 17 in the lutStatus. 2669 */ 2670 static inline void PXP_SetLutUsage(PXP_Type *base, uint64_t lutStatus) 2671 { 2672 base->WFE_A_STG1_8X1_OUT0_0 |= (uint32_t)lutStatus; 2673 base->WFE_A_STG1_8X1_OUT0_1 |= (uint32_t)(lutStatus >> 32U); 2674 } 2675 2676 /*! 2677 * @brief Clears the LUT usage status for waveform engine. 2678 * 2679 * If any EPDC LUT(s) has finished processing and is(are) free, use this API to clear its usage for PXP WFE-A. 2680 * 2681 * @param base PXP base pointer 2682 * @param lutStatus the status mask of the LUT(s) to be cleared, can be a single flag or several flags up to all 64 2683 * LUTs. If user wants to clear LUT17, set bit 17. 2684 */ 2685 static inline void PXP_ClearLutUsage(PXP_Type *base, uint64_t lutStatus) 2686 { 2687 base->WFE_A_STG1_8X1_OUT0_0 &= ~(uint32_t)lutStatus; 2688 base->WFE_A_STG1_8X1_OUT0_1 &= ~(uint32_t)(lutStatus >> 32U); 2689 } 2690 2691 /*! 2692 * @brief Gets the occupied LUT list. 2693 * 2694 * @param base PXP base pointer 2695 * @return lutStatus the status mask of the LUT(s) that is(are) occupied 2696 */ 2697 static inline uint64_t PXP_GetLutUsage(PXP_Type *base) 2698 { 2699 return ((uint64_t)base->WFE_A_STG1_8X1_OUT0_0 | (uint64_t)base->WFE_A_STG1_8X1_OUT0_1 << 32U); 2700 } 2701 2702 /* @} */ 2703 2704 #endif /* FSL_FEATURE_PXP_V3 */ 2705 2706 #if defined(__cplusplus) 2707 } 2708 #endif 2709 2710 /*! @}*/ 2711 2712 #endif /* _FSL_PXP_H_ */
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