drivers/pit/fsl_pit.c

0001 /*
0002  * Copyright (c) 2015, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2017 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #include "fsl_pit.h"
0010
0011 /* Component ID definition, used by tools. */
0012 #ifndef FSL_COMPONENT_ID
0013 #define FSL_COMPONENT_ID "platform.drivers.pit"
0014 #endif
0015
0016 /*******************************************************************************
0017  * Prototypes
0018  ******************************************************************************/
0019 /*!
0020  * @brief Gets the instance from the base address to be used to gate or ungate the module clock
0021  *
0022  * @param base PIT peripheral base address
0023  *
0024  * @return The PIT instance
0025  */
0026 static uint32_t PIT_GetInstance(PIT_Type *base);
0027
0028 /*******************************************************************************
0029  * Variables
0030  ******************************************************************************/
0031 /*! @brief Pointers to PIT bases for each instance. */
0032 static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS;
0033
0034 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0035 /*! @brief Pointers to PIT clocks for each instance. */
0036 static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS;
0037 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0038
0039 /*******************************************************************************
0040  * Code
0041  ******************************************************************************/
0042 static uint32_t PIT_GetInstance(PIT_Type *base)
0043 {
0044     uint32_t instance;
0045
0046     /* Find the instance index from base address mappings. */
0047     for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++)
0048     {
0049         if (s_pitBases[instance] == base)
0050         {
0051             break;
0052         }
0053     }
0054
0055     assert(instance < ARRAY_SIZE(s_pitBases));
0056
0057     return instance;
0058 }
0059
0060 /*!
0061  * brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations.
0062  *
0063  * note This API should be called at the beginning of the application using the PIT driver.
0064  *
0065  * param base   PIT peripheral base address
0066  * param config Pointer to the user's PIT config structure
0067  */
0068 void PIT_Init(PIT_Type *base, const pit_config_t *config)
0069 {
0070     assert(NULL != config);
0071
0072 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0073     /* Ungate the PIT clock*/
0074     CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]);
0075 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0076
0077 #if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS
0078     /* Enable PIT timers */
0079     base->MCR &= ~PIT_MCR_MDIS_MASK;
0080 #endif
0081
0082 #if defined(FSL_FEATURE_PIT_TIMER_COUNT) && (FSL_FEATURE_PIT_TIMER_COUNT)
0083     /* Clear all status bits for all channels to make sure the status of all TCTRL registers is clean. */
0084     for (uint8_t i = 0U; i < (uint32_t)FSL_FEATURE_PIT_TIMER_COUNT; i++)
0085     {
0086         base->CHANNEL[i].TCTRL &= ~(PIT_TCTRL_TEN_MASK | PIT_TCTRL_TIE_MASK | PIT_TCTRL_CHN_MASK);
0087     }
0088 #endif /* FSL_FEATURE_PIT_TIMER_COUNT */
0089
0090     /* Config timer operation when in debug mode */
0091     if (true == config->enableRunInDebug)
0092     {
0093         base->MCR &= ~PIT_MCR_FRZ_MASK;
0094     }
0095     else
0096     {
0097         base->MCR |= PIT_MCR_FRZ_MASK;
0098     }
0099 }
0100
0101 /*!
0102  * brief Gates the PIT clock and disables the PIT module.
0103  *
0104  * param base PIT peripheral base address
0105  */
0106 void PIT_Deinit(PIT_Type *base)
0107 {
0108 #if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS
0109     /* Disable PIT timers */
0110     base->MCR |= PIT_MCR_MDIS_MASK;
0111 #endif
0112
0113 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0114     /* Gate the PIT clock*/
0115     CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]);
0116 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0117 }
0118
0119 #if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
0120
0121 /*!
0122  * brief Reads the current lifetime counter value.
0123  *
0124  * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together.
0125  * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer.
0126  * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1".
0127  * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit
0128  * has the value of timer 0.
0129  *
0130  * param base PIT peripheral base address
0131  *
0132  * return Current lifetime timer value
0133  */
0134 uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base)
0135 {
0136     uint32_t valueH = 0U;
0137     uint32_t valueL = 0U;
0138
0139     /* LTMR64H should be read before LTMR64L */
0140     valueH = base->LTMR64H;
0141     valueL = base->LTMR64L;
0142
0143     return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
0144 }
0145
0146 #endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */