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0001 /* 0002 * Copyright (c) 2015, Freescale Semiconductor, Inc. 0003 * Copyright 2016-2022 NXP 0004 * All rights reserved. 0005 * 0006 * SPDX-License-Identifier: BSD-3-Clause 0007 */ 0008 #ifndef _FSL_MU_H_ 0009 #define _FSL_MU_H_ 0010 0011 #include "fsl_common.h" 0012 0013 /*! 0014 * @addtogroup mu 0015 * @{ 0016 */ 0017 0018 /****************************************************************************** 0019 * Definitions 0020 *****************************************************************************/ 0021 0022 /* Compatibility Macros */ 0023 #ifndef MU_CR_NMI_MASK 0024 #define MU_CR_NMI_MASK 0U 0025 #endif 0026 0027 #if (defined(FSL_FEATURE_MU_HAS_RESET_INT) && FSL_FEATURE_MU_HAS_RESET_INT) 0028 0029 #ifndef FSL_FEATURE_MU_HAS_RESET_ASSERT_INT 0030 #define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT 1 0031 #endif 0032 0033 #ifndef FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT 0034 #define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT 1 0035 #endif 0036 0037 #endif /* FSL_FEATURE_MU_HAS_RESET_INT */ 0038 0039 /*! @name Driver version */ 0040 /*@{*/ 0041 /*! @brief MU driver version. */ 0042 #define FSL_MU_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) 0043 /*@}*/ 0044 0045 /*! 0046 * @brief MU status flags. 0047 */ 0048 enum _mu_status_flags 0049 { 0050 kMU_Tx0EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 3U)), /*!< TX0 empty. */ 0051 kMU_Tx1EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 2U)), /*!< TX1 empty. */ 0052 kMU_Tx2EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 1U)), /*!< TX2 empty. */ 0053 kMU_Tx3EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 0U)), /*!< TX3 empty. */ 0054 0055 kMU_Rx0FullFlag = (1U << (MU_SR_RFn_SHIFT + 3U)), /*!< RX0 full. */ 0056 kMU_Rx1FullFlag = (1U << (MU_SR_RFn_SHIFT + 2U)), /*!< RX1 full. */ 0057 kMU_Rx2FullFlag = (1U << (MU_SR_RFn_SHIFT + 1U)), /*!< RX2 full. */ 0058 kMU_Rx3FullFlag = (1U << (MU_SR_RFn_SHIFT + 0U)), /*!< RX3 full. */ 0059 0060 kMU_GenInt0Flag = (1U << (MU_SR_GIPn_SHIFT + 3U)), /*!< General purpose interrupt 0 pending. */ 0061 kMU_GenInt1Flag = (1U << (MU_SR_GIPn_SHIFT + 2U)), /*!< General purpose interrupt 1 pending. */ 0062 kMU_GenInt2Flag = (1U << (MU_SR_GIPn_SHIFT + 1U)), /*!< General purpose interrupt 2 pending. */ 0063 kMU_GenInt3Flag = (1U << (MU_SR_GIPn_SHIFT + 0U)), /*!< General purpose interrupt 3 pending. */ 0064 0065 kMU_EventPendingFlag = MU_SR_EP_MASK, /*!< MU event pending. */ 0066 kMU_FlagsUpdatingFlag = MU_SR_FUP_MASK, /*!< MU flags update is on-going. */ 0067 0068 #if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) 0069 kMU_ResetAssertInterruptFlag = MU_SR_RAIP_MASK, /*!< The other core reset assert interrupt pending. */ 0070 #endif 0071 #if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) 0072 kMU_ResetDeassertInterruptFlag = MU_SR_RDIP_MASK, /*!< The other core reset de-assert interrupt pending. */ 0073 #endif 0074 0075 #if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) 0076 kMU_OtherSideInResetFlag = MU_SR_RS_MASK, /*!< The other side is in reset. */ 0077 #endif 0078 0079 #if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) 0080 kMU_MuResetInterruptFlag = MU_SR_MURIP_MASK, /*!< The other side initializes MU reset. */ 0081 #endif 0082 #if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) 0083 kMU_HardwareResetInterruptFlag = MU_SR_HRIP_MASK, /*!< Current side has been hardware reset by the other side. */ 0084 #endif 0085 }; 0086 0087 /*! 0088 * @brief MU interrupt source to enable. 0089 */ 0090 enum _mu_interrupt_enable 0091 { 0092 kMU_Tx0EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 3U)), /*!< TX0 empty. */ 0093 kMU_Tx1EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 2U)), /*!< TX1 empty. */ 0094 kMU_Tx2EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 1U)), /*!< TX2 empty. */ 0095 kMU_Tx3EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 0U)), /*!< TX3 empty. */ 0096 0097 kMU_Rx0FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 3U)), /*!< RX0 full. */ 0098 kMU_Rx1FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 2U)), /*!< RX1 full. */ 0099 kMU_Rx2FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 1U)), /*!< RX2 full. */ 0100 kMU_Rx3FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 0U)), /*!< RX3 full. */ 0101 0102 kMU_GenInt0InterruptEnable = (int)(1U << (MU_CR_GIEn_SHIFT + 3U)), /*!< General purpose interrupt 0. */ 0103 kMU_GenInt1InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 2U)), /*!< General purpose interrupt 1. */ 0104 kMU_GenInt2InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 1U)), /*!< General purpose interrupt 2. */ 0105 kMU_GenInt3InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 0U)), /*!< General purpose interrupt 3. */ 0106 0107 #if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) 0108 kMU_ResetAssertInterruptEnable = MU_CR_RAIE_MASK, /*!< The other core reset assert interrupt. */ 0109 #endif 0110 #if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) 0111 kMU_ResetDeassertInterruptEnable = MU_CR_RDIE_MASK, /*!< The other core reset de-assert interrupt. */ 0112 #endif 0113 #if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) 0114 kMU_MuResetInterruptEnable = MU_CR_MURIE_MASK, /*!< The other side initializes MU reset. The interrupt 0115 is ORed with the general purpose interrupt 3. The 0116 general purpose interrupt 3 is issued when the other side 0117 set the MU reset and this interrupt is enabled. */ 0118 #endif 0119 #if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) 0120 kMU_HardwareResetInterruptEnable = MU_CR_HRIE_MASK, /*!< Current side has been hardware reset by the other side. */ 0121 #endif 0122 }; 0123 0124 /*! 0125 * @brief MU interrupt that could be triggered to the other core. 0126 */ 0127 enum _mu_interrupt_trigger 0128 { 0129 #if !(defined(FSL_FEATURE_MU_NO_NMI) && FSL_FEATURE_MU_NO_NMI) 0130 kMU_NmiInterruptTrigger = MU_CR_NMI_MASK, /*!< NMI interrupt. */ 0131 #endif 0132 kMU_GenInt0InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 3U)), /*!< General purpose interrupt 0. */ 0133 kMU_GenInt1InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 2U)), /*!< General purpose interrupt 1. */ 0134 kMU_GenInt2InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 1U)), /*!< General purpose interrupt 2. */ 0135 kMU_GenInt3InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 0U)) /*!< General purpose interrupt 3. */ 0136 }; 0137 0138 /*! 0139 * @brief MU message register. 0140 */ 0141 typedef enum _mu_msg_reg_index 0142 { 0143 kMU_MsgReg0 = 0, 0144 kMU_MsgReg1, 0145 kMU_MsgReg2, 0146 kMU_MsgReg3, 0147 } mu_msg_reg_index_t; 0148 0149 /******************************************************************************* 0150 * API 0151 ******************************************************************************/ 0152 0153 #if defined(__cplusplus) 0154 extern "C" { 0155 #endif 0156 0157 /*! 0158 * @name MU initialization. 0159 * @{ 0160 */ 0161 /*! 0162 * @brief Initializes the MU module. 0163 * 0164 * This function enables the MU clock only. 0165 * 0166 * @param base MU peripheral base address. 0167 */ 0168 void MU_Init(MU_Type *base); 0169 0170 /*! 0171 * @brief De-initializes the MU module. 0172 * 0173 * This function disables the MU clock only. 0174 * 0175 * @param base MU peripheral base address. 0176 */ 0177 void MU_Deinit(MU_Type *base); 0178 0179 /* @} */ 0180 0181 /*! 0182 * @name MU Message 0183 * @{ 0184 */ 0185 0186 /*! 0187 * @brief Writes a message to the TX register. 0188 * 0189 * This function writes a message to the specific TX register. It does not check 0190 * whether the TX register is empty or not. The upper layer should make sure the TX 0191 * register is empty before calling this function. This function can be used 0192 * in ISR for better performance. 0193 * 0194 * @code 0195 * while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { } Wait for TX0 register empty. 0196 * MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG_VAL); Write message to the TX0 register. 0197 * @endcode 0198 * 0199 * @param base MU peripheral base address. 0200 * @param regIndex TX register index, see @ref mu_msg_reg_index_t. 0201 * @param msg Message to send. 0202 */ 0203 static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg) 0204 { 0205 assert(regIndex < MU_TR_COUNT); 0206 0207 base->TR[regIndex] = msg; 0208 } 0209 0210 /*! 0211 * @brief Blocks to send a message. 0212 * 0213 * This function waits until the TX register is empty and sends the message. 0214 * 0215 * @param base MU peripheral base address. 0216 * @param regIndex MU message register, see @ref mu_msg_reg_index_t 0217 * @param msg Message to send. 0218 */ 0219 void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg); 0220 0221 /*! 0222 * @brief Reads a message from the RX register. 0223 * 0224 * This function reads a message from the specific RX register. It does not check 0225 * whether the RX register is full or not. The upper layer should make sure the RX 0226 * register is full before calling this function. This function can be used 0227 * in ISR for better performance. 0228 * 0229 * @code 0230 * uint32_t msg; 0231 * while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base))) 0232 * { 0233 * } Wait for the RX0 register full. 0234 * 0235 * msg = MU_ReceiveMsgNonBlocking(base, kMU_MsgReg0); Read message from RX0 register. 0236 * @endcode 0237 * 0238 * @param base MU peripheral base address. 0239 * @param RX register index, see @ref mu_msg_reg_index_t. 0240 * @return The received message. 0241 */ 0242 static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex) 0243 { 0244 assert(regIndex < MU_TR_COUNT); 0245 0246 return base->RR[regIndex]; 0247 } 0248 0249 /*! 0250 * @brief Blocks to receive a message. 0251 * 0252 * This function waits until the RX register is full and receives the message. 0253 * 0254 * @param base MU peripheral base address. 0255 * @param regIndex MU message register, see @ref mu_msg_reg_index_t 0256 * @return The received message. 0257 */ 0258 uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex); 0259 0260 /* @} */ 0261 0262 /*! 0263 * @name MU Flags 0264 * @{ 0265 */ 0266 0267 /*! 0268 * @brief Sets the 3-bit MU flags reflect on the other MU side. 0269 * 0270 * This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, 0271 * the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are 0272 * updating to the other side. After the 3-bit MU flags are updated, the status flag 0273 * \c kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, 0274 * the flags cannot be changed. The upper layer should make sure the status flag 0275 * \c kMU_FlagsUpdatingFlag is cleared before calling this function. 0276 * 0277 * @code 0278 * while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base)) 0279 * { 0280 * } Wait for previous MU flags updating. 0281 * 0282 * MU_SetFlagsNonBlocking(base, 0U); Set the mU flags. 0283 * @endcode 0284 * 0285 * @param base MU peripheral base address. 0286 * @param flags The 3-bit MU flags to set. 0287 */ 0288 static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags) 0289 { 0290 uint32_t reg = base->CR; 0291 reg = (reg & ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | MU_CR_Fn_MASK)) | MU_CR_Fn(flags); 0292 base->CR = reg; 0293 } 0294 0295 /*! 0296 * @brief Blocks setting the 3-bit MU flags reflect on the other MU side. 0297 * 0298 * This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, 0299 * the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are 0300 * updating to the other side. After the 3-bit MU flags are updated, the status flag 0301 * \c kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, 0302 * the flags cannot be changed. This function waits for the MU status flag 0303 * \c kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags. 0304 * 0305 * @param base MU peripheral base address. 0306 * @param flags The 3-bit MU flags to set. 0307 */ 0308 void MU_SetFlags(MU_Type *base, uint32_t flags); 0309 0310 /*! 0311 * @brief Gets the current value of the 3-bit MU flags set by the other side. 0312 * 0313 * This function gets the current 3-bit MU flags on the current side. 0314 * 0315 * @param base MU peripheral base address. 0316 * @return flags Current value of the 3-bit flags. 0317 */ 0318 static inline uint32_t MU_GetFlags(MU_Type *base) 0319 { 0320 return (base->SR & MU_SR_Fn_MASK) >> MU_SR_Fn_SHIFT; 0321 } 0322 0323 /* @} */ 0324 0325 /*! 0326 * @name Status and Interrupt. 0327 * @{ 0328 */ 0329 0330 /*! 0331 * @brief Gets the MU status flags. 0332 * 0333 * This function returns the bit mask of the MU status flags. See _mu_status_flags. 0334 * 0335 * @code 0336 * uint32_t flags; 0337 * flags = MU_GetStatusFlags(base); Get all status flags. 0338 * if (kMU_Tx0EmptyFlag & flags) 0339 * { 0340 * The TX0 register is empty. Message can be sent. 0341 * MU_SendMsgNonBlocking(base, kMU_MsgReg0, MSG0_VAL); 0342 * } 0343 * if (kMU_Tx1EmptyFlag & flags) 0344 * { 0345 * The TX1 register is empty. Message can be sent. 0346 * MU_SendMsgNonBlocking(base, kMU_MsgReg1, MSG1_VAL); 0347 * } 0348 * @endcode 0349 * 0350 * @param base MU peripheral base address. 0351 * @return Bit mask of the MU status flags, see _mu_status_flags. 0352 */ 0353 static inline uint32_t MU_GetStatusFlags(MU_Type *base) 0354 { 0355 return (base->SR & (MU_SR_TEn_MASK | MU_SR_RFn_MASK | MU_SR_GIPn_MASK | MU_SR_EP_MASK | MU_SR_FUP_MASK 0356 #if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) 0357 | MU_SR_RS_MASK 0358 #endif 0359 #if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) 0360 | MU_SR_RAIP_MASK 0361 #endif 0362 #if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) 0363 | MU_SR_RDIP_MASK 0364 #endif 0365 #if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) 0366 | MU_SR_MURIP_MASK 0367 #endif 0368 #if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) 0369 | MU_SR_HRIP_MASK 0370 #endif 0371 )); 0372 } 0373 0374 /*! 0375 * @brief Gets the MU IRQ pending status. 0376 * 0377 * This function returns the bit mask of the pending MU IRQs. 0378 * 0379 * @param base MU peripheral base address. 0380 * @return Bit mask of the MU IRQs pending. 0381 */ 0382 static inline uint32_t MU_GetInterruptsPending(MU_Type *base) 0383 { 0384 uint32_t irqMask = base->CR & (MU_CR_GIEn_MASK | MU_CR_TIEn_MASK | MU_CR_RIEn_MASK); 0385 return (base->SR & irqMask); 0386 } 0387 0388 /*! 0389 * @brief Clears the specific MU status flags. 0390 * 0391 * This function clears the specific MU status flags. The flags to clear should 0392 * be passed in as bit mask. See _mu_status_flags. 0393 * 0394 * @code 0395 * Clear general interrupt 0 and general interrupt 1 pending flags. 0396 * MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag); 0397 * @endcode 0398 * 0399 * @param base MU peripheral base address. 0400 * @param mask Bit mask of the MU status flags. See _mu_status_flags. The following 0401 * flags are cleared by hardware, this function could not clear them. 0402 * - kMU_Tx0EmptyFlag 0403 * - kMU_Tx1EmptyFlag 0404 * - kMU_Tx2EmptyFlag 0405 * - kMU_Tx3EmptyFlag 0406 * - kMU_Rx0FullFlag 0407 * - kMU_Rx1FullFlag 0408 * - kMU_Rx2FullFlag 0409 * - kMU_Rx3FullFlag 0410 * - kMU_EventPendingFlag 0411 * - kMU_FlagsUpdatingFlag 0412 * - kMU_OtherSideInResetFlag 0413 */ 0414 static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t mask) 0415 { 0416 /* regMask is the mask of w1c status bits. */ 0417 uint32_t regMask = MU_SR_GIPn_MASK; 0418 0419 #if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) 0420 regMask |= MU_SR_RAIP_MASK; 0421 #endif 0422 #if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) 0423 regMask |= MU_SR_RDIP_MASK; 0424 #endif 0425 0426 #if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) 0427 regMask |= MU_SR_MURIP_MASK; 0428 #endif 0429 0430 #if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) 0431 regMask |= MU_SR_HRIP_MASK; 0432 #endif 0433 0434 base->SR = (mask & regMask); 0435 } 0436 0437 /*! 0438 * @brief Enables the specific MU interrupts. 0439 * 0440 * This function enables the specific MU interrupts. The interrupts to enable 0441 * should be passed in as bit mask. See _mu_interrupt_enable. 0442 * 0443 * @code 0444 * Enable general interrupt 0 and TX0 empty interrupt. 0445 * MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable); 0446 * @endcode 0447 * 0448 * @param base MU peripheral base address. 0449 * @param mask Bit mask of the MU interrupts. See _mu_interrupt_enable. 0450 */ 0451 static inline void MU_EnableInterrupts(MU_Type *base, uint32_t mask) 0452 { 0453 uint32_t reg = base->CR; 0454 reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask; 0455 base->CR = reg; 0456 } 0457 0458 /*! 0459 * @brief Disables the specific MU interrupts. 0460 * 0461 * This function disables the specific MU interrupts. The interrupts to disable 0462 * should be passed in as bit mask. See _mu_interrupt_enable. 0463 * 0464 * @code 0465 * Disable general interrupt 0 and TX0 empty interrupt. 0466 * MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable); 0467 * @endcode 0468 * 0469 * @param base MU peripheral base address. 0470 * @param mask Bit mask of the MU interrupts. See _mu_interrupt_enable. 0471 */ 0472 static inline void MU_DisableInterrupts(MU_Type *base, uint32_t mask) 0473 { 0474 uint32_t reg = base->CR; 0475 reg &= ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | mask); 0476 base->CR = reg; 0477 } 0478 0479 /*! 0480 * @brief Triggers interrupts to the other core. 0481 * 0482 * This function triggers the specific interrupts to the other core. The interrupts 0483 * to trigger are passed in as bit mask. See \ref _mu_interrupt_trigger. 0484 * The MU should not trigger an interrupt to the other core when the previous interrupt 0485 * has not been processed by the other core. This function checks whether the 0486 * previous interrupts have been processed. If not, it returns an error. 0487 * 0488 * @code 0489 * if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger)) 0490 * { 0491 * Previous general purpose interrupt 0 or general purpose interrupt 2 0492 * has not been processed by the other core. 0493 * } 0494 * @endcode 0495 * 0496 * @param base MU peripheral base address. 0497 * @param mask Bit mask of the interrupts to trigger. See _mu_interrupt_trigger. 0498 * @retval kStatus_Success Interrupts have been triggered successfully. 0499 * @retval kStatus_Fail Previous interrupts have not been accepted. 0500 */ 0501 status_t MU_TriggerInterrupts(MU_Type *base, uint32_t mask); 0502 0503 #if !(defined(FSL_FEATURE_MU_NO_NMI) && FSL_FEATURE_MU_NO_NMI) 0504 /*! 0505 * @brief Clear non-maskable interrupt (NMI) sent by the other core. 0506 * 0507 * This function clears non-maskable interrupt (NMI) sent by the other core. 0508 * 0509 * @param base MU peripheral base address. 0510 */ 0511 static inline void MU_ClearNmi(MU_Type *base) 0512 { 0513 base->SR = MU_SR_NMIC_MASK; 0514 } 0515 #endif /* FSL_FEATURE_MU_NO_NMI */ 0516 0517 /* @} */ 0518 0519 /*! 0520 * @name MU misc functions 0521 * @{ 0522 */ 0523 0524 #if !(defined(FSL_FEATURE_MU_NO_RSTH) && FSL_FEATURE_MU_NO_RSTH) 0525 /*! 0526 * @brief Boots the core at B side. 0527 * 0528 * This function sets the B side core's boot configuration and releases the 0529 * core from reset. 0530 * 0531 * @param base MU peripheral base address. 0532 * @param mode Core B boot mode. 0533 * @note Only MU side A can use this function. 0534 */ 0535 void MU_BootCoreB(MU_Type *base, mu_core_boot_mode_t mode); 0536 0537 /*! 0538 * @brief Holds the core reset of B side. 0539 * 0540 * This function causes the core of B side to be held in reset following any reset event. 0541 * 0542 * @param base MU peripheral base address. 0543 * @note Only A side could call this function. 0544 */ 0545 static inline void MU_HoldCoreBReset(MU_Type *base) 0546 { 0547 #if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) 0548 base->CCR |= MU_CCR_RSTH_MASK; 0549 #else /* FSL_FEATURE_MU_HAS_CCR */ 0550 uint32_t reg = base->CR; 0551 reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_RSTH_MASK; 0552 base->CR = reg; 0553 #endif /* FSL_FEATURE_MU_HAS_CCR */ 0554 } 0555 0556 /*! 0557 * @brief Boots the other core. 0558 * 0559 * This function boots the other core with a boot configuration. 0560 * 0561 * @param base MU peripheral base address. 0562 * @param mode The other core boot mode. 0563 */ 0564 void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode); 0565 0566 /*! 0567 * @brief Holds the other core reset. 0568 * 0569 * This function causes the other core to be held in reset following any reset event. 0570 * 0571 * @param base MU peripheral base address. 0572 */ 0573 static inline void MU_HoldOtherCoreReset(MU_Type *base) 0574 { 0575 /* 0576 * MU_HoldOtherCoreReset and MU_HoldCoreBReset are the same, MU_HoldCoreBReset 0577 * is kept for compatible with older platforms. 0578 */ 0579 MU_HoldCoreBReset(base); 0580 } 0581 #endif /* FSL_FEATURE_MU_NO_RSTH */ 0582 0583 #if !(defined(FSL_FEATURE_MU_NO_MUR) && FSL_FEATURE_MU_NO_MUR) 0584 /*! 0585 * @brief Resets the MU for both A side and B side. 0586 * 0587 * This function resets the MU for both A side and B side. Before reset, it is 0588 * recommended to interrupt processor B, because this function may affect the 0589 * ongoing processor B programs. 0590 * 0591 * @param base MU peripheral base address. 0592 * @note For some platforms, only MU side A could use this function, check 0593 * reference manual for details. 0594 */ 0595 static inline void MU_ResetBothSides(MU_Type *base) 0596 { 0597 uint32_t reg = base->CR; 0598 reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_MUR_MASK; 0599 base->CR = reg; 0600 0601 #if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) 0602 /* Wait for the other side out of reset. */ 0603 while (0U != (base->SR & MU_SR_RS_MASK)) 0604 { 0605 } 0606 #endif /* FSL_FEATURE_MU_HAS_SR_RS */ 0607 } 0608 #endif /* FSL_FEATURE_MU_NO_MUR */ 0609 0610 #if (defined(FSL_FEATURE_MU_HAS_HRM) && FSL_FEATURE_MU_HAS_HRM) 0611 /*! 0612 * @brief Mask hardware reset by the other core. 0613 * 0614 * The other core could call MU_HardwareResetOtherCore() to reset current core. 0615 * To mask the reset, call this function and pass in true. 0616 * 0617 * @param base MU peripheral base address. 0618 * @param mask Pass true to mask the hardware reset, pass false to unmask it. 0619 */ 0620 static inline void MU_MaskHardwareReset(MU_Type *base, bool mask) 0621 { 0622 #if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) 0623 if (mask) 0624 { 0625 base->CCR |= MU_CCR_HRM_MASK; 0626 } 0627 else 0628 { 0629 base->CCR &= ~MU_CCR_HRM_MASK; 0630 } 0631 #else /* FSL_FEATURE_MU_HAS_CCR */ 0632 if (mask) 0633 { 0634 base->CR |= MU_CR_HRM_MASK; 0635 } 0636 else 0637 { 0638 base->CR &= ~MU_CR_HRM_MASK; 0639 } 0640 #endif /* FSL_FEATURE_MU_HAS_CCR */ 0641 } 0642 #endif /* FSL_FEATURE_MU_HAS_HRM */ 0643 0644 #if !(defined(FSL_FEATURE_MU_NO_HR) && FSL_FEATURE_MU_NO_HR) 0645 /*! 0646 * @brief Hardware reset the other core. 0647 * 0648 * This function resets the other core, the other core could mask the 0649 * hardware reset by calling MU_MaskHardwareReset. The hardware reset 0650 * mask feature is only available for some platforms. 0651 * This function could be used together with MU_BootOtherCore to control the 0652 * other core reset workflow. 0653 * 0654 * Example 1: Reset the other core, and no hold reset 0655 * @code 0656 * MU_HardwareResetOtherCore(MU_A, true, false, bootMode); 0657 * @endcode 0658 * In this example, the core at MU side B will reset with the specified boot mode. 0659 * 0660 * Example 2: Reset the other core and hold it, then boot the other core later. 0661 * @code 0662 * Here the other core enters reset, and the reset is hold 0663 * MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare); 0664 * Current core boot the other core when necessary. 0665 * MU_BootOtherCore(MU_A, bootMode); 0666 * @endcode 0667 * 0668 * @param base MU peripheral base address. 0669 * @param waitReset Wait the other core enters reset. 0670 * - true: Wait until the other core enters reset, if the other 0671 * core has masked the hardware reset, then this function will 0672 * be blocked. 0673 * - false: Don't wait the reset. 0674 * @param holdReset Hold the other core reset or not. 0675 * - true: Hold the other core in reset, this function returns 0676 * directly when the other core enters reset. 0677 * - false: Don't hold the other core in reset, this function 0678 * waits until the other core out of reset. 0679 * @param bootMode Boot mode of the other core, if @p holdReset is true, this 0680 * parameter is useless. 0681 */ 0682 void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode); 0683 #endif /* FSL_FEATURE_MU_NO_HR */ 0684 0685 #if !(defined(FSL_FEATURE_MU_NO_CLKE) && FSL_FEATURE_MU_NO_CLKE) 0686 /*! 0687 * @brief Enables or disables the clock on the other core. 0688 * 0689 * This function enables or disables the platform clock on the other core when 0690 * that core enters a stop mode. If disabled, the platform clock for the other 0691 * core is disabled when it enters stop mode. If enabled, the platform clock 0692 * keeps running on the other core in stop mode, until this core also enters 0693 * stop mode. 0694 * 0695 * @param base MU peripheral base address. 0696 * @param enable Enable or disable the clock on the other core. 0697 */ 0698 static inline void MU_SetClockOnOtherCoreEnable(MU_Type *base, bool enable) 0699 { 0700 #if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) 0701 if (enable) 0702 { 0703 base->CCR |= MU_CCR_CLKE_MASK; 0704 } 0705 else 0706 { 0707 base->CCR &= ~MU_CCR_CLKE_MASK; 0708 } 0709 #else /* FSL_FEATURE_MU_HAS_CCR */ 0710 uint32_t reg = base->CR; 0711 0712 reg &= ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK); 0713 0714 if (enable) 0715 { 0716 reg |= MU_CR_CLKE_MASK; 0717 } 0718 else 0719 { 0720 reg &= ~MU_CR_CLKE_MASK; 0721 } 0722 0723 base->CR = reg; 0724 #endif /* FSL_FEATURE_MU_HAS_CCR */ 0725 } 0726 #endif /* FSL_FEATURE_MU_NO_CLKE */ 0727 0728 #if !(defined(FSL_FEATURE_MU_NO_PM) && FSL_FEATURE_MU_NO_PM) 0729 /*! 0730 * @brief Gets the power mode of the other core. 0731 * 0732 * This function gets the power mode of the other core. 0733 * 0734 * @param base MU peripheral base address. 0735 * @return Power mode of the other core. 0736 */ 0737 static inline mu_power_mode_t MU_GetOtherCorePowerMode(MU_Type *base) 0738 { 0739 uint32_t ret = (base->SR & MU_SR_PM_MASK) >> MU_SR_PM_SHIFT; 0740 0741 return (mu_power_mode_t)ret; 0742 } 0743 #endif /* FSL_FEATURE_MU_NO_PM */ 0744 0745 /* @} */ 0746 0747 #if defined(__cplusplus) 0748 } 0749 #endif /*_cplusplus*/ 0750 /*@}*/ 0751 0752 #endif /* _FSL_MU_H_*/
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