drivers/mipi_dsi_split/fsl_mipi_dsi.h

0001 /*
0002  * Copyright 2020-2022 NXP
0003  * All rights reserved.
0004  *
0005  * SPDX-License-Identifier: BSD-3-Clause
0006  */
0007
0008 #ifndef _FSL_MIPI_DSI_H_
0009 #define _FSL_MIPI_DSI_H_
0010
0011 #include "fsl_common.h"
0012
0013 /*!
0014  * @addtogroup mipi_dsi
0015  * @{
0016  */
0017
0018 /*******************************************************************************
0019  * Definitions
0020  ******************************************************************************/
0021
0022 /*! @name Driver version */
0023 /*@{*/
0024 #define FSL_MIPI_DSI_DRIVER_VERSION (MAKE_VERSION(2, 2, 3))
0025 /*@}*/
0026
0027 /* The max APB transfer size. */
0028 #define FSL_DSI_TX_MAX_PAYLOAD_BYTE (64U * 4U)
0029 #define FSL_DSI_RX_MAX_PAYLOAD_BYTE (64U * 4U)
0030
0031 /*! @brief MIPI DSI structure definition. */
0032 typedef struct
0033 {
0034     DSI_HOST_Type *host;                        /*!< Pointer to HOST registers. */
0035     DSI_HOST_APB_PKT_IF_Type *apb;              /*!< Pointer to APB registers. */
0036     DSI_HOST_DPI_INTFC_Type *dpi;               /*!< Pointer to DPI registers. */
0037     DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type *dphy; /*!< Pointer to DPHY registers. */
0038 } MIPI_DSI_Type;
0039
0040 /*! @brief Error codes for the MIPI DSI driver. */
0041 enum
0042 {
0043     kStatus_DSI_Busy        = MAKE_STATUS((int32_t)kStatusGroup_MIPI_DSI, 0), /*!< DSI is busy. */
0044     kStatus_DSI_RxDataError = MAKE_STATUS((int32_t)kStatusGroup_MIPI_DSI, 1), /*!< Read data error. */
0045     kStatus_DSI_ErrorReportReceived =
0046         MAKE_STATUS((int32_t)kStatusGroup_MIPI_DSI, 2),                        /*!< Error report package received. */
0047     kStatus_DSI_NotSupported = MAKE_STATUS((int32_t)kStatusGroup_MIPI_DSI, 3), /*!< The transfer type not supported. */
0048 };
0049
0050 /*! @brief MIPI DSI controller configuration. */
0051 typedef struct _dsi_config
0052 {
0053     uint8_t numLanes;              /*!< Number of lanes. */
0054     bool enableNonContinuousHsClk; /*!< In enabled, the high speed clock will enter
0055                                        low power mode between transmissions. */
0056     bool enableTxUlps;             /*!< Enable the TX ULPS. */
0057     bool autoInsertEoTp;           /*!< Insert an EoTp short package when switching from HS to LP. */
0058     uint8_t numExtraEoTp;          /*!< How many extra EoTp to send after the end of a packet. */
0059     uint32_t htxTo_ByteClk;        /*!< HS TX timeout count (HTX_TO) in byte clock. */
0060     uint32_t lrxHostTo_ByteClk;    /*!< LP RX host timeout count (LRX-H_TO) in byte clock. */
0061     uint32_t btaTo_ByteClk;        /*!< Bus turn around timeout count (TA_TO) in byte clock. */
0062 } dsi_config_t;
0063
0064 /*! @brief MIPI DPI interface color coding. */
0065 typedef enum _dsi_dpi_color_coding
0066 {
0067     kDSI_Dpi16BitConfig1 = 0U, /*!< 16-bit configuration 1. RGB565: XXXXXXXX_RRRRRGGG_GGGBBBBB. */
0068     kDSI_Dpi16BitConfig2 = 1U, /*!< 16-bit configuration 2. RGB565: XXXRRRRR_XXGGGGGG_XXXBBBBB. */
0069     kDSI_Dpi16BitConfig3 = 2U, /*!< 16-bit configuration 3. RGB565: XXRRRRRX_XXGGGGGG_XXBBBBBX. */
0070     kDSI_Dpi18BitConfig1 = 3U, /*!< 18-bit configuration 1. RGB666: XXXXXXRR_RRRRGGGG_GGBBBBBB. */
0071     kDSI_Dpi18BitConfig2 = 4U, /*!< 18-bit configuration 2. RGB666: XXRRRRRR_XXGGGGGG_XXBBBBBB. */
0072     kDSI_Dpi24Bit        = 5U, /*!< 24-bit. */
0073 } dsi_dpi_color_coding_t;
0074
0075 /*! @brief MIPI DSI pixel packet type send through DPI interface. */
0076 typedef enum _dsi_dpi_pixel_packet
0077 {
0078     kDSI_PixelPacket16Bit        = 0U, /*!< 16 bit RGB565. */
0079     kDSI_PixelPacket18Bit        = 1U, /*!< 18 bit RGB666 packed. */
0080     kDSI_PixelPacket18BitLoosely = 2U, /*!< 18 bit RGB666 loosely packed into three bytes. */
0081     kDSI_PixelPacket24Bit        = 3U, /*!< 24 bit RGB888, each pixel uses three bytes. */
0082 } dsi_dpi_pixel_packet_t;
0083
0084 /*! @brief _dsi_dpi_polarity_flag DPI signal polarity. */
0085 enum
0086 {
0087     kDSI_DpiVsyncActiveLow  = 0U,         /*!< VSYNC active low. */
0088     kDSI_DpiHsyncActiveLow  = 0U,         /*!< HSYNC active low. */
0089     kDSI_DpiVsyncActiveHigh = (1U << 0U), /*!< VSYNC active high. */
0090     kDSI_DpiHsyncActiveHigh = (1U << 1U), /*!< HSYNC active high. */
0091 };
0092
0093 /*! @brief DPI video mode. */
0094 typedef enum _dsi_dpi_video_mode
0095 {
0096     kDSI_DpiNonBurstWithSyncPulse = 0U, /*!< Non-Burst mode with Sync Pulses. */
0097     kDSI_DpiNonBurstWithSyncEvent = 1U, /*!< Non-Burst mode with Sync Events. */
0098     kDSI_DpiBurst                 = 2U, /*!< Burst mode. */
0099 } dsi_dpi_video_mode_t;
0100
0101 /*! @brief Behavior in BLLP (Blanking or Low-Power Interval). */
0102 typedef enum _dsi_dpi_bllp_mode
0103 {
0104     kDSI_DpiBllpLowPower, /*!< LP mode used in BLLP periods. */
0105     kDSI_DpiBllpBlanking, /*!< Blanking packets used in BLLP periods. */
0106     kDSI_DpiBllpNull,     /*!< Null packets used in BLLP periods. */
0107 } dsi_dpi_bllp_mode_t;
0108
0109 /*! @brief MIPI DSI controller DPI interface configuration. */
0110 typedef struct _dsi_dpi_config
0111 {
0112     uint16_t pixelPayloadSize;             /*!< Maximum number of pixels that should be sent
0113                                               as one DSI packet. Recommended that the line size
0114                                               (in pixels) is evenly divisible by this parameter. */
0115     dsi_dpi_color_coding_t dpiColorCoding; /*!< DPI color coding. */
0116     dsi_dpi_pixel_packet_t pixelPacket;    /*!< Pixel packet format. */
0117
0118     dsi_dpi_video_mode_t videoMode; /*!< Video mode. */
0119     dsi_dpi_bllp_mode_t bllpMode;   /*!< Behavior in BLLP. */
0120
0121     uint8_t polarityFlags; /*!< OR'ed value of _dsi_dpi_polarity_flag controls signal polarity. */
0122     uint16_t hfp;          /*!< Horizontal front porch, in dpi pixel clock. */
0123     uint16_t hbp;          /*!< Horizontal back porch, in dpi pixel clock. */
0124     uint16_t hsw;          /*!< Horizontal sync width, in dpi pixel clock. */
0125     uint8_t vfp;           /*!< Number of lines in vertical front porch. */
0126     uint8_t vbp;           /*!< Number of lines in vertical back porch. */
0127     uint16_t panelHeight;  /*!< Line number in vertical active area. */
0128
0129     uint8_t virtualChannel; /*!< Virtual channel. */
0130 } dsi_dpi_config_t;
0131
0132 /*! @brief MIPI DSI D-PHY configuration. */
0133 typedef struct _dsi_dphy_config
0134 {
0135     uint32_t txHsBitClk_Hz; /*!< The generated HS TX bit clock in Hz. */
0136
0137     uint8_t tClkPre_ByteClk;        /*!< TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE in byte clock.
0138                                          Set how long the controller
0139                                          will wait after enabling clock lane for HS before
0140                                          enabling data lanes for HS. */
0141     uint8_t tClkPost_ByteClk;       /*!< TCLK-POST + T_CLK-TRAIL in byte clock. Set how long the controller
0142                                         will wait before putting clock lane into LP mode after
0143                                         data lanes detected in stop state. */
0144     uint8_t tHsExit_ByteClk;        /*!< THS-EXIT in byte clock. Set how long the controller
0145                                           will wait after the clock lane has been put into LP
0146                                           mode before enabling clock lane for HS again. */
0147     uint32_t tWakeup_EscClk;        /*!< Number of clk_esc clock periods to keep a clock
0148                                          or data lane in Mark-1 state after exiting ULPS. */
0149     uint8_t tHsPrepare_HalfEscClk;  /*!< THS-PREPARE in clk_esc/2. Set how long
0150                                       to drive the LP-00 state before HS transmissions,
0151                                       available values are 2, 3, 4, 5. */
0152     uint8_t tClkPrepare_HalfEscClk; /*!< TCLK-PREPARE in clk_esc/2. Set how long
0153                                      to drive the LP-00 state before HS transmissions,
0154                                      available values are 2, 3. */
0155     uint8_t tHsZero_ByteClk;        /*!< THS-ZERO in clk_byte. Set how long that controller
0156                                       drives data lane HS-0 state before transmit
0157                                       the Sync sequence. Available values are 6, 7, ..., 37. */
0158     uint8_t tClkZero_ByteClk;       /*!< TCLK-ZERO in clk_byte. Set how long that controller
0159                                       drives clock lane HS-0 state before transmit
0160                                       the Sync sequence. Available values are 3, 4, ..., 66. */
0161     uint8_t tHsTrail_ByteClk;       /*!< THS-TRAIL + 4*UI in clk_byte. Set the time
0162                                        of the flipped differential state after last payload
0163                                        data bit of HS transmission burst. Available values
0164                                        are 0, 1, ..., 15. */
0165     uint8_t tClkTrail_ByteClk;      /*!< TCLK-TRAIL + 4*UI in clk_byte. Set the time
0166                                        of the flipped differential state after last payload
0167                                        data bit of HS transmission burst. Available values
0168                                        are 0, 1, ..., 15. */
0169 } dsi_dphy_config_t;
0170
0171 /*! @brief _dsi_apb_status Status of APB to packet interface. */
0172 enum
0173 {
0174     kDSI_ApbNotIdle          = (1UL << 0U), /*!< State machine not idle */
0175     kDSI_ApbTxDone           = (1UL << 1U), /*!< Tx packet done */
0176     kDSI_ApbRxControl        = (1UL << 2U), /*!< DPHY direction 0 - tx had control, 1 - rx has control */
0177     kDSI_ApbTxOverflow       = (1UL << 3U), /*!< TX fifo overflow */
0178     kDSI_ApbTxUnderflow      = (1UL << 4U), /*!< TX fifo underflow */
0179     kDSI_ApbRxOverflow       = (1UL << 5U), /*!< RX fifo overflow */
0180     kDSI_ApbRxUnderflow      = (1UL << 6U), /*!< RX fifo underflow */
0181     kDSI_ApbRxHeaderReceived = (1UL << 7U), /*!< RX packet header has been received */
0182     kDSI_ApbRxPacketReceived = (1UL << 8U), /*!< All RX packet payload data has been received */
0183 };
0184
0185 /*! @brief _dsi_rx_error_status Host receive error status. */
0186 enum
0187 {
0188     kDSI_RxErrorEccOneBit   = (1UL << 0U), /*!< ECC single bit error detected. */
0189     kDSI_RxErrorEccMultiBit = (1UL << 1U), /*!< ECC multi bit error detected. */
0190     kDSI_RxErrorCrc         = (1UL << 7U), /*!< CRC error detected. */
0191     kDSI_RxErrorHtxTo       = (1UL << 8U), /*!< High Speed forward TX timeout detected. */
0192     kDSI_RxErrorLrxTo       = (1UL << 9U), /*!< Reverse Low power data receive timeout detected. */
0193     kDSI_RxErrorBtaTo       = (1UL << 10U) /*!< BTA timeout detected. */
0194 };
0195
0196 /*! @brief DSI host controller status (status_out) */
0197 enum _dsi_host_status
0198 {
0199     kDSI_HostSoTError           = (1UL << 0U), /*!< SoT error from peripheral error report. */
0200     kDSI_HostSoTSyncError       = (1UL << 1U), /*!< SoT Sync error from peripheral error report. */
0201     kDSI_HostEoTSyncError       = (1UL << 2U), /*!< EoT Sync error from peripheral error report. */
0202     kDSI_HostEscEntryCmdError   = (1UL << 3U), /*!< Escape Mode Entry Command Error from peripheral error report. */
0203     kDSI_HostLpTxSyncError      = (1UL << 4U), /*!< Low-power transmit Sync Error from peripheral error report. */
0204     kDSI_HostPeriphToError      = (1UL << 5U), /*!< Peripheral timeout error from peripheral error report. */
0205     kDSI_HostFalseControlError  = (1UL << 6U), /*!< False control error from peripheral error report. */
0206     kDSI_HostContentionDetected = (1UL << 7U), /*!< Contention detected from peripheral error report. */
0207     kDSI_HostEccErrorOneBit     = (1UL << 8U), /*!< Single bit ECC error (corrected) from peripheral error report. */
0208     kDSI_HostEccErrorMultiBit   = (1UL << 9U), /*!< Multi bit ECC error (not corrected) from peripheral error report. */
0209     kDSI_HostChecksumError      = (1UL << 10U),   /*!< Checksum error from peripheral error report. */
0210     kDSI_HostInvalidDataType    = (1UL << 11U),   /*!< DSI data type not recognized. */
0211     kDSI_HostInvalidVcId        = (1UL << 12U),   /*!< DSI VC ID invalid. */
0212     kDSI_HostInvalidTxLength    = (1UL << 13U),   /*!< Invalid transmission length. */
0213     kDSI_HostProtocalViolation  = (1UL << 15U),   /*!< DSI protocal violation. */
0214     kDSI_HostResetTriggerReceived = (1UL << 16U), /*!< Reset trigger received. */
0215     kDSI_HostTearTriggerReceived  = (1UL << 17U), /*!< Tear effect trigger receive. */
0216     kDSI_HostAckTriggerReceived   = (1UL << 18U), /*!< Acknowledge trigger message received. */
0217 };
0218
0219 /*! @brief _dsi_interrupt DSI interrupt. */
0220 enum
0221 {
0222     kDSI_InterruptGroup1ApbNotIdle          = (1UL << 0U),   /*!< State machine not idle */
0223     kDSI_InterruptGroup1ApbTxDone           = (1UL << 1U),   /*!< Tx packet done */
0224     kDSI_InterruptGroup1ApbRxControl        = (1UL << 2U),   /*!< DPHY direction 0 - tx control, 1 - rx control */
0225     kDSI_InterruptGroup1ApbTxOverflow       = (1UL << 3U),   /*!< TX fifo overflow */
0226     kDSI_InterruptGroup1ApbTxUnderflow      = (1UL << 4U),   /*!< TX fifo underflow */
0227     kDSI_InterruptGroup1ApbRxOverflow       = (1UL << 5U),   /*!< RX fifo overflow */
0228     kDSI_InterruptGroup1ApbRxUnderflow      = (1UL << 6U),   /*!< RX fifo underflow */
0229     kDSI_InterruptGroup1ApbRxHeaderReceived = (1UL << 7U),   /*!< RX packet header has been received */
0230     kDSI_InterruptGroup1ApbRxPacketReceived = (1UL << 8U),   /*!< All RX packet payload data has been received */
0231     kDSI_InterruptGroup1SoTError            = (1UL << 9U),   /*!< SoT error from peripheral error report. */
0232     kDSI_InterruptGroup1SoTSyncError        = (1UL << 10U),  /*!< SoT Sync error from peripheral error report. */
0233     kDSI_InterruptGroup1EoTSyncError        = (1UL << 11U),  /*!< EoT Sync error from peripheral error report. */
0234     kDSI_InterruptGroup1EscEntryCmdError    = (1UL << 12U),  /*!< Escape Mode Entry Command Error
0235                                                                    from peripheral error report. */
0236     kDSI_InterruptGroup1LpTxSyncError = (1UL << 13U),        /*!< Low-power transmit Sync Error from
0237                                                                    peripheral error report. */
0238     kDSI_InterruptGroup1PeriphToError = (1UL << 14U),        /*!< Peripheral timeout error from
0239                                                                    peripheral error report. */
0240     kDSI_InterruptGroup1FalseControlError  = (1UL << 15U),   /*!< False control error from peripheral error report. */
0241     kDSI_InterruptGroup1ContentionDetected = (1UL << 16U),   /*!< Contention detected from peripheral error report. */
0242     kDSI_InterruptGroup1EccErrorOneBit     = (1UL << 17U),   /*!< Single bit ECC error (corrected) from
0243                                                                    peripheral error report. */
0244     kDSI_InterruptGroup1EccErrorMultiBit = (1UL << 18U),     /*!< Multi bit ECC error (not corrected) from
0245                                                                peripheral error report. */
0246     kDSI_InterruptGroup1ChecksumError        = (1UL << 19U), /*!< Checksum error from peripheral error report. */
0247     kDSI_InterruptGroup1InvalidDataType      = (1UL << 20U), /*!< DSI data type not recognized. */
0248     kDSI_InterruptGroup1InvalidVcId          = (1UL << 21U), /*!< DSI VC ID invalid. */
0249     kDSI_InterruptGroup1InvalidTxLength      = (1UL << 22U), /*!< Invalid transmission length. */
0250     kDSI_InterruptGroup1ProtocalViolation    = (1UL << 24U), /*!< DSI protocal violation. */
0251     kDSI_InterruptGroup1ResetTriggerReceived = (1UL << 25U), /*!< Reset trigger received. */
0252     kDSI_InterruptGroup1TearTriggerReceived  = (1UL << 26U), /*!< Tear effect trigger receive. */
0253     kDSI_InterruptGroup1AckTriggerReceived   = (1UL << 27U), /*!< Acknowledge trigger message received. */
0254     kDSI_InterruptGroup1HtxTo                = (1UL << 29U), /*!< High speed TX timeout. */
0255     kDSI_InterruptGroup1LrxTo                = (1UL << 30U), /*!< Low power RX timeout. */
0256     kDSI_InterruptGroup1BtaTo                = (1UL << 31U), /*!< Host BTA timeout. */
0257     kDSI_InterruptGroup2EccOneBit            = (1UL << 0U),  /*!< Sinle bit ECC error. */
0258     kDSI_InterruptGroup2EccMultiBit          = (1UL << 1U),  /*!< Multi bit ECC error. */
0259     kDSI_InterruptGroup2CrcError             = (1UL << 2U),  /*!< CRC error. */
0260 };
0261
0262 /*! @brief DSI TX data type. */
0263 typedef enum _dsi_tx_data_type
0264 {
0265     kDSI_TxDataVsyncStart          = 0x01U, /*!< V Sync start. */
0266     kDSI_TxDataVsyncEnd            = 0x11U, /*!< V Sync end. */
0267     kDSI_TxDataHsyncStart          = 0x21U, /*!< H Sync start. */
0268     kDSI_TxDataHsyncEnd            = 0x31U, /*!< H Sync end. */
0269     kDSI_TxDataEoTp                = 0x08U, /*!< End of transmission packet. */
0270     kDSI_TxDataCmOff               = 0x02U, /*!< Color mode off. */
0271     kDSI_TxDataCmOn                = 0x12U, /*!< Color mode on. */
0272     kDSI_TxDataShutDownPeriph      = 0x22U, /*!< Shut down peripheral. */
0273     kDSI_TxDataTurnOnPeriph        = 0x32U, /*!< Turn on peripheral. */
0274     kDSI_TxDataGenShortWrNoParam   = 0x03U, /*!< Generic Short WRITE, no parameters. */
0275     kDSI_TxDataGenShortWrOneParam  = 0x13U, /*!< Generic Short WRITE, one parameter. */
0276     kDSI_TxDataGenShortWrTwoParam  = 0x23U, /*!< Generic Short WRITE, two parameter. */
0277     kDSI_TxDataGenShortRdNoParam   = 0x04U, /*!< Generic Short READ, no parameters. */
0278     kDSI_TxDataGenShortRdOneParam  = 0x14U, /*!< Generic Short READ, one parameter. */
0279     kDSI_TxDataGenShortRdTwoParam  = 0x24U, /*!< Generic Short READ, two parameter. */
0280     kDSI_TxDataDcsShortWrNoParam   = 0x05U, /*!< DCS Short WRITE, no parameters. */
0281     kDSI_TxDataDcsShortWrOneParam  = 0x15U, /*!< DCS Short WRITE, one parameter. */
0282     kDSI_TxDataDcsShortRdNoParam   = 0x06U, /*!< DCS Short READ, no parameters. */
0283     kDSI_TxDataSetMaxReturnPktSize = 0x37U, /*!< Set the Maximum Return Packet Size. */
0284
0285     kDSI_TxDataNull                         = 0x09U, /*!< Null Packet, no data. */
0286     kDSI_TxDataBlanking                     = 0x19U, /*!< Blanking Packet, no data. */
0287     kDSI_TxDataGenLongWr                    = 0x29U, /*!< Generic long write. */
0288     kDSI_TxDataDcsLongWr                    = 0x39U, /*!< DCS Long Write/write_LUT Command Packet. */
0289     kDSI_TxDataLooselyPackedPixel20BitYCbCr = 0x0CU, /*!< Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2 Format. */
0290     kDSI_TxDataPackedPixel24BitYCbCr        = 0x1CU, /*!< Packed Pixel Stream, 24-bit YCbCr, 4:2:2 Format. */
0291     kDSI_TxDataPackedPixel16BitYCbCr        = 0x2CU, /*!< Packed Pixel Stream, 16-bit YCbCr, 4:2:2 Format. */
0292     kDSI_TxDataPackedPixel30BitRGB          = 0x0DU, /*!< Packed Pixel Stream, 30-bit RGB, 10-10-10 Format. */
0293     kDSI_TxDataPackedPixel36BitRGB          = 0x1DU, /*!< Packed Pixel Stream, 36-bit RGB, 12-12-12 Format. */
0294     kDSI_TxDataPackedPixel12BitYCrCb        = 0x3DU, /*!< Packed Pixel Stream, 12-bit YCbCr, 4:2:0 Format. */
0295     kDSI_TxDataPackedPixel16BitRGB          = 0x0EU, /*!< Packed Pixel Stream, 16-bit RGB, 5-6-5 Format. */
0296     kDSI_TxDataPackedPixel18BitRGB          = 0x1EU, /*!< Packed Pixel Stream, 18-bit RGB, 6-6-6 Format. */
0297     kDSI_TxDataLooselyPackedPixel18BitRGB   = 0x2EU, /*!< Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6 Format. */
0298     kDSI_TxDataPackedPixel24BitRGB          = 0x3EU, /*!< Packed Pixel Stream, 24-bit RGB, 8-8-8 Format. */
0299 } dsi_tx_data_type_t;
0300
0301 /*! @brief DSI RX data type. */
0302 typedef enum _dsi_rx_data_type
0303 {
0304     kDSI_RxDataAckAndErrorReport         = 0x02U, /*!< Acknowledge and Error Report */
0305     kDSI_RxDataEoTp                      = 0x08U, /*!< End of Transmission packet. */
0306     kDSI_RxDataGenShortRdResponseOneByte = 0x11U, /*!< Generic Short READ Response, 1 byte returned. */
0307     kDSI_RxDataGenShortRdResponseTwoByte = 0x12U, /*!< Generic Short READ Response, 2 byte returned. */
0308     kDSI_RxDataGenLongRdResponse         = 0x1AU, /*!< Generic Long READ Response. */
0309     kDSI_RxDataDcsLongRdResponse         = 0x1CU, /*!< DCS Long READ Response. */
0310     kDSI_RxDataDcsShortRdResponseOneByte = 0x21U, /*!< DCS Short READ Response, 1 byte returned. */
0311     kDSI_RxDataDcsShortRdResponseTwoByte = 0x22U, /*!< DCS Short READ Response, 2 byte returned. */
0312 } dsi_rx_data_type_t;
0313
0314 /*! @brief _dsi_transfer_flags DSI transfer control flags. */
0315 enum
0316 {
0317     kDSI_TransferUseHighSpeed = (1U << 0U), /*!< Use high speed mode or not. */
0318     kDSI_TransferPerformBTA   = (1U << 1U), /*!< Perform BTA or not. */
0319 };
0320
0321 /*! @brief Structure for the data transfer. */
0322 typedef struct _dsi_transfer
0323 {
0324     uint8_t virtualChannel;        /*!< Virtual channel. */
0325     dsi_tx_data_type_t txDataType; /*!< TX data type. */
0326     uint8_t flags;                 /*!< Flags to control the transfer, see _dsi_transfer_flags. */
0327     const uint8_t *txData;         /*!< The TX data buffer. */
0328     uint8_t *rxData;               /*!< The TX data buffer. */
0329     uint16_t txDataSize;           /*!< Size of the TX data. */
0330     uint16_t rxDataSize;           /*!< Size of the RX data. */
0331     bool sendDscCmd;               /*!< If set to true, the DSC command is specified by @ref dscCmd, otherwise
0332                                         the DSC command is included in the @ref txData. */
0333     uint8_t dscCmd;                /*!< The DSC command to send, only valid when @ref sendDscCmd is true. */
0334 } dsi_transfer_t;
0335
0336 /*! @brief MIPI DSI transfer handle. */
0337 typedef struct _dsi_handle dsi_handle_t;
0338
0339 /*!
0340  * @brief MIPI DSI callback for finished transfer.
0341  *
0342  * When transfer finished, one of these status values will be passed to the user:
0343  * - @ref kStatus_Success Data transfer finished with no error.
0344  * - @ref kStatus_Timeout Transfer failed because of timeout.
0345  * - @ref kStatus_DSI_RxDataError RX data error, user could use @ref DSI_GetRxErrorStatus
0346  *        to check the error details.
0347  * - @ref kStatus_DSI_ErrorReportReceived Error Report packet received, user could use
0348  *        @ref DSI_GetAndClearHostStatus to check the error report status.
0349  * - @ref kStatus_Fail Transfer failed for other reasons.
0350  */
0351 typedef void (*dsi_callback_t)(const MIPI_DSI_Type *base, dsi_handle_t *handle, status_t status, void *userData);
0352
0353 /*! @brief MIPI DSI transfer handle structure */
0354 struct _dsi_handle
0355 {
0356     volatile bool isBusy;     /*!< MIPI DSI is busy with APB data transfer. */
0357     dsi_transfer_t xfer;      /*!< Transfer information. */
0358     dsi_callback_t callback;  /*!< DSI callback */
0359     void *userData;           /*!< Callback parameter */
0360     const MIPI_DSI_Type *dsi; /*!< Pointer to MIPI DSI peripheral. */
0361 };
0362
0363 /*******************************************************************************
0364  * API
0365  ******************************************************************************/
0366
0367 #if defined(__cplusplus)
0368 extern "C" {
0369 #endif
0370
0371 /*!
0372  * @name MIPI_DSI host initialization.
0373  * @{
0374  */
0375
0376 /*!
0377  * @brief Initializes an MIPI DSI host with the user configuration.
0378  *
0379  * This function initializes the MIPI DSI host with the configuration, it should
0380  * be called first before other MIPI DSI driver functions.
0381  *
0382  * @param base MIPI DSI host peripheral base address.
0383  * @param config Pointer to a user-defined configuration structure.
0384  */
0385 void DSI_Init(const MIPI_DSI_Type *base, const dsi_config_t *config);
0386
0387 /*!
0388  * @brief Deinitializes an MIPI DSI host.
0389  *
0390  * This function should be called after all bother MIPI DSI driver functions.
0391  *
0392  * @param base MIPI DSI host peripheral base address.
0393  */
0394 void DSI_Deinit(const MIPI_DSI_Type *base);
0395
0396 /*!
0397  * @brief Get the default configuration to initialize the MIPI DSI host.
0398  *
0399  * The default value is:
0400  * @code
0401     config->numLanes = 4;
0402     config->enableNonContinuousHsClk = false;
0403     config->enableTxUlps = false;
0404     config->autoInsertEoTp = true;
0405     config->numExtraEoTp = 0;
0406     config->htxTo_ByteClk = 0;
0407     config->lrxHostTo_ByteClk = 0;
0408     config->btaTo_ByteClk = 0;
0409    @endcode
0410  *
0411  * @param config Pointer to a user-defined configuration structure.
0412  */
0413 void DSI_GetDefaultConfig(dsi_config_t *config);
0414
0415 /*! @} */
0416
0417 /*!
0418  * @name DPI interface
0419  * @{
0420  */
0421
0422 /*!
0423  * @brief Configure the DPI interface core.
0424  *
0425  * This function sets the DPI interface configuration, it should be used in
0426  * video mode.
0427  *
0428  * @param base MIPI DSI host peripheral base address.
0429  * @param config Pointer to the DPI interface configuration.
0430  * @param numLanes Lane number, should be same with the setting in @ref dsi_dpi_config_t.
0431  * @param dpiPixelClkFreq_Hz The DPI pixel clock frequency in Hz.
0432  * @param dsiHsBitClkFreq_Hz The DSI high speed bit clock frequency in Hz. It is
0433  * the same with DPHY PLL output.
0434  */
0435 void DSI_SetDpiConfig(const MIPI_DSI_Type *base,
0436                       const dsi_dpi_config_t *config,
0437                       uint8_t numLanes,
0438                       uint32_t dpiPixelClkFreq_Hz,
0439                       uint32_t dsiHsBitClkFreq_Hz);
0440
0441 /*! @} */
0442
0443 /*!
0444  * @name D-PHY configuration.
0445  * @{
0446  */
0447
0448 /*!
0449  * @brief Initializes the D-PHY
0450  *
0451  * This function configures the D-PHY timing and setups the D-PHY PLL based on
0452  * user configuration. The configuration structure could be got by the function
0453  * @ref DSI_GetDphyDefaultConfig.
0454  *
0455  * For some platforms there is not dedicated D-PHY PLL, indicated by the macro
0456  * FSL_FEATURE_MIPI_DSI_NO_DPHY_PLL. For these platforms, the @p refClkFreq_Hz
0457  * is useless.
0458  *
0459  * @param base MIPI DSI host peripheral base address.
0460  * @param config Pointer to the D-PHY configuration.
0461  * @param refClkFreq_Hz The REFCLK frequency in Hz.
0462  * @return The actual D-PHY PLL output frequency. If could not configure the
0463  * PLL to the target frequency, the return value is 0.
0464  */
0465 uint32_t DSI_InitDphy(const MIPI_DSI_Type *base, const dsi_dphy_config_t *config, uint32_t refClkFreq_Hz);
0466
0467 /*!
0468  * @brief Deinitializes the D-PHY
0469  *
0470  * Power down the D-PHY PLL and shut down D-PHY.
0471  *
0472  * @param base MIPI DSI host peripheral base address.
0473  */
0474 void DSI_DeinitDphy(const MIPI_DSI_Type *base);
0475
0476 /*!
0477  * @brief Get the default D-PHY configuration.
0478  *
0479  * Gets the default D-PHY configuration, the timing parameters are set according
0480  * to D-PHY specification. User could use the configuration directly, or change
0481  * some parameters according to the special device.
0482  *
0483  * @param config Pointer to the D-PHY configuration.
0484  * @param txHsBitClk_Hz High speed bit clock in Hz.
0485  * @param txEscClk_Hz Esc clock in Hz.
0486  */
0487 void DSI_GetDphyDefaultConfig(dsi_dphy_config_t *config, uint32_t txHsBitClk_Hz, uint32_t txEscClk_Hz);
0488
0489 /*! @} */
0490
0491 /*!
0492  * @name Interrupts
0493  * @{
0494  */
0495
0496 /*!
0497  * @brief Enable the interrupts.
0498  *
0499  * The interrupts to enable are passed in as OR'ed mask value of _dsi_interrupt.
0500  *
0501  * @param base MIPI DSI host peripheral base address.
0502  * @param intGroup1 Interrupts to enable in group 1.
0503  * @param intGroup2 Interrupts to enable in group 2.
0504  */
0505 static inline void DSI_EnableInterrupts(const MIPI_DSI_Type *base, uint32_t intGroup1, uint32_t intGroup2)
0506 {
0507     base->apb->IRQ_MASK &= ~intGroup1;
0508     base->apb->IRQ_MASK2 &= ~intGroup2;
0509 }
0510
0511 /*!
0512  * @brief Disable the interrupts.
0513  *
0514  * The interrupts to disable are passed in as OR'ed mask value of _dsi_interrupt.
0515  *
0516  * @param base MIPI DSI host peripheral base address.
0517  * @param intGroup1 Interrupts to disable in group 1.
0518  * @param intGroup2 Interrupts to disable in group 2.
0519  */
0520 static inline void DSI_DisableInterrupts(const MIPI_DSI_Type *base, uint32_t intGroup1, uint32_t intGroup2)
0521 {
0522     base->apb->IRQ_MASK |= intGroup1;
0523     base->apb->IRQ_MASK2 |= intGroup2;
0524 }
0525
0526 /*!
0527  * @brief Get and clear the interrupt status.
0528  *
0529  * @param base MIPI DSI host peripheral base address.
0530  * @param intGroup1 Group 1 interrupt status.
0531  * @param intGroup2 Group 2 interrupt status.
0532  */
0533 static inline void DSI_GetAndClearInterruptStatus(const MIPI_DSI_Type *base, uint32_t *intGroup1, uint32_t *intGroup2)
0534 {
0535     *intGroup2 = base->apb->IRQ_STATUS2;
0536     *intGroup1 = base->apb->IRQ_STATUS;
0537 }
0538
0539 /*! @} */
0540
0541 /*!
0542  * @name MIPI DSI APB
0543  * @{
0544  */
0545
0546 /*!
0547  * @brief Configure the APB packet to send.
0548  *
0549  * This function configures the next APB packet transfer. After configuration,
0550  * the packet transfer could be started with function @ref DSI_SendApbPacket.
0551  * If the packet is long packet, Use @ref DSI_WriteApbTxPayload to fill the payload
0552  * before start transfer.
0553  *
0554  * @param base MIPI DSI host peripheral base address.
0555  * @param wordCount For long packet, this is the byte count of the payload.
0556  * For short packet, this is (data1 << 8) | data0.
0557  * @param virtualChannel Virtual channel.
0558  * @param dataType The packet data type, (DI).
0559  * @param flags The transfer control flags, see _dsi_transfer_flags.
0560  */
0561 void DSI_SetApbPacketControl(
0562     const MIPI_DSI_Type *base, uint16_t wordCount, uint8_t virtualChannel, dsi_tx_data_type_t dataType, uint8_t flags);
0563
0564 /*!
0565  * @brief Fill the long APB packet payload.
0566  *
0567  * Write the long packet payload to TX FIFO.
0568  *
0569  * @param base MIPI DSI host peripheral base address.
0570  * @param payload Pointer to the payload.
0571  * @param payloadSize Payload size in byte.
0572  */
0573 void DSI_WriteApbTxPayload(const MIPI_DSI_Type *base, const uint8_t *payload, uint16_t payloadSize);
0574
0575 /*!
0576  * @brief Extended function to fill the payload to TX FIFO.
0577  *
0578  * Write the long packet payload to TX FIFO. This function could be used in two ways
0579  *
0580  * 1. Include the DSC command in parameter @p payload. In this case, the DSC command
0581  *    is the first byte of @p payload. The parameter @p sendDscCmd is set to false,
0582  *    the @p dscCmd is not used. This function is the same as @ref DSI_WriteApbTxPayload
0583  *    when used in this way.
0584  *
0585  * 2. The DSC command in not in parameter @p payload, but specified by parameter @p dscCmd.
0586  *    In this case, the parameter @p sendDscCmd is set to true, the @p dscCmd is the DSC
0587  *    command to send. The @p payload is sent after @p dscCmd.
0588  *
0589  * @param base MIPI DSI host peripheral base address.
0590  * @param payload Pointer to the payload.
0591  * @param payloadSize Payload size in byte.
0592  * @param sendDscCmd If set to true, the DSC command is specified by @p dscCmd,
0593  *        otherwise the DSC command is included in the @p payload.
0594  * @param dscCmd The DSC command to send, only used when @p sendDscCmd is true.
0595  */
0596 void DSI_WriteApbTxPayloadExt(
0597     const MIPI_DSI_Type *base, const uint8_t *payload, uint16_t payloadSize, bool sendDscCmd, uint8_t dscCmd);
0598
0599 /*!
0600  * @brief Read the long APB packet payload.
0601  *
0602  * Read the long packet payload from RX FIFO. This function reads directly but
0603  * does not check the RX FIFO status. Upper layer should make sure there are
0604  * available data.
0605  *
0606  * @param base MIPI DSI host peripheral base address.
0607  * @param payload Pointer to the payload.
0608  * @param payloadSize Payload size in byte.
0609  */
0610 void DSI_ReadApbRxPayload(const MIPI_DSI_Type *base, uint8_t *payload, uint16_t payloadSize);
0611
0612 /*!
0613  * @brief Trigger the controller to send out APB packet.
0614  *
0615  * Send the packet set by @ref DSI_SetApbPacketControl.
0616  *
0617  * @param base MIPI DSI host peripheral base address.
0618  */
0619 static inline void DSI_SendApbPacket(const MIPI_DSI_Type *base)
0620 {
0621     base->apb->SEND_PACKET = 0x1U;
0622 }
0623
0624 /*!
0625  * @brief Get the APB status.
0626  *
0627  * The return value is OR'ed value of _dsi_apb_status.
0628  *
0629  * @param base MIPI DSI host peripheral base address.
0630  * @return The APB status.
0631  */
0632 static inline uint32_t DSI_GetApbStatus(const MIPI_DSI_Type *base)
0633 {
0634     return base->apb->PKT_STATUS;
0635 }
0636
0637 /*!
0638  * @brief Get the error status during data transfer.
0639  *
0640  * The return value is OR'ed value of _dsi_rx_error_status.
0641  *
0642  * @param base MIPI DSI host peripheral base address.
0643  * @return The error status.
0644  */
0645 static inline uint32_t DSI_GetRxErrorStatus(const MIPI_DSI_Type *base)
0646 {
0647     return base->host->RX_ERROR_STATUS;
0648 }
0649
0650 /*!
0651  * @brief Get the one-bit RX ECC error position.
0652  *
0653  * When one-bit ECC RX error detected using @ref DSI_GetRxErrorStatus, this
0654  * function could be used to get the error bit position.
0655  *
0656  * @code
0657    uint8_t eccErrorPos;
0658    uint32_t rxErrorStatus = DSI_GetRxErrorStatus(MIPI_DSI);
0659    if (kDSI_RxErrorEccOneBit & rxErrorStatus)
0660    {
0661        eccErrorPos = DSI_GetEccRxErrorPosition(rxErrorStatus);
0662    }
0663    @endcode
0664  *
0665  * @param rxErrorStatus The error status returned by @ref DSI_GetRxErrorStatus.
0666  * @return The 1-bit ECC error position.
0667  */
0668 static inline uint8_t DSI_GetEccRxErrorPosition(uint32_t rxErrorStatus)
0669 {
0670     return (uint8_t)((rxErrorStatus >> 2U) & 0x1FU);
0671 }
0672
0673 /*!
0674  * @brief Get and clear the DSI host status.
0675  *
0676  * The host status are returned as mask value of @ref _dsi_host_status.
0677  *
0678  * @param base MIPI DSI host peripheral base address.
0679  * @return The DSI host status.
0680  */
0681 static inline uint32_t DSI_GetAndClearHostStatus(const MIPI_DSI_Type *base)
0682 {
0683     return base->host->CFG_STATUS_OUT;
0684 }
0685
0686 /*!
0687  * @brief Get the RX packet header.
0688  *
0689  * @param base MIPI DSI host peripheral base address.
0690  * @return The RX packet header.
0691  */
0692 static inline uint32_t DSI_GetRxPacketHeader(const MIPI_DSI_Type *base)
0693 {
0694     return base->apb->PKT_RX_PKT_HEADER;
0695 }
0696
0697 /*!
0698  * @brief Extract the RX packet type from the packet header.
0699  *
0700  * Extract the RX packet type from the packet header get by @ref DSI_GetRxPacketHeader.
0701  *
0702  * @param rxPktHeader The RX packet header get by @ref DSI_GetRxPacketHeader.
0703  * @return The RX packet type.
0704  */
0705 static inline dsi_rx_data_type_t DSI_GetRxPacketType(uint32_t rxPktHeader)
0706 {
0707     return (dsi_rx_data_type_t)(uint8_t)((rxPktHeader >> 16U) & 0x3FU);
0708 }
0709
0710 /*!
0711  * @brief Extract the RX packet word count from the packet header.
0712  *
0713  * Extract the RX packet word count from the packet header get by @ref DSI_GetRxPacketHeader.
0714  *
0715  * @param rxPktHeader The RX packet header get by @ref DSI_GetRxPacketHeader.
0716  * @return For long packet, return the payload word count (byte). For short packet,
0717  * return the (data0 << 8) | data1.
0718  */
0719 static inline uint16_t DSI_GetRxPacketWordCount(uint32_t rxPktHeader)
0720 {
0721     return (uint16_t)(rxPktHeader & 0xFFFFU);
0722 }
0723
0724 /*!
0725  * @brief Extract the RX packet virtual channel from the packet header.
0726  *
0727  * Extract the RX packet virtual channel from the packet header get by @ref DSI_GetRxPacketHeader.
0728  *
0729  * @param rxPktHeader The RX packet header get by @ref DSI_GetRxPacketHeader.
0730  * @return The virtual channel.
0731  */
0732 static inline uint8_t DSI_GetRxPacketVirtualChannel(uint32_t rxPktHeader)
0733 {
0734     return (uint8_t)((rxPktHeader >> 22U) & 0x3U);
0735 }
0736
0737 /*!
0738  * @brief APB data transfer using blocking method.
0739  *
0740  * Perform APB data transfer using blocking method. This function waits until all
0741  * data send or received, or timeout happens.
0742  *
0743  * When using this API to read data, the actually read data count could be got
0744  * from xfer->rxDataSize.
0745  *
0746  * @param base MIPI DSI host peripheral base address.
0747  * @param xfer Pointer to the transfer structure.
0748  * @retval kStatus_Success Data transfer finished with no error.
0749  * @retval kStatus_Timeout Transfer failed because of timeout.
0750  * @retval kStatus_DSI_RxDataError RX data error, user could use @ref DSI_GetRxErrorStatus
0751  * to check the error details.
0752  * @retval kStatus_DSI_ErrorReportReceived Error Report packet received, user could use
0753  *        @ref DSI_GetAndClearHostStatus to check the error report status.
0754  * @retval kStatus_DSI_NotSupported Transfer format not supported.
0755  * @retval kStatus_DSI_Fail Transfer failed for other reasons.
0756  */
0757 status_t DSI_TransferBlocking(const MIPI_DSI_Type *base, dsi_transfer_t *xfer);
0758
0759 /*! @} */
0760
0761 /*!
0762  * @name Transactional
0763  * @{
0764  */
0765
0766 /*!
0767  * @brief Create the MIPI DSI handle.
0768  *
0769  * This function initializes the MIPI DSI handle which can be used for other transactional APIs.
0770  *
0771  * @param base MIPI DSI host peripheral base address.
0772  * @param handle Handle pointer.
0773  * @param callback Callback function.
0774  * @param userData User data.
0775  */
0776 status_t DSI_TransferCreateHandle(const MIPI_DSI_Type *base,
0777                                   dsi_handle_t *handle,
0778                                   dsi_callback_t callback,
0779                                   void *userData);
0780
0781 /*!
0782  * @brief APB data transfer using interrupt method.
0783  *
0784  * Perform APB data transfer using interrupt method, when transfer finished,
0785  * upper layer could be informed through callback function.
0786  *
0787  * When using this API to read data, the actually read data count could be got
0788  * from handle->xfer->rxDataSize after read finished.
0789  *
0790  * @param base MIPI DSI host peripheral base address.
0791  * @param handle pointer to dsi_handle_t structure which stores the transfer state.
0792  * @param xfer Pointer to the transfer structure.
0793  *
0794  * @retval kStatus_Success Data transfer started successfully.
0795  * @retval kStatus_DSI_Busy Failed to start transfer because DSI is busy with pervious transfer.
0796  * @retval kStatus_DSI_NotSupported Transfer format not supported.
0797  */
0798 status_t DSI_TransferNonBlocking(const MIPI_DSI_Type *base, dsi_handle_t *handle, dsi_transfer_t *xfer);
0799
0800 /*!
0801  * @brief Abort current APB data transfer.
0802  *
0803  * @param base MIPI DSI host peripheral base address.
0804  * @param handle pointer to dsi_handle_t structure which stores the transfer state.
0805  */
0806 void DSI_TransferAbort(const MIPI_DSI_Type *base, dsi_handle_t *handle);
0807
0808 /*!
0809  * @brief Interrupt handler for the DSI.
0810  *
0811  * @param base MIPI DSI host peripheral base address.
0812  * @param handle pointer to dsi_handle_t structure which stores the transfer state.
0813  */
0814 void DSI_TransferHandleIRQ(const MIPI_DSI_Type *base, dsi_handle_t *handle);
0815
0816 /*! @} */
0817
0818 #if defined(__cplusplus)
0819 }
0820 #endif
0821
0822 /*! @} */
0823
0824 #endif /* _FSL_MIPI_DSI_H_ */