drivers/mipi_csi2rx/fsl_mipi_csi2rx.h

0001 /*
0002  * Copyright 2017, 2019-2020 NXP
0003  * All rights reserved.
0004  *
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #ifndef _FSL_MIPI_CSI2RX_H_
0010 #define _FSL_MIPI_CSI2RX_H_
0011
0012 #include "fsl_common.h"
0013
0014 /*!
0015  * @addtogroup csi2rx
0016  * @{
0017  */
0018
0019 /*******************************************************************************
0020  * Definitions
0021  ******************************************************************************/
0022
0023 /*! @name Driver version */
0024 /*@{*/
0025 /*! @brief CSI2RX driver version. */
0026 #define FSL_CSI2RX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
0027 /*@}*/
0028
0029 #if (defined(FSL_FEATURE_CSI2RX_HAS_NO_REG_PREFIX) && FSL_FEATURE_CSI2RX_HAS_NO_REG_PREFIX)
0030
0031 #define CSI2RX_REG_CFG_NUM_LANES(base)             (base)->CFG_NUM_LANES
0032 #define CSI2RX_REG_CFG_DISABLE_DATA_LANES(base)    (base)->CFG_DISABLE_DATA_LANES
0033 #define CSI2RX_REG_BIT_ERR(base)                   (base)->BIT_ERR
0034 #define CSI2RX_REG_IRQ_STATUS(base)                (base)->IRQ_STATUS
0035 #define CSI2RX_REG_IRQ_MASK(base)                  (base)->IRQ_MASK
0036 #define CSI2RX_REG_ULPS_STATUS(base)               (base)->ULPS_STATUS
0037 #define CSI2RX_REG_PPI_ERRSOT_HS(base)             (base)->PPI_ERRSOT_HS
0038 #define CSI2RX_REG_PPI_ERRSOTSYNC_HS(base)         (base)->PPI_ERRSOTSYNC_HS
0039 #define CSI2RX_REG_PPI_ERRESC(base)                (base)->PPI_ERRESC
0040 #define CSI2RX_REG_PPI_ERRSYNCESC(base)            (base)->PPI_ERRSYNCESC
0041 #define CSI2RX_REG_PPI_ERRCONTROL(base)            (base)->PPI_ERRCONTROL
0042 #define CSI2RX_REG_CFG_DISABLE_PAYLOAD_0(base)     (base)->CFG_DISABLE_PAYLOAD_0
0043 #define CSI2RX_REG_CFG_DISABLE_PAYLOAD_1(base)     (base)->CFG_DISABLE_PAYLOAD_1
0044 #define CSI2RX_REG_CFG_IGNORE_VC(base)             (base)->CFG_IGNORE_VC
0045 #define CSI2RX_REG_CFG_VID_VC(base)                (base)->CFG_VID_VC
0046 #define CSI2RX_REG_CFG_VID_P_FIFO_SEND_LEVEL(base) (base)->CFG_VID_P_FIFO_SEND_LEVEL
0047 #define CSI2RX_REG_CFG_VID_VSYNC(base)             (base)->CFG_VID_VSYNC
0048 #define CSI2RX_REG_CFG_VID_HSYNC_FP(base)          (base)->CFG_VID_HSYNC_FP
0049 #define CSI2RX_REG_CFG_VID_HSYNC(base)             (base)->CFG_VID_HSYNC
0050 #define CSI2RX_REG_CFG_VID_HSYNC_BP(base)          (base)->CFG_VID_HSYNC_BP
0051
0052 #else
0053
0054 #define CSI2RX_REG_CFG_NUM_LANES(base)             (base)->CSI2RX_CFG_NUM_LANES
0055 #define CSI2RX_REG_CFG_DISABLE_DATA_LANES(base)    (base)->CSI2RX_CFG_DISABLE_DATA_LANES
0056 #define CSI2RX_REG_BIT_ERR(base)                   (base)->CSI2RX_BIT_ERR
0057 #define CSI2RX_REG_IRQ_STATUS(base)                (base)->CSI2RX_IRQ_STATUS
0058 #define CSI2RX_REG_IRQ_MASK(base)                  (base)->CSI2RX_IRQ_MASK
0059 #define CSI2RX_REG_ULPS_STATUS(base)               (base)->CSI2RX_ULPS_STATUS
0060 #define CSI2RX_REG_PPI_ERRSOT_HS(base)             (base)->CSI2RX_PPI_ERRSOT_HS
0061 #define CSI2RX_REG_PPI_ERRSOTSYNC_HS(base)         (base)->CSI2RX_PPI_ERRSOTSYNC_HS
0062 #define CSI2RX_REG_PPI_ERRESC(base)                (base)->CSI2RX_PPI_ERRESC
0063 #define CSI2RX_REG_PPI_ERRSYNCESC(base)            (base)->CSI2RX_PPI_ERRSYNCESC
0064 #define CSI2RX_REG_PPI_ERRCONTROL(base)            (base)->CSI2RX_PPI_ERRCONTROL
0065 #define CSI2RX_REG_CFG_DISABLE_PAYLOAD_0(base)     (base)->CSI2RX_CFG_DISABLE_PAYLOAD_0
0066 #define CSI2RX_REG_CFG_DISABLE_PAYLOAD_1(base)     (base)->CSI2RX_CFG_DISABLE_PAYLOAD_1
0067 #define CSI2RX_REG_CFG_IGNORE_VC(base)             (base)->CSI2RX_CFG_IGNORE_VC
0068 #define CSI2RX_REG_CFG_VID_VC(base)                (base)->CSI2RX_CFG_VID_VC
0069 #define CSI2RX_REG_CFG_VID_P_FIFO_SEND_LEVEL(base) (base)->CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL
0070 #define CSI2RX_REG_CFG_VID_VSYNC(base)             (base)->CSI2RX_CFG_VID_VSYNC
0071 #define CSI2RX_REG_CFG_VID_HSYNC_FP(base)          (base)->CSI2RX_CFG_VID_HSYNC_FP
0072 #define CSI2RX_REG_CFG_VID_HSYNC(base)             (base)->CSI2RX_CFG_VID_HSYNC
0073 #define CSI2RX_REG_CFG_VID_HSYNC_BP(base)          (base)->CSI2RX_CFG_VID_HSYNC_BP
0074
0075 #endif
0076
0077 #ifndef MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK
0078 #define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK
0079 #endif
0080
0081 #ifndef MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK
0082 #define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK
0083 #endif
0084
0085 /*! @brief CSI2RX data lanes.  */
0086 enum _csi2rx_data_lane
0087 {
0088     kCSI2RX_DataLane0 = (1U << 0U), /*!< Data lane 0. */
0089     kCSI2RX_DataLane1 = (1U << 1U), /*!< Data lane 1. */
0090     kCSI2RX_DataLane2 = (1U << 2U), /*!< Data lane 2. */
0091     kCSI2RX_DataLane3 = (1U << 3U)  /*!< Data lane 3. */
0092 };
0093
0094 /*! @brief CSI2RX payload type.  */
0095 enum _csi2rx_payload
0096 {
0097     kCSI2RX_PayloadGroup0Null         = (1U << 0U),  /*!< NULL. */
0098     kCSI2RX_PayloadGroup0Blank        = (1U << 1U),  /*!< Blank. */
0099     kCSI2RX_PayloadGroup0Embedded     = (1U << 2U),  /*!< Embedded. */
0100     kCSI2RX_PayloadGroup0YUV420_8Bit  = (1U << 10U), /*!< Legacy YUV420 8 bit. */
0101     kCSI2RX_PayloadGroup0YUV422_8Bit  = (1U << 14U), /*!< YUV422 8 bit. */
0102     kCSI2RX_PayloadGroup0YUV422_10Bit = (1U << 15U), /*!< YUV422 10 bit. */
0103     kCSI2RX_PayloadGroup0RGB444       = (1U << 16U), /*!< RGB444. */
0104     kCSI2RX_PayloadGroup0RGB555       = (1U << 17U), /*!< RGB555. */
0105     kCSI2RX_PayloadGroup0RGB565       = (1U << 18U), /*!< RGB565. */
0106     kCSI2RX_PayloadGroup0RGB666       = (1U << 19U), /*!< RGB666. */
0107     kCSI2RX_PayloadGroup0RGB888       = (1U << 20U), /*!< RGB888. */
0108     kCSI2RX_PayloadGroup0Raw6         = (1U << 24U), /*!< Raw 6. */
0109     kCSI2RX_PayloadGroup0Raw7         = (1U << 25U), /*!< Raw 7. */
0110     kCSI2RX_PayloadGroup0Raw8         = (1U << 26U), /*!< Raw 8. */
0111     kCSI2RX_PayloadGroup0Raw10        = (1U << 27U), /*!< Raw 10. */
0112     kCSI2RX_PayloadGroup0Raw12        = (1U << 28U), /*!< Raw 12. */
0113     kCSI2RX_PayloadGroup0Raw14        = (1U << 29U), /*!< Raw 14. */
0114     kCSI2RX_PayloadGroup1UserDefined1 = (1U << 0U),  /*!< User defined 8-bit data type 1, 0x30. */
0115     kCSI2RX_PayloadGroup1UserDefined2 = (1U << 1U),  /*!< User defined 8-bit data type 2, 0x31. */
0116     kCSI2RX_PayloadGroup1UserDefined3 = (1U << 2U),  /*!< User defined 8-bit data type 3, 0x32. */
0117     kCSI2RX_PayloadGroup1UserDefined4 = (1U << 3U),  /*!< User defined 8-bit data type 4, 0x33. */
0118     kCSI2RX_PayloadGroup1UserDefined5 = (1U << 4U),  /*!< User defined 8-bit data type 5, 0x34. */
0119     kCSI2RX_PayloadGroup1UserDefined6 = (1U << 5U),  /*!< User defined 8-bit data type 6, 0x35. */
0120     kCSI2RX_PayloadGroup1UserDefined7 = (1U << 6U),  /*!< User defined 8-bit data type 7, 0x36. */
0121     kCSI2RX_PayloadGroup1UserDefined8 = (1U << 7U)   /*!< User defined 8-bit data type 8, 0x37. */
0122 };
0123
0124 /*! @brief CSI2RX configuration.  */
0125 typedef struct _csi2rx_config
0126 {
0127     uint8_t laneNum;          /*!< Number of active lanes used for receiving data. */
0128     uint8_t tHsSettle_EscClk; /*!< Number of rx_clk_esc clock periods for T_HS_SETTLE.
0129                                    The T_HS_SETTLE should be in the range of
0130                                    85ns + 6UI to 145ns + 10UI. */
0131 } csi2rx_config_t;
0132
0133 /*! @brief MIPI CSI2RX bit errors. */
0134 enum _csi2rx_bit_error
0135 {
0136     kCSI2RX_BitErrorEccTwoBit = (1U << 0U), /*!< ECC two bit error has occurred. */
0137     kCSI2RX_BitErrorEccOneBit = (1U << 1U)  /*!< ECC one bit error has occurred. */
0138 };
0139
0140 /*! @brief MIPI CSI2RX PPI error types. */
0141 typedef enum _csi2rx_ppi_error
0142 {
0143     kCSI2RX_PpiErrorSotHs,     /*!< CSI2RX DPHY PPI error ErrSotHS. */
0144     kCSI2RX_PpiErrorSotSyncHs, /*!< CSI2RX DPHY PPI error ErrSotSync_HS. */
0145     kCSI2RX_PpiErrorEsc,       /*!< CSI2RX DPHY PPI error ErrEsc. */
0146     kCSI2RX_PpiErrorSyncEsc,   /*!< CSI2RX DPHY PPI error ErrSyncEsc. */
0147     kCSI2RX_PpiErrorControl,   /*!< CSI2RX DPHY PPI error ErrControl. */
0148 } csi2rx_ppi_error_t;
0149
0150 /*! @brief MIPI CSI2RX interrupt. */
0151 enum _csi2rx_interrupt
0152 {
0153     kCSI2RX_InterruptCrcError         = (1U << 0U), /* CRC error. */
0154     kCSI2RX_InterruptEccOneBitError   = (1U << 1U), /* One bit ECC error. */
0155     kCSI2RX_InterruptEccTwoBitError   = (1U << 2U), /* One bit ECC error. */
0156     kCSI2RX_InterruptUlpsStatusChange = (1U << 3U), /* ULPS status changed. */
0157     kCSI2RX_InterruptErrorSotHs       = (1U << 4U), /* D-PHY ErrSotHS occurred. */
0158     kCSI2RX_InterruptErrorSotSyncHs   = (1U << 5U), /* D-PHY ErrSotSync_HS occurred. */
0159     kCSI2RX_InterruptErrorEsc         = (1U << 6U), /* D-PHY ErrEsc occurred. */
0160     kCSI2RX_InterruptErrorSyncEsc     = (1U << 7U), /* D-PHY ErrSyncEsc occurred. */
0161     kCSI2RX_InterruptErrorControl     = (1U << 8U), /* D-PHY ErrControl occurred. */
0162 };
0163
0164 /*! @brief MIPI CSI2RX D-PHY ULPS state. */
0165 enum _csi2rx_ulps_status
0166 {
0167     kCSI2RX_ClockLaneUlps = (1U << 0U), /*!< Clock lane is in ULPS state. */
0168     kCSI2RX_DataLane0Ulps = (1U << 1U), /*!< Data lane 0 is in ULPS state. */
0169     kCSI2RX_DataLane1Ulps = (1U << 2U), /*!< Data lane 1 is in ULPS state. */
0170     kCSI2RX_DataLane2Ulps = (1U << 3U), /*!< Data lane 2 is in ULPS state. */
0171     kCSI2RX_DataLane3Ulps = (1U << 4U), /*!< Data lane 3 is in ULPS state. */
0172     kCSI2RX_ClockLaneMark = (1U << 5U), /*!< Clock lane is in mark state. */
0173     kCSI2RX_DataLane0Mark = (1U << 6U), /*!< Data lane 0 is in mark state. */
0174     kCSI2RX_DataLane1Mark = (1U << 7U), /*!< Data lane 1 is in mark state. */
0175     kCSI2RX_DataLane2Mark = (1U << 8U), /*!< Data lane 2 is in mark state. */
0176     kCSI2RX_DataLane3Mark = (1U << 9U), /*!< Data lane 3 is in mark state. */
0177 };
0178
0179 /*******************************************************************************
0180  * API
0181  ******************************************************************************/
0182 #if defined(__cplusplus)
0183 extern "C" {
0184 #endif
0185
0186 /*!
0187  * @brief Enables and configures the CSI2RX peripheral module.
0188  *
0189  * @param base CSI2RX peripheral address.
0190  * @param config CSI2RX module configuration structure.
0191  */
0192 void CSI2RX_Init(MIPI_CSI2RX_Type *base, const csi2rx_config_t *config);
0193
0194 /*!
0195  * @brief Disables the CSI2RX peripheral module.
0196  *
0197  * @param base CSI2RX peripheral address.
0198  */
0199 void CSI2RX_Deinit(MIPI_CSI2RX_Type *base);
0200
0201 /*!
0202  * @brief Gets the MIPI CSI2RX bit error status.
0203  *
0204  * This function gets the RX bit error status, the return value could be compared
0205  * with @ref _csi2rx_bit_error. If one bit ECC error detected, the return value
0206  * could be passed to the function @ref CSI2RX_GetEccBitErrorPosition to get the
0207  * position of the ECC error bit.
0208  *
0209  * Example:
0210  * @code
0211     uint32_t bitError;
0212     uint32_t bitErrorPosition;
0213
0214     bitError = CSI2RX_GetBitError(MIPI_CSI2RX);
0215
0216     if (kCSI2RX_BitErrorEccTwoBit & bitError)
0217     {
0218         Two bits error;
0219     }
0220     else if (kCSI2RX_BitErrorEccOneBit & bitError)
0221     {
0222         One bits error;
0223         bitErrorPosition = CSI2RX_GetEccBitErrorPosition(bitError);
0224     }
0225    @endcode
0226  *
0227  * @param base CSI2RX peripheral address.
0228  * @return The RX bit error status.
0229  */
0230 static inline uint32_t CSI2RX_GetBitError(MIPI_CSI2RX_Type *base)
0231 {
0232     return CSI2RX_REG_BIT_ERR(base);
0233 }
0234
0235 /*!
0236  * @brief Get ECC one bit error bit position.
0237  *
0238  * If @ref CSI2RX_GetBitError detects ECC one bit error, this function could
0239  * extract the error bit position from the return value of @ref CSI2RX_GetBitError.
0240  *
0241  * @param bitError The bit error returned by @ref CSI2RX_GetBitError.
0242  * @return The position of error bit.
0243  */
0244 static inline uint32_t CSI2RX_GetEccBitErrorPosition(uint32_t bitError)
0245 {
0246     return (bitError >> 2U) & 0x1FU;
0247 }
0248
0249 /*!
0250  * @brief Gets the MIPI CSI2RX D-PHY ULPS status.
0251  *
0252  * Example to check whether data lane 0 is in ULPS status.
0253  * @code
0254    uint32_t status = CSI2RX_GetUlpsStatus(MIPI_CSI2RX);
0255
0256    if (kCSI2RX_DataLane0Ulps & status)
0257    {
0258        Data lane 0 is in ULPS status.
0259    }
0260    @endcode
0261  *
0262  * @param base CSI2RX peripheral address.
0263  * @return The MIPI CSI2RX D-PHY ULPS status, it is OR'ed value or @ref _csi2rx_ulps_status.
0264  */
0265 static inline uint32_t CSI2RX_GetUlpsStatus(MIPI_CSI2RX_Type *base)
0266 {
0267     return CSI2RX_REG_ULPS_STATUS(base);
0268 }
0269
0270 /*!
0271  * @brief Gets the MIPI CSI2RX D-PHY PPI error lanes.
0272  *
0273  * This function checks the PPI error occurred on which data lanes, the returned
0274  * value is OR'ed value of @ref csi2rx_ppi_error_t. For example, if the ErrSotHS
0275  * is detected, to check the ErrSotHS occurred on which data lanes, use like this:
0276  *
0277  * @code
0278    uint32_t errorDataLanes = CSI2RX_GetPpiErrorDataLanes(MIPI_CSI2RX, kCSI2RX_PpiErrorSotHs);
0279
0280    if (kCSI2RX_DataLane0 & errorDataLanes)
0281    {
0282        ErrSotHS occurred on data lane 0.
0283    }
0284
0285    if (kCSI2RX_DataLane1 & errorDataLanes)
0286    {
0287        ErrSotHS occurred on data lane 1.
0288    }
0289    @endcode
0290  *
0291  * @param base CSI2RX peripheral address.
0292  * @param errorType What kind of error to check.
0293  * @return The data lane mask that error @p errorType occurred.
0294  */
0295 static inline uint32_t CSI2RX_GetPpiErrorDataLanes(MIPI_CSI2RX_Type *base, csi2rx_ppi_error_t errorType)
0296 {
0297     uint32_t errorLanes;
0298
0299     if (kCSI2RX_PpiErrorSotHs == errorType)
0300     {
0301         errorLanes = CSI2RX_REG_PPI_ERRSOT_HS(base);
0302     }
0303     else if (kCSI2RX_PpiErrorSotSyncHs == errorType)
0304     {
0305         errorLanes = CSI2RX_REG_PPI_ERRSOTSYNC_HS(base);
0306     }
0307     else if (kCSI2RX_PpiErrorEsc == errorType)
0308     {
0309         errorLanes = CSI2RX_REG_PPI_ERRESC(base);
0310     }
0311     else if (kCSI2RX_PpiErrorSyncEsc == errorType)
0312     {
0313         errorLanes = CSI2RX_REG_PPI_ERRSYNCESC(base);
0314     }
0315     else
0316     {
0317         errorLanes = CSI2RX_REG_PPI_ERRCONTROL(base);
0318     }
0319
0320     return errorLanes;
0321 }
0322
0323 /*!
0324  * @brief Enable the MIPI CSI2RX interrupts.
0325  *
0326  * This function enables the MIPI CSI2RX interrupts. The interrupts to enable
0327  * are passed in as an OR'ed value of @ref _csi2rx_interrupt. For example, to enable
0328  * one bit and two bit ECC error interrupts, use like this:
0329  *
0330  * @code
0331    CSI2RX_EnableInterrupts(MIPI_CSI2RX, kCSI2RX_InterruptEccOneBitError | kCSI2RX_InterruptEccTwoBitError);
0332    @endcode
0333  *
0334  * @param base CSI2RX peripheral address.
0335  * @param mask OR'ed value of @ref _csi2rx_interrupt.
0336  */
0337 static inline void CSI2RX_EnableInterrupts(MIPI_CSI2RX_Type *base, uint32_t mask)
0338 {
0339     CSI2RX_REG_IRQ_MASK(base) &= ~mask;
0340 }
0341
0342 /*!
0343  * @brief Disable the MIPI CSI2RX interrupts.
0344  *
0345  * This function disables the MIPI CSI2RX interrupts. The interrupts to disable
0346  * are passed in as an OR'ed value of @ref _csi2rx_interrupt. For example, to disable
0347  * one bit and two bit ECC error interrupts, use like this:
0348  *
0349  * @code
0350    CSI2RX_DisableInterrupts(MIPI_CSI2RX, kCSI2RX_InterruptEccOneBitError | kCSI2RX_InterruptEccTwoBitError);
0351    @endcode
0352  *
0353  * @param base CSI2RX peripheral address.
0354  * @param mask OR'ed value of @ref _csi2rx_interrupt.
0355  */
0356 static inline void CSI2RX_DisableInterrupts(MIPI_CSI2RX_Type *base, uint32_t mask)
0357 {
0358     CSI2RX_REG_IRQ_MASK(base) |= mask;
0359 }
0360
0361 /*!
0362  * @brief Get the MIPI CSI2RX interrupt status.
0363  *
0364  * This function returns the MIPI CSI2RX interrupts status as an OR'ed value
0365  * of @ref _csi2rx_interrupt.
0366  *
0367  * @param base CSI2RX peripheral address.
0368  * @return OR'ed value of @ref _csi2rx_interrupt.
0369  */
0370 static inline uint32_t CSI2RX_GetInterruptStatus(MIPI_CSI2RX_Type *base)
0371 {
0372     return CSI2RX_REG_IRQ_STATUS(base);
0373 }
0374
0375 #if defined(__cplusplus)
0376 }
0377 #endif
0378
0379 /*!
0380  *@}
0381  */
0382
0383 #endif /* _FSL_MIPI_CSI2RX_H_ */