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File indexing completed on 2025-05-11 08:23:00
0001 /* 0002 * Copyright 2019-2021 NXP 0003 * All rights reserved. 0004 * 0005 * 0006 * SPDX-License-Identifier: BSD-3-Clause 0007 */ 0008 0009 #ifndef _FSL_MECC_H_ 0010 #define _FSL_MECC_H_ 0011 0012 #include "fsl_common.h" 0013 0014 /*! 0015 * @addtogroup mecc 0016 * @{ 0017 */ 0018 0019 /****************************************************************************** 0020 * Definitions. 0021 *****************************************************************************/ 0022 0023 /*! @name Driver version */ 0024 /*@{*/ 0025 /*! @brief Driver version 2.0.2. */ 0026 #define FSL_MECC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U)) 0027 /*@}*/ 0028 /*! @brief Error codes for the MECC driver. */ 0029 enum 0030 { 0031 kStatus_MECC_BankMiss = MAKE_STATUS(kStatusGroup_MECC, 0), /*!< Ocram bank miss */ 0032 }; 0033 0034 /*! 0035 * @brief MECC interrupt configuration structure, default settings all disabled. 0036 * 0037 * This structure contains the settings for all of the MECC interrupt configurations. 0038 */ 0039 enum 0040 { 0041 kMECC_SingleError0InterruptEnable = 0042 MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank0 interrupt enable.*/ 0043 kMECC_SingleError1InterruptEnable = 0044 MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank1 interrupt enable*/ 0045 kMECC_SingleError2InterruptEnable = 0046 MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank2 interrupt enable*/ 0047 kMECC_SingleError3InterruptEnable = 0048 MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK, /*!< Single Bit Error On Ocram Bank3 interrupt enable*/ 0049 0050 kMECC_MultiError0InterruptEnable = 0051 MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank0 interrupt enable*/ 0052 kMECC_MultiError1InterruptEnable = 0053 MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank1 interrupt enable*/ 0054 kMECC_MultiError2InterruptEnable = 0055 MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank2 interrupt enable*/ 0056 kMECC_MultiError3InterruptEnable = 0057 MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK, /*!< Multiple Bits Error On Ocram Bank3 interrupt enable*/ 0058 0059 kMECC_StrobeError0InterruptEnable = 0060 MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank0 interrupt enable*/ 0061 kMECC_StrobeError1InterruptEnable = 0062 MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank1 interrupt enable*/ 0063 kMECC_StrobeError2InterruptEnable = 0064 MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank2 interrupt enable*/ 0065 kMECC_StrobeError3InterruptEnable = 0066 MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK, /*!< AXI Strobe Error On Ocram Bank3 interrupt enable*/ 0067 0068 kMECC_AccessError0InterruptEnable = 0069 MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK, /*!< Ocram Access Error On Bank0 interrupt enable*/ 0070 kMECC_AccessError1InterruptEnable = 0071 MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK, /*!< Ocram Access Error On Bank1 interrupt enable*/ 0072 kMECC_AccessError2InterruptEnable = 0073 MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK, /*!< Ocram Access Error On Bank2 interrupt enable*/ 0074 kMECC_AccessError3InterruptEnable = 0075 MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK, /*!< Ocram Access Error On Bank3 interrupt enable*/ 0076 0077 kMECC_AllInterruptsEnable = 0xFFFF, /*!< all interrupts enable */ 0078 }; 0079 0080 /*! 0081 * @brief MECC interrupt status configuration structure, default settings all disabled. 0082 * 0083 * This structure contains the settings for all of the MECC interrupt status configurations. 0084 */ 0085 enum 0086 { 0087 kMECC_SingleError0InterruptStatusEnable = 0088 MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank0 interrupt status enable.*/ 0089 kMECC_SingleError1InterruptStatusEnable = 0090 MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank1 interrupt status enable*/ 0091 kMECC_SingleError2InterruptStatusEnable = 0092 MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank2 interrupt status enable*/ 0093 kMECC_SingleError3InterruptStatusEnable = 0094 MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK, /*!< Single Bit Error On Ocram Bank3 interrupt status enable*/ 0095 0096 kMECC_MultiError0InterruptStatusEnable = 0097 MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank0 interrupt status enable*/ 0098 kMECC_MultiError1InterruptStatusEnable = 0099 MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank1 interrupt status enable*/ 0100 kMECC_MultiError2InterruptStatusEnable = 0101 MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank2 interrupt status enable*/ 0102 kMECC_MultiError3InterruptStatusEnable = 0103 MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK, /*!< Multiple Bits Error On Ocram Bank3 interrupt status enable*/ 0104 0105 kMECC_StrobeError0InterruptStatusEnable = 0106 MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank0 interrupt status enable*/ 0107 kMECC_StrobeError1InterruptStatusEnable = 0108 MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank1 interrupt status enable*/ 0109 kMECC_StrobeError2InterruptStatusEnable = 0110 MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank2 interrupt status enable*/ 0111 kMECC_StrobeError3InterruptStatusEnable = 0112 MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK, /*!< AXI Strobe Error On Ocram Bank3 interrupt status enable*/ 0113 0114 kMECC_AccessError0InterruptStatusEnable = 0115 MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK, /*!< Ocram Access Error On Bank0 interrupt status enable*/ 0116 kMECC_AccessError1InterruptStatusEnable = 0117 MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK, /*!< Ocram Access Error On Bank1 interrupt status enable*/ 0118 kMECC_AccessError2InterruptStatusEnable = 0119 MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK, /*!< Ocram Access Error On Bank2 interrupt status enable*/ 0120 kMECC_AccessError3InterruptStatusEnable = 0121 MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK, /*!< Ocram Access Error On Bank3 interrupt status enable*/ 0122 0123 kMECC_AllInterruptsStatusEnable = 0xFFFF, /*!< all interrupts enable */ 0124 }; 0125 0126 /*! 0127 * @brief MECC status flags. 0128 * 0129 * This provides constants for the MECC status flags for use in the MECC functions. 0130 */ 0131 enum 0132 { 0133 kMECC_SingleError0InterruptFlag = 0134 MECC_ERR_STATUS_SINGLE_ERR0_MASK, /*!< Single Bit Error On Ocram Bank0 interrupt flag*/ 0135 kMECC_SingleError1InterruptFlag = 0136 MECC_ERR_STATUS_SINGLE_ERR1_MASK, /*!< Single Bit Error On Ocram Bank1 interrupt flag*/ 0137 kMECC_SingleError2InterruptFlag = 0138 MECC_ERR_STATUS_SINGLE_ERR2_MASK, /*!< Single Bit Error On Ocram Bank2 interrupt flag*/ 0139 kMECC_SingleError3InterruptFlag = 0140 MECC_ERR_STATUS_SINGLE_ERR3_MASK, /*!< Single Bit Error On Ocram Bank3 interrupt flag*/ 0141 0142 kMECC_MultiError0InterruptFlag = 0143 MECC_ERR_STATUS_MULTI_ERR0_MASK, /*!< Multiple Bits Error On Ocram Bank0 interrupt flag*/ 0144 kMECC_MultiError1InterruptFlag = 0145 MECC_ERR_STATUS_MULTI_ERR1_MASK, /*!< Multiple Bits Error On Ocram Bank1 interrupt flag*/ 0146 kMECC_MultiError2InterruptFlag = 0147 MECC_ERR_STATUS_MULTI_ERR2_MASK, /*!< Multiple Bits Error On Ocram Bank2 interrupt flag*/ 0148 kMECC_MultiError3InterruptFlag = 0149 MECC_ERR_STATUS_MULTI_ERR3_MASK, /*!< Multiple Bits Error On Ocram Bank3 interrupt flag*/ 0150 0151 kMECC_StrobeError0InterruptFlag = 0152 MECC_ERR_STATUS_STRB_ERR0_MASK, /*!< AXI Strobe Error On Ocram Bank0 interrupt flag*/ 0153 kMECC_StrobeError1InterruptFlag = 0154 MECC_ERR_STATUS_STRB_ERR1_MASK, /*!< AXI Strobe Error On Ocram Bank1 interrupt flag*/ 0155 kMECC_StrobeError2InterruptFlag = 0156 MECC_ERR_STATUS_STRB_ERR2_MASK, /*!< AXI Strobe Error On Ocram Bank2 interrupt flag*/ 0157 kMECC_StrobeError3InterruptFlag = 0158 MECC_ERR_STATUS_STRB_ERR3_MASK, /*!< AXI Strobe Error On Ocram Bank3 interrupt flag*/ 0159 0160 kMECC_AccessError0InterruptFlag = MECC_ERR_STATUS_ADDR_ERR0_MASK, /*!< Ocram Access Error On Bank0 interrupt flag*/ 0161 kMECC_AccessError1InterruptFlag = MECC_ERR_STATUS_ADDR_ERR1_MASK, /*!< Ocram Access Error On Bank1 interrupt flag*/ 0162 kMECC_AccessError2InterruptFlag = MECC_ERR_STATUS_ADDR_ERR2_MASK, /*!< Ocram Access Error On Bank2 interrupt flag*/ 0163 kMECC_AccessError3InterruptFlag = MECC_ERR_STATUS_ADDR_ERR3_MASK, /*!< Ocram Access Error On Bank3 interrupt flag*/ 0164 0165 kMECC_AllInterruptsFlag = 0xFFFF, /*!< all interrupts interrupt flag */ 0166 }; 0167 0168 /*! @brief MECC ocram bank number */ 0169 enum 0170 { 0171 kMECC_OcramBank0 = 0U, /*!< ocram bank number 0: ocram_base_address+0x20*i */ 0172 kMECC_OcramBank1 = 1U, /*!< ocram bank number 1: ocram_base_address+0x20*i+0x8 */ 0173 kMECC_OcramBank2 = 2U, /*!< ocram bank number 2: ocram_base_address+0x20*i+0x10 */ 0174 kMECC_OcramBank3 = 3U, /*!< ocram bank number 3: ocram_base_address+0x20*i+0x18 */ 0175 }; 0176 0177 /*! @brief MECC instance */ 0178 enum 0179 { 0180 kMECC_Instance0 = 0U, /*!< Peripheral MECC1 base */ 0181 kMECC_Instance1 = 1U, /*!< Peripheral MECC2 base */ 0182 }; 0183 0184 /*! @brief MECC user configuration.*/ 0185 typedef struct _mecc_config 0186 { 0187 bool enableMecc; /*!< Enable the MECC function. */ 0188 uint32_t Ocram1StartAddress; /*!< Ocram 1 start address. */ 0189 uint32_t Ocram1EndAddress; /*!< Ocram 1 end address. */ 0190 uint32_t Ocram2StartAddress; /*!< Ocram 2 start address. */ 0191 uint32_t Ocram2EndAddress; /*!< Ocram 2 end address. */ 0192 } mecc_config_t; 0193 0194 /*! @brief MECC ocram single error information, including single error address, ECC code, error data and error bit 0195 * position */ 0196 typedef struct _mecc_single_error_info 0197 { 0198 uint32_t singleErrorAddress; /*!< Single error address on Ocram bank n */ 0199 uint32_t singleErrorDataLow; /*!< Single error low 32 bits uncorrected read data on Ocram bank n */ 0200 uint32_t singleErrorDataHigh; /*!< Single error high 32 bits uncorrected read data on Ocram bank n */ 0201 uint32_t singleErrorPosLow; /*!< Single error bit postion of low 32 bits read data on Ocram bank n */ 0202 uint32_t singleErrorPosHigh; /*!< Single error bit postion of high 32 bits read data on Ocram bank n */ 0203 uint8_t singleErrorEccCode; /*!< Single error ECC code on Ocram bank n */ 0204 } mecc_single_error_info_t; 0205 0206 /*! @brief MECC ocram multiple error information, including multiple error address, ECC code, error data */ 0207 typedef struct _mecc_multi_error_info 0208 { 0209 uint32_t multiErrorAddress; /*!< Multiple error address on Ocram bank n */ 0210 uint32_t multiErrorDataLow; /*!< Multiple error low 32 bits read data on Ocram bank n */ 0211 uint32_t multiErrorDataHigh; /*!< Multiple error high 32 bits read data on Ocram bank n */ 0212 uint8_t multiErrorEccCode; /*!< Multiple error ECC code on Ocram bank n */ 0213 } mecc_multi_error_info_t; 0214 0215 /******************************************************************************* 0216 * APIs 0217 ******************************************************************************/ 0218 0219 #if defined(__cplusplus) 0220 extern "C" { 0221 #endif 0222 0223 /*! 0224 * @name Initialization and deinitialization 0225 * @{ 0226 */ 0227 0228 /*! 0229 * @brief MECC module initialization function. 0230 * 0231 * @param base MECC base address. 0232 * @param config pointer to the MECC configuration structure. 0233 */ 0234 void MECC_Init(MECC_Type *base, mecc_config_t *config); 0235 0236 /*! 0237 * @brief Deinitializes the MECC. 0238 * 0239 * @param base MECC base address. 0240 */ 0241 void MECC_Deinit(MECC_Type *base); 0242 0243 /*! 0244 * @brief Sets the MECC configuration structure to default values. 0245 * 0246 * @param config pointer to the MECC configuration structure. 0247 */ 0248 void MECC_GetDefaultConfig(mecc_config_t *config); 0249 0250 /* @} */ 0251 0252 /*! 0253 * @name Status 0254 * @{ 0255 */ 0256 /*! 0257 * @brief Gets MECC status flags. 0258 * 0259 * @param base MECC peripheral base address. 0260 * @return MECC status flags. 0261 */ 0262 static inline uint32_t MECC_GetStatusFlags(MECC_Type *base) 0263 { 0264 return base->ERR_STATUS & (uint32_t)kMECC_AllInterruptsFlag; 0265 } 0266 0267 /*! 0268 * @brief MECC module clear interrupt status. 0269 * 0270 * @param base MECC base address. 0271 * @param mask status to clear. 0272 */ 0273 static inline void MECC_ClearStatusFlags(MECC_Type *base, uint32_t mask) 0274 { 0275 base->ERR_STATUS = mask; 0276 } 0277 0278 /*! 0279 * @brief MECC module enable interrupt status. 0280 * 0281 * @param base MECC base address. 0282 * @param mask status to enable. 0283 */ 0284 static inline void MECC_EnableInterruptStatus(MECC_Type *base, uint32_t mask) 0285 { 0286 base->ERR_STAT_EN |= mask; 0287 } 0288 0289 /*! 0290 * @brief MECC module disable interrupt status. 0291 * 0292 * @param base MECC base address. 0293 * @param mask status to disable. 0294 */ 0295 static inline void MECC_DisableInterruptStatus(MECC_Type *base, uint32_t mask) 0296 { 0297 base->ERR_STAT_EN &= ~mask; 0298 } 0299 0300 /* @} */ 0301 0302 /*! 0303 * @name Interrupts 0304 * @{ 0305 */ 0306 0307 /*! 0308 * @brief MECC module enable interrupt. 0309 * 0310 * @param base MECC base address. 0311 * @param mask The interrupts to enable. 0312 */ 0313 static inline void MECC_EnableInterrupts(MECC_Type *base, uint32_t mask) 0314 { 0315 base->ERR_SIG_EN |= mask; 0316 } 0317 0318 /*! 0319 * @brief MECC module disable interrupt. 0320 * 0321 * @param base MECC base address. 0322 * @param mask The interrupts to disable. 0323 */ 0324 static inline void MECC_DisableInterrupts(MECC_Type *base, uint32_t mask) 0325 { 0326 base->ERR_SIG_EN &= ~mask; 0327 } 0328 /* @} */ 0329 0330 /*! 0331 * @name functional 0332 * @{ 0333 */ 0334 0335 /*! 0336 * @brief MECC module error injection. 0337 * 0338 * @param base MECC base address. 0339 * @param lowerrordata low 32 bits data. 0340 * @param higherrordata high 32 bits data. 0341 * @param eccdata ecc code. 0342 * @param banknumber ocram bank number. 0343 * @retval kStatus_Success. 0344 * 0345 * Bank0: ocram_base_address+0x20*i 0346 * Bank1: ocram_base_address+0x20*i+0x8 0347 * Bank2: ocram_base_address+0x20*i+0x10 0348 * Bank3: ocram_base_address+0x20*i+0x18 0349 * i = 0,1,2,3,4..... 0350 */ 0351 status_t MECC_ErrorInjection( 0352 MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber); 0353 0354 /*! 0355 * @brief MECC module get single error information. 0356 * 0357 * @param base MECC base address. 0358 * @param info single error information. 0359 * @param banknumber ocram bank number. 0360 * @retval kStatus_Success. 0361 * @retval kStatus_MECC_BankMiss. 0362 * 0363 * Bank0: ocram_base_address+0x20*i 0364 * Bank1: ocram_base_address+0x20*i+0x8 0365 * Bank2: ocram_base_address+0x20*i+0x10 0366 * Bank3: ocram_base_address+0x20*i+0x18 0367 * i = 0,1,2,3,4..... 0368 */ 0369 status_t MECC_GetSingleErrorInfo(MECC_Type *base, mecc_single_error_info_t *info, uint8_t banknumber); 0370 0371 /*! 0372 * @brief MECC module get multiple error information. 0373 * 0374 * @param base MECC base address. 0375 * @param info multiple error information. 0376 * @param banknumber ocram bank number. 0377 * @retval kStatus_Success. 0378 * @retval kStatus_MECC_BankMiss. 0379 * 0380 * Bank0: ocram_base_address+0x20*i 0381 * Bank1: ocram_base_address+0x20*i+0x8 0382 * Bank2: ocram_base_address+0x20*i+0x10 0383 * Bank3: ocram_base_address+0x20*i+0x18 0384 * i = 0,1,2,3,4..... 0385 */ 0386 status_t MECC_GetMultiErrorInfo(MECC_Type *base, mecc_multi_error_info_t *info, uint8_t banknumber); 0387 0388 /*! @}*/ 0389 0390 #if defined(__cplusplus) 0391 } 0392 #endif 0393 0394 /*! @}*/ 0395 0396 #endif
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