drivers/lpuart/fsl_lpuart.c

0001 /*
0002  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2022 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #include "fsl_lpuart.h"
0010
0011 /*******************************************************************************
0012  * Definitions
0013  ******************************************************************************/
0014
0015 /* Component ID definition, used by tools. */
0016 #ifndef FSL_COMPONENT_ID
0017 #define FSL_COMPONENT_ID "platform.drivers.lpuart"
0018 #endif
0019
0020 /* LPUART transfer state. */
0021 enum
0022 {
0023     kLPUART_TxIdle, /*!< TX idle. */
0024     kLPUART_TxBusy, /*!< TX busy. */
0025     kLPUART_RxIdle, /*!< RX idle. */
0026     kLPUART_RxBusy  /*!< RX busy. */
0027 };
0028
0029 /*******************************************************************************
0030  * Prototypes
0031  ******************************************************************************/
0032 /*!
0033  * @brief Check whether the RX ring buffer is full.
0034  *
0035  * @userData handle LPUART handle pointer.
0036  * @retval true  RX ring buffer is full.
0037  * @retval false RX ring buffer is not full.
0038  */
0039 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle);
0040
0041 /*!
0042  * @brief Write to TX register using non-blocking method.
0043  *
0044  * This function writes data to the TX register directly, upper layer must make
0045  * sure the TX register is empty or TX FIFO has empty room before calling this function.
0046  *
0047  * @note This function does not check whether all the data has been sent out to bus,
0048  * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is
0049  * finished.
0050  *
0051  * @param base LPUART peripheral base address.
0052  * @param data Start address of the data to write.
0053  * @param length Size of the buffer to be sent.
0054  */
0055 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
0056
0057 /*!
0058  * @brief Read RX register using non-blocking method.
0059  *
0060  * This function reads data from the TX register directly, upper layer must make
0061  * sure the RX register is full or TX FIFO has data before calling this function.
0062  *
0063  * @param base LPUART peripheral base address.
0064  * @param data Start address of the buffer to store the received data.
0065  * @param length Size of the buffer.
0066  */
0067 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length);
0068
0069 /*!
0070  * @brief LPUART_TransferHandleIDLEIsReady handle function.
0071  * This function handles when IDLE is ready.
0072  *
0073  * @param base LPUART peripheral base address.
0074  * @param irqHandle LPUART handle pointer.
0075  */
0076 static void LPUART_TransferHandleIDLEReady(LPUART_Type *base, lpuart_handle_t *handle);
0077
0078 /*!
0079  * @brief LPUART_TransferHandleReceiveDataIsFull handle function.
0080  * This function handles when receive data is full.
0081  *
0082  * @param base LPUART peripheral base address.
0083  * @param handle LPUART handle pointer.
0084  */
0085 static void LPUART_TransferHandleReceiveDataFull(LPUART_Type *base, lpuart_handle_t *handle);
0086
0087 /*!
0088  * @brief LPUART_TransferHandleSendDataIsEmpty handle function.
0089  * This function handles when send data is empty.
0090  *
0091  * @param base LPUART peripheral base address.
0092  * @param irqHandle LPUART handle pointer.
0093  */
0094 static void LPUART_TransferHandleSendDataEmpty(LPUART_Type *base, lpuart_handle_t *handle);
0095
0096 /*!
0097  * @brief LPUART_TransferHandleTransmissionIsComplete handle function.
0098  * This function handles Transmission complete and the interrupt is enabled.
0099  *
0100  * @param base LPUART peripheral base address.
0101  * @param irqHandle LPUART handle pointer.
0102  */
0103 static void LPUART_TransferHandleTransmissionComplete(LPUART_Type *base, lpuart_handle_t *handle);
0104
0105 /*******************************************************************************
0106  * Variables
0107  ******************************************************************************/
0108 /* Array of LPUART peripheral base address. */
0109 static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS;
0110 /* Array of LPUART handle. */
0111 void *s_lpuartHandle[ARRAY_SIZE(s_lpuartBases)];
0112 /* Array of LPUART IRQ number. */
0113 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
0114 static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS;
0115 const IRQn_Type s_lpuartTxIRQ[]        = LPUART_TX_IRQS;
0116 #else
0117 const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS;
0118 #endif
0119 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0120 /* Array of LPUART clock name. */
0121 static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS;
0122
0123 #if defined(LPUART_PERIPH_CLOCKS)
0124 /* Array of LPUART functional clock name. */
0125 static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS;
0126 #endif
0127
0128 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0129
0130 /* LPUART ISR for transactional APIs. */
0131 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
0132 lpuart_isr_t s_lpuartIsr[ARRAY_SIZE(s_lpuartBases)] = {[0 ...(ARRAY_SIZE(s_lpuartBases) - 1)] =
0133                                                            (lpuart_isr_t)DefaultISR};
0134 #else
0135 lpuart_isr_t s_lpuartIsr[ARRAY_SIZE(s_lpuartBases)];
0136 #endif
0137
0138 /*******************************************************************************
0139  * Code
0140  ******************************************************************************/
0141 /*!
0142  * brief Get the LPUART instance from peripheral base address.
0143  *
0144  * param base LPUART peripheral base address.
0145  * return LPUART instance.
0146  */
0147 uint32_t LPUART_GetInstance(LPUART_Type *base)
0148 {
0149     uint32_t instance;
0150
0151     /* Find the instance index from base address mappings. */
0152     for (instance = 0U; instance < ARRAY_SIZE(s_lpuartBases); instance++)
0153     {
0154         if (s_lpuartBases[instance] == base)
0155         {
0156             break;
0157         }
0158     }
0159
0160     assert(instance < ARRAY_SIZE(s_lpuartBases));
0161
0162     return instance;
0163 }
0164
0165 /*!
0166  * brief Get the length of received data in RX ring buffer.
0167  *
0168  * userData handle LPUART handle pointer.
0169  * return Length of received data in RX ring buffer.
0170  */
0171 size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle)
0172 {
0173     assert(NULL != handle);
0174
0175     size_t size;
0176     size_t tmpRxRingBufferSize   = handle->rxRingBufferSize;
0177     uint16_t tmpRxRingBufferTail = handle->rxRingBufferTail;
0178     uint16_t tmpRxRingBufferHead = handle->rxRingBufferHead;
0179
0180     if (tmpRxRingBufferTail > tmpRxRingBufferHead)
0181     {
0182         size = ((size_t)tmpRxRingBufferHead + tmpRxRingBufferSize - (size_t)tmpRxRingBufferTail);
0183     }
0184     else
0185     {
0186         size = ((size_t)tmpRxRingBufferHead - (size_t)tmpRxRingBufferTail);
0187     }
0188
0189     return size;
0190 }
0191
0192 static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle)
0193 {
0194     assert(NULL != handle);
0195
0196     bool full;
0197
0198     if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U))
0199     {
0200         full = true;
0201     }
0202     else
0203     {
0204         full = false;
0205     }
0206     return full;
0207 }
0208
0209 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
0210 {
0211     assert(NULL != data);
0212
0213     size_t i;
0214
0215     /* The Non Blocking write data API assume user have ensured there is enough space in
0216     peripheral to write. */
0217     for (i = 0; i < length; i++)
0218     {
0219         base->DATA = data[i];
0220     }
0221 }
0222
0223 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
0224 {
0225     assert(NULL != data);
0226
0227     size_t i;
0228 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
0229     uint32_t ctrl        = base->CTRL;
0230     bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) ||
0231                             (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U)));
0232 #endif
0233
0234     /* The Non Blocking read data API assume user have ensured there is enough space in
0235     peripheral to write. */
0236     for (i = 0; i < length; i++)
0237     {
0238 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
0239         if (isSevenDataBits)
0240         {
0241             data[i] = (uint8_t)(base->DATA & 0x7FU);
0242         }
0243         else
0244         {
0245             data[i] = (uint8_t)base->DATA;
0246         }
0247 #else
0248         data[i] = (uint8_t)(base->DATA);
0249 #endif
0250     }
0251 }
0252
0253 /*!
0254  * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
0255  *
0256  * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
0257  * to configure the configuration structure and get the default configuration.
0258  * The example below shows how to use this API to configure the LPUART.
0259  * code
0260  *  lpuart_config_t lpuartConfig;
0261  *  lpuartConfig.baudRate_Bps = 115200U;
0262  *  lpuartConfig.parityMode = kLPUART_ParityDisabled;
0263  *  lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
0264  *  lpuartConfig.isMsb = false;
0265  *  lpuartConfig.stopBitCount = kLPUART_OneStopBit;
0266  *  lpuartConfig.txFifoWatermark = 0;
0267  *  lpuartConfig.rxFifoWatermark = 1;
0268  *  LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
0269  * endcode
0270  *
0271  * param base LPUART peripheral base address.
0272  * param config Pointer to a user-defined configuration structure.
0273  * param srcClock_Hz LPUART clock source frequency in HZ.
0274  * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
0275  * retval kStatus_Success LPUART initialize succeed
0276  */
0277 #ifndef __rtems__
0278 status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz)
0279 #else /* __rtems__ */
0280 status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz, bool do_reset)
0281 #endif /* __rtems__ */
0282 {
0283     assert(NULL != config);
0284     assert(0U < config->baudRate_Bps);
0285 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
0286     assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->txFifoWatermark);
0287     assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->rxFifoWatermark);
0288 #endif
0289
0290     status_t status = kStatus_Success;
0291     uint32_t temp;
0292     uint16_t sbr, sbrTemp;
0293     uint8_t osr, osrTemp;
0294     uint32_t tempDiff, calculatedBaud, baudDiff;
0295
0296     /* This LPUART instantiation uses a slightly different baud rate calculation
0297      * The idea is to use the best OSR (over-sampling rate) possible
0298      * Note, OSR is typically hard-set to 16 in other LPUART instantiations
0299      * loop to find the best OSR value possible, one that generates minimum baudDiff
0300      * iterate through the rest of the supported values of OSR */
0301
0302     baudDiff = config->baudRate_Bps;
0303     osr      = 0U;
0304     sbr      = 0U;
0305     for (osrTemp = 4U; osrTemp <= 32U; osrTemp++)
0306     {
0307         /* calculate the temporary sbr value   */
0308         sbrTemp = (uint16_t)((srcClock_Hz * 10U / (config->baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U);
0309         /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
0310         if (sbrTemp == 0U)
0311         {
0312             sbrTemp = 1U;
0313         }
0314         /* Calculate the baud rate based on the temporary OSR and SBR values */
0315         calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp));
0316         tempDiff       = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) :
0317                                                            (config->baudRate_Bps - calculatedBaud);
0318
0319         if (tempDiff <= baudDiff)
0320         {
0321             baudDiff = tempDiff;
0322             osr      = osrTemp; /* update and store the best OSR value calculated */
0323             sbr      = sbrTemp; /* update store the best SBR value calculated */
0324         }
0325     }
0326
0327 #ifndef __rtems__
0328     /* Check to see if actual baud rate is within 3% of desired baud rate
0329      * based on the best calculate OSR value */
0330     if (baudDiff > ((config->baudRate_Bps / 100U) * 3U))
0331     {
0332         /* Unacceptable baud rate difference of more than 3%*/
0333         status = kStatus_LPUART_BaudrateNotSupport;
0334     }
0335     else
0336 #else /* __rtems__ */
0337     /*
0338      * Better to have any baudrate then none. With this change, the function can
0339      * not fail any more.
0340      */
0341 #endif /* __rtems__ */
0342     {
0343 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0344
0345         uint32_t instance = LPUART_GetInstance(base);
0346
0347         /* Enable lpuart clock */
0348         (void)CLOCK_EnableClock(s_lpuartClock[instance]);
0349 #if defined(LPUART_PERIPH_CLOCKS)
0350         (void)CLOCK_EnableClock(s_lpuartPeriphClocks[instance]);
0351 #endif
0352
0353 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0354
0355 #if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
0356         /*Reset all internal logic and registers, except the Global Register */
0357 #ifndef __rtems__
0358         LPUART_SoftwareReset(base);
0359 #else /* __rtems__ */
0360         if (do_reset) {
0361             LPUART_SoftwareReset(base);
0362         }
0363 #endif /* __rtems__ */
0364 #else
0365         /* Disable LPUART TX RX before setting. */
0366         base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
0367 #endif
0368
0369         temp = base->BAUD;
0370
0371         /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
0372          * If so, then "BOTHEDGE" sampling must be turned on */
0373         if ((osr > 3U) && (osr < 8U))
0374         {
0375             temp |= LPUART_BAUD_BOTHEDGE_MASK;
0376         }
0377
0378         /* program the osr value (bit value is one less than actual value) */
0379         temp &= ~LPUART_BAUD_OSR_MASK;
0380         temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL);
0381
0382         /* write the sbr value to the BAUD registers */
0383         temp &= ~LPUART_BAUD_SBR_MASK;
0384         base->BAUD = temp | LPUART_BAUD_SBR(sbr);
0385
0386         /* Set bit count and parity mode. */
0387         base->BAUD &= ~LPUART_BAUD_M10_MASK;
0388
0389         temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
0390                               LPUART_CTRL_IDLECFG_MASK);
0391
0392         temp |= (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) |
0393                 LPUART_CTRL_ILT(config->rxIdleType);
0394
0395 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
0396         if (kLPUART_SevenDataBits == config->dataBitsCount)
0397         {
0398             if (kLPUART_ParityDisabled != config->parityMode)
0399             {
0400                 temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */
0401             }
0402             else
0403             {
0404                 temp |= LPUART_CTRL_M7_MASK;
0405             }
0406         }
0407         else
0408 #endif
0409         {
0410             if (kLPUART_ParityDisabled != config->parityMode)
0411             {
0412                 temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */
0413             }
0414         }
0415
0416         base->CTRL = temp;
0417
0418 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
0419         /* set stop bit per char */
0420         temp       = base->BAUD & ~LPUART_BAUD_SBNS_MASK;
0421         base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount);
0422 #endif
0423
0424 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
0425         /* Set tx/rx WATER watermark
0426            Note:
0427            Take care of the RX FIFO, RX interrupt request only assert when received bytes
0428            equal or more than RX water mark, there is potential issue if RX water
0429            mark larger than 1.
0430            For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
0431            5 bytes are received. the last byte will be saved in FIFO but not trigger
0432            RX interrupt because the water mark is 2.
0433          */
0434         base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16U) | config->txFifoWatermark);
0435
0436         /* Enable tx/rx FIFO */
0437         base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK);
0438
0439         /* Flush FIFO */
0440         base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK);
0441 #endif
0442
0443         /* Clear all status flags */
0444         temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
0445                 LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
0446
0447 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
0448         temp |= LPUART_STAT_LBKDIF_MASK;
0449 #endif
0450
0451 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
0452         temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
0453 #endif
0454
0455 #if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
0456         /* Set the CTS configuration/TX CTS source. */
0457         base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource);
0458         if (true == config->enableRxRTS)
0459         {
0460             /* Enable the receiver RTS(request-to-send) function. */
0461             base->MODIR |= LPUART_MODIR_RXRTSE_MASK;
0462         }
0463         if (true == config->enableTxCTS)
0464         {
0465             /* Enable the CTS(clear-to-send) function. */
0466             base->MODIR |= LPUART_MODIR_TXCTSE_MASK;
0467         }
0468 #endif
0469
0470         /* Set data bits order. */
0471         if (true == config->isMsb)
0472         {
0473             temp |= LPUART_STAT_MSBF_MASK;
0474         }
0475         else
0476         {
0477             temp &= ~LPUART_STAT_MSBF_MASK;
0478         }
0479
0480         base->STAT |= temp;
0481
0482         /* Enable TX/RX base on configure structure. */
0483         temp = base->CTRL;
0484         if (true == config->enableTx)
0485         {
0486             temp |= LPUART_CTRL_TE_MASK;
0487         }
0488
0489         if (true == config->enableRx)
0490         {
0491             temp |= LPUART_CTRL_RE_MASK;
0492         }
0493
0494         base->CTRL = temp;
0495     }
0496
0497     return status;
0498 }
0499 /*!
0500  * brief Deinitializes a LPUART instance.
0501  *
0502  * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
0503  *
0504  * param base LPUART peripheral base address.
0505  */
0506 void LPUART_Deinit(LPUART_Type *base)
0507 {
0508     uint32_t temp;
0509
0510 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
0511     /* Wait tx FIFO send out*/
0512     while (0U != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT))
0513     {
0514     }
0515 #endif
0516     /* Wait last char shift out */
0517     while (0U == (base->STAT & LPUART_STAT_TC_MASK))
0518     {
0519     }
0520
0521     /* Clear all status flags */
0522     temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK |
0523             LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK);
0524
0525 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
0526     temp |= LPUART_STAT_LBKDIF_MASK;
0527 #endif
0528
0529 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
0530     temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK);
0531 #endif
0532
0533     base->STAT |= temp;
0534
0535     /* Disable the module. */
0536     base->CTRL = 0U;
0537
0538 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
0539     uint32_t instance = LPUART_GetInstance(base);
0540
0541     /* Disable lpuart clock */
0542     (void)CLOCK_DisableClock(s_lpuartClock[instance]);
0543
0544 #if defined(LPUART_PERIPH_CLOCKS)
0545     (void)CLOCK_DisableClock(s_lpuartPeriphClocks[instance]);
0546 #endif
0547
0548 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
0549 }
0550
0551 /*!
0552  * brief Gets the default configuration structure.
0553  *
0554  * This function initializes the LPUART configuration structure to a default value. The default
0555  * values are:
0556  *   lpuartConfig->baudRate_Bps = 115200U;
0557  *   lpuartConfig->parityMode = kLPUART_ParityDisabled;
0558  *   lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
0559  *   lpuartConfig->isMsb = false;
0560  *   lpuartConfig->stopBitCount = kLPUART_OneStopBit;
0561  *   lpuartConfig->txFifoWatermark = 0;
0562  *   lpuartConfig->rxFifoWatermark = 1;
0563  *   lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit;
0564  *   lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1;
0565  *   lpuartConfig->enableTx = false;
0566  *   lpuartConfig->enableRx = false;
0567  *
0568  * param config Pointer to a configuration structure.
0569  */
0570 void LPUART_GetDefaultConfig(lpuart_config_t *config)
0571 {
0572     assert(NULL != config);
0573
0574     /* Initializes the configure structure to zero. */
0575     (void)memset(config, 0, sizeof(*config));
0576
0577     config->baudRate_Bps  = 115200U;
0578     config->parityMode    = kLPUART_ParityDisabled;
0579     config->dataBitsCount = kLPUART_EightDataBits;
0580     config->isMsb         = false;
0581 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
0582     config->stopBitCount = kLPUART_OneStopBit;
0583 #endif
0584 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
0585     config->txFifoWatermark = 0U;
0586     config->rxFifoWatermark = 0U;
0587 #endif
0588 #if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
0589     config->enableRxRTS = false;
0590     config->enableTxCTS = false;
0591     config->txCtsConfig = kLPUART_CtsSampleAtStart;
0592     config->txCtsSource = kLPUART_CtsSourcePin;
0593 #endif
0594     config->rxIdleType   = kLPUART_IdleTypeStartBit;
0595     config->rxIdleConfig = kLPUART_IdleCharacter1;
0596     config->enableTx     = false;
0597     config->enableRx     = false;
0598 }
0599
0600 /*!
0601  * brief Sets the LPUART instance baudrate.
0602  *
0603  * This function configures the LPUART module baudrate. This function is used to update
0604  * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
0605  * code
0606  *  LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
0607  * endcode
0608  *
0609  * param base LPUART peripheral base address.
0610  * param baudRate_Bps LPUART baudrate to be set.
0611  * param srcClock_Hz LPUART clock source frequency in HZ.
0612  * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
0613  * retval kStatus_Success Set baudrate succeeded.
0614  */
0615 status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
0616 {
0617     assert(0U < baudRate_Bps);
0618
0619     status_t status = kStatus_Success;
0620     uint32_t temp, oldCtrl;
0621     uint16_t sbr, sbrTemp;
0622     uint8_t osr, osrTemp;
0623     uint32_t tempDiff, calculatedBaud, baudDiff;
0624
0625     /* This LPUART instantiation uses a slightly different baud rate calculation
0626      * The idea is to use the best OSR (over-sampling rate) possible
0627      * Note, OSR is typically hard-set to 16 in other LPUART instantiations
0628      * loop to find the best OSR value possible, one that generates minimum baudDiff
0629      * iterate through the rest of the supported values of OSR */
0630
0631     baudDiff = baudRate_Bps;
0632     osr      = 0U;
0633     sbr      = 0U;
0634     for (osrTemp = 4U; osrTemp <= 32U; osrTemp++)
0635     {
0636         /* calculate the temporary sbr value   */
0637         sbrTemp = (uint16_t)((srcClock_Hz * 10U / (baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U);
0638         /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
0639         if (sbrTemp == 0U)
0640         {
0641             sbrTemp = 1U;
0642         }
0643         /* Calculate the baud rate based on the temporary OSR and SBR values */
0644         calculatedBaud = srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp);
0645
0646         tempDiff = calculatedBaud > baudRate_Bps ? (calculatedBaud - baudRate_Bps) : (baudRate_Bps - calculatedBaud);
0647
0648         if (tempDiff <= baudDiff)
0649         {
0650             baudDiff = tempDiff;
0651             osr      = osrTemp; /* update and store the best OSR value calculated */
0652             sbr      = sbrTemp; /* update store the best SBR value calculated */
0653         }
0654     }
0655
0656     /* Check to see if actual baud rate is within 3% of desired baud rate
0657      * based on the best calculate OSR value */
0658     if (baudDiff < (uint32_t)((baudRate_Bps / 100U) * 3U))
0659     {
0660         /* Store CTRL before disable Tx and Rx */
0661         oldCtrl = base->CTRL;
0662
0663         /* Disable LPUART TX RX before setting. */
0664         base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
0665
0666         temp = base->BAUD;
0667
0668         /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling.
0669          * If so, then "BOTHEDGE" sampling must be turned on */
0670         if ((osr > 3U) && (osr < 8U))
0671         {
0672             temp |= LPUART_BAUD_BOTHEDGE_MASK;
0673         }
0674
0675         /* program the osr value (bit value is one less than actual value) */
0676         temp &= ~LPUART_BAUD_OSR_MASK;
0677         temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL);
0678
0679         /* write the sbr value to the BAUD registers */
0680         temp &= ~LPUART_BAUD_SBR_MASK;
0681         base->BAUD = temp | LPUART_BAUD_SBR(sbr);
0682
0683         /* Restore CTRL. */
0684         base->CTRL = oldCtrl;
0685     }
0686     else
0687     {
0688         /* Unacceptable baud rate difference of more than 3%*/
0689         status = kStatus_LPUART_BaudrateNotSupport;
0690     }
0691
0692     return status;
0693 }
0694
0695 /*!
0696  * brief Enable 9-bit data mode for LPUART.
0697  *
0698  * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user.
0699  *
0700  * param base LPUART peripheral base address.
0701  * param enable true to enable, flase to disable.
0702  */
0703 void LPUART_Enable9bitMode(LPUART_Type *base, bool enable)
0704 {
0705     assert(base != NULL);
0706
0707     uint32_t temp = 0U;
0708
0709     if (enable)
0710     {
0711         /* Set LPUART_CTRL_M for 9-bit mode, clear LPUART_CTRL_PE to disable parity. */
0712         temp = base->CTRL & ~((uint32_t)LPUART_CTRL_PE_MASK | (uint32_t)LPUART_CTRL_M_MASK);
0713         temp |= (uint32_t)LPUART_CTRL_M_MASK;
0714         base->CTRL = temp;
0715     }
0716     else
0717     {
0718         /* Clear LPUART_CTRL_M. */
0719         base->CTRL &= ~(uint32_t)LPUART_CTRL_M_MASK;
0720     }
0721 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
0722     /* Clear LPUART_CTRL_M7 to disable 7-bit mode. */
0723     base->CTRL &= ~(uint32_t)LPUART_CTRL_M7_MASK;
0724 #endif
0725 #if defined(FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT
0726     /* Clear LPUART_BAUD_M10 to disable 10-bit mode. */
0727     base->BAUD &= ~(uint32_t)LPUART_BAUD_M10_MASK;
0728 #endif
0729 }
0730
0731 /*!
0732  * brief Transmit an address frame in 9-bit data mode.
0733  *
0734  * param base LPUART peripheral base address.
0735  * param address LPUART slave address.
0736  */
0737 void LPUART_SendAddress(LPUART_Type *base, uint8_t address)
0738 {
0739     assert(base != NULL);
0740
0741     uint32_t temp = base->DATA & 0xFFFFFC00UL;
0742     temp |= ((uint32_t)address | (1UL << LPUART_DATA_R8T8_SHIFT));
0743     base->DATA = temp;
0744 }
0745
0746 /*!
0747  * brief Enables LPUART interrupts according to a provided mask.
0748  *
0749  * This function enables the LPUART interrupts according to a provided mask. The mask
0750  * is a logical OR of enumeration members. See the ref _lpuart_interrupt_enable.
0751  * This examples shows how to enable TX empty interrupt and RX full interrupt:
0752  * code
0753  *     LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
0754  * endcode
0755  *
0756  * param base LPUART peripheral base address.
0757  * param mask The interrupts to enable. Logical OR of ref _lpuart_interrupt_enable.
0758  */
0759 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
0760 {
0761     /* Only consider the real interrupt enable bits. */
0762     mask &= (uint32_t)kLPUART_AllInterruptEnable;
0763
0764     /* Check int enable bits in base->BAUD */
0765     uint32_t tempReg = base->BAUD;
0766 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
0767     tempReg |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK);
0768     /* Clear bit 7 from mask */
0769     mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable;
0770 #endif
0771     tempReg |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK);
0772     /* Clear bit 6 from mask */
0773     mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable;
0774     base->BAUD = tempReg;
0775
0776 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
0777     /* Check int enable bits in base->FIFO */
0778     base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
0779                  (mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
0780     /* Clear bit 9 and bit 8 from mask */
0781     mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable);
0782 #endif
0783
0784     /* Set int enable bits in base->CTRL */
0785     base->CTRL |= mask;
0786 }
0787
0788 /*!
0789  * brief Disables  LPUART interrupts according to a provided mask.
0790  *
0791  * This function disables the LPUART interrupts according to a provided mask. The mask
0792  * is a logical OR of enumeration members. See ref _lpuart_interrupt_enable.
0793  * This example shows how to disable the TX empty interrupt and RX full interrupt:
0794  * code
0795  *     LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
0796  * endcode
0797  *
0798  * param base LPUART peripheral base address.
0799  * param mask The interrupts to disable. Logical OR of ref _lpuart_interrupt_enable.
0800  */
0801 void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
0802 {
0803     /* Only consider the real interrupt enable bits. */
0804     mask &= (uint32_t)kLPUART_AllInterruptEnable;
0805     /* Check int enable bits in base->BAUD */
0806     uint32_t tempReg = base->BAUD;
0807 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
0808     tempReg &= ~((mask << 8U) & LPUART_BAUD_LBKDIE_MASK);
0809     /* Clear bit 7 from mask */
0810     mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable;
0811 #endif
0812     tempReg &= ~((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK);
0813     /* Clear bit 6 from mask */
0814     mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable;
0815     base->BAUD = tempReg;
0816
0817 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
0818     /* Check int enable bits in base->FIFO */
0819     base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
0820                  ~(mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
0821     /* Clear bit 9 and bit 8 from mask */
0822     mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable);
0823 #endif
0824
0825     /* Check int enable bits in base->CTRL */
0826     base->CTRL &= ~mask;
0827 }
0828
0829 /*!
0830  * brief Gets enabled LPUART interrupts.
0831  *
0832  * This function gets the enabled LPUART interrupts. The enabled interrupts are returned
0833  * as the logical OR value of the enumerators ref _lpuart_interrupt_enable. To check
0834  * a specific interrupt enable status, compare the return value with enumerators
0835  * in ref _lpuart_interrupt_enable.
0836  * For example, to check whether the TX empty interrupt is enabled:
0837  * code
0838  *     uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);
0839  *
0840  *     if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
0841  *     {
0842  *         ...
0843  *     }
0844  * endcode
0845  *
0846  * param base LPUART peripheral base address.
0847  * return LPUART interrupt flags which are logical OR of the enumerators in ref _lpuart_interrupt_enable.
0848  */
0849 uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base)
0850 {
0851     /* Check int enable bits in base->CTRL */
0852     uint32_t temp = (uint32_t)(base->CTRL & (uint32_t)kLPUART_AllInterruptEnable);
0853
0854     /* Check int enable bits in base->BAUD */
0855     temp = (temp & ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable) | ((base->BAUD & LPUART_BAUD_RXEDGIE_MASK) >> 8U);
0856 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
0857     temp = (temp & ~(uint32_t)kLPUART_LinBreakInterruptEnable) | ((base->BAUD & LPUART_BAUD_LBKDIE_MASK) >> 8U);
0858 #endif
0859
0860 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
0861     /* Check int enable bits in base->FIFO */
0862     temp =
0863         (temp & ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable)) |
0864         (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
0865 #endif
0866
0867     return temp;
0868 }
0869
0870 /*!
0871  * brief Gets LPUART status flags.
0872  *
0873  * This function gets all LPUART status flags. The flags are returned as the logical
0874  * OR value of the enumerators ref _lpuart_flags. To check for a specific status,
0875  * compare the return value with enumerators in the ref _lpuart_flags.
0876  * For example, to check whether the TX is empty:
0877  * code
0878  *     if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
0879  *     {
0880  *         ...
0881  *     }
0882  * endcode
0883  *
0884  * param base LPUART peripheral base address.
0885  * return LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
0886  */
0887 uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
0888 {
0889     uint32_t temp;
0890     temp = base->STAT;
0891 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
0892     temp |= (base->FIFO &
0893              (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >>
0894             16U;
0895 #endif
0896     /* Only keeps the status bits */
0897     temp &= (uint32_t)kLPUART_AllFlags;
0898     return temp;
0899 }
0900
0901 /*!
0902  * brief Clears status flags with a provided mask.
0903  *
0904  * This function clears LPUART status flags with a provided mask. Automatically cleared flags
0905  * can't be cleared by this function.
0906  * Flags that can only cleared or set by hardware are:
0907  *    kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
0908  *    kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag,
0909  *    kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
0910  * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
0911  *
0912  * param base LPUART peripheral base address.
0913  * param mask the status flags to be cleared. The user can use the enumerators in the
0914  *  _lpuart_status_flag_t to do the OR operation and get the mask.
0915  * return 0 succeed, others failed.
0916  * retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but
0917  *         it is cleared automatically by hardware.
0918  * retval kStatus_Success Status in the mask are cleared.
0919  */
0920 status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
0921 {
0922     uint32_t temp;
0923     status_t status;
0924
0925     /* Only deal with the clearable flags */
0926     mask &= (uint32_t)kLPUART_AllClearFlags;
0927 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
0928     /* Status bits in FIFO register */
0929     if ((mask & ((uint32_t)kLPUART_TxFifoOverflowFlag | (uint32_t)kLPUART_RxFifoUnderflowFlag)) != 0U)
0930     {
0931         /* Get the FIFO register value and mask the rx/tx FIFO flush bits and the status bits that can be W1C in case
0932            they are written 1 accidentally. */
0933         temp = (uint32_t)base->FIFO;
0934         temp &= (uint32_t)(
0935             ~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK));
0936         temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
0937         base->FIFO = temp;
0938     }
0939 #endif
0940     /* Status bits in STAT register */
0941     /* First get the STAT register value and mask all the bits that not represent status, then OR with the status bit
0942      * that is to be W1C */
0943     temp       = (base->STAT & 0x3E000000UL) | mask;
0944     base->STAT = temp;
0945     /* If some flags still pending. */
0946     if (0U != (mask & LPUART_GetStatusFlags(base)))
0947     {
0948         status = kStatus_LPUART_FlagCannotClearManually;
0949     }
0950     else
0951     {
0952         status = kStatus_Success;
0953     }
0954
0955     return status;
0956 }
0957
0958 /*!
0959  * brief Writes to the transmitter register using a blocking method.
0960  *
0961  * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room,
0962  * and writes data to the transmitter buffer, then waits for the data to be sent out to bus.
0963  *
0964  * param base LPUART peripheral base address.
0965  * param data Start address of the data to write.
0966  * param length Size of the data to write.
0967  * retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
0968  * retval kStatus_Success Successfully wrote all data.
0969  */
0970 status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length)
0971 {
0972     assert(NULL != data);
0973
0974     const uint8_t *dataAddress = data;
0975     size_t transferSize        = length;
0976
0977 #if UART_RETRY_TIMES
0978     uint32_t waitTimes;
0979 #endif
0980
0981     while (0U != transferSize)
0982     {
0983 #if UART_RETRY_TIMES
0984         waitTimes = UART_RETRY_TIMES;
0985         while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes))
0986 #else
0987         while (0U == (base->STAT & LPUART_STAT_TDRE_MASK))
0988 #endif
0989         {
0990         }
0991 #if UART_RETRY_TIMES
0992         if (0U == waitTimes)
0993         {
0994             return kStatus_LPUART_Timeout;
0995         }
0996 #endif
0997         base->DATA = *(dataAddress);
0998         dataAddress++;
0999         transferSize--;
1000     }
1001     /* Ensure all the data in the transmit buffer are sent out to bus. */
1002 #if UART_RETRY_TIMES
1003     waitTimes = UART_RETRY_TIMES;
1004     while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes))
1005 #else
1006     while (0U == (base->STAT & LPUART_STAT_TC_MASK))
1007 #endif
1008     {
1009     }
1010 #if UART_RETRY_TIMES
1011     if (0U == waitTimes)
1012     {
1013         return kStatus_LPUART_Timeout;
1014     }
1015 #endif
1016     return kStatus_Success;
1017 }
1018
1019 /*!
1020  * brief Reads the receiver data register using a blocking method.
1021  *
1022  * This function polls the receiver register, waits for the receiver register full or receiver FIFO
1023  * has data, and reads data from the TX register.
1024  *
1025  * param base LPUART peripheral base address.
1026  * param data Start address of the buffer to store the received data.
1027  * param length Size of the buffer.
1028  * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
1029  * retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
1030  * retval kStatus_LPUART_FramingError Framing error happened while receiving data.
1031  * retval kStatus_LPUART_ParityError Parity error happened while receiving data.
1032  * retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
1033  * retval kStatus_Success Successfully received all data.
1034  */
1035 status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
1036 {
1037     assert(NULL != data);
1038
1039     status_t status = kStatus_Success;
1040     uint32_t statusFlag;
1041     uint8_t *dataAddress = data;
1042
1043 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
1044     uint32_t ctrl        = base->CTRL;
1045     bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) ||
1046                             (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U)));
1047 #endif
1048
1049 #if UART_RETRY_TIMES
1050     uint32_t waitTimes;
1051 #endif
1052
1053     while (0U != (length--))
1054     {
1055 #if UART_RETRY_TIMES
1056         waitTimes = UART_RETRY_TIMES;
1057 #endif
1058 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
1059         while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
1060 #else
1061         while (0U == (base->STAT & LPUART_STAT_RDRF_MASK))
1062 #endif
1063         {
1064 #if UART_RETRY_TIMES
1065             if (0U == --waitTimes)
1066             {
1067                 status = kStatus_LPUART_Timeout;
1068                 break;
1069             }
1070 #endif
1071             statusFlag = LPUART_GetStatusFlags(base);
1072
1073             if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag))
1074             {
1075                 status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ?
1076                               (kStatus_LPUART_RxHardwareOverrun) :
1077                               (kStatus_LPUART_FlagCannotClearManually));
1078                 /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other
1079                  * error flags*/
1080                 break;
1081             }
1082
1083             if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag))
1084             {
1085                 status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ?
1086                               (kStatus_LPUART_ParityError) :
1087                               (kStatus_LPUART_FlagCannotClearManually));
1088             }
1089
1090             if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag))
1091             {
1092                 status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ?
1093                               (kStatus_LPUART_FramingError) :
1094                               (kStatus_LPUART_FlagCannotClearManually));
1095             }
1096
1097             if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag))
1098             {
1099                 status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ?
1100                               (kStatus_LPUART_NoiseError) :
1101                               (kStatus_LPUART_FlagCannotClearManually));
1102             }
1103             if (kStatus_Success != status)
1104             {
1105                 break;
1106             }
1107         }
1108
1109         if (kStatus_Success == status)
1110         {
1111 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
1112             if (isSevenDataBits)
1113             {
1114                 *(dataAddress) = (uint8_t)(base->DATA & 0x7FU);
1115                 dataAddress++;
1116             }
1117             else
1118             {
1119                 *(dataAddress) = (uint8_t)base->DATA;
1120                 dataAddress++;
1121             }
1122 #else
1123             *(dataAddress) = (uint8_t)base->DATA;
1124             dataAddress++;
1125 #endif
1126         }
1127         else
1128         {
1129             break;
1130         }
1131     }
1132
1133     return status;
1134 }
1135
1136 /*!
1137  * brief Initializes the LPUART handle.
1138  *
1139  * This function initializes the LPUART handle, which can be used for other LPUART
1140  * transactional APIs. Usually, for a specified LPUART instance,
1141  * call this API once to get the initialized handle.
1142  *
1143  * The LPUART driver supports the "background" receiving, which means that user can set up
1144  * an RX ring buffer optionally. Data received is stored into the ring buffer even when the
1145  * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received
1146  * in the ring buffer, the user can get the received data from the ring buffer directly.
1147  * The ring buffer is disabled if passing NULL as p ringBuffer.
1148  *
1149  * param base LPUART peripheral base address.
1150  * param handle LPUART handle pointer.
1151  * param callback Callback function.
1152  * param userData User data.
1153  */
1154 void LPUART_TransferCreateHandle(LPUART_Type *base,
1155                                  lpuart_handle_t *handle,
1156                                  lpuart_transfer_callback_t callback,
1157                                  void *userData)
1158 {
1159     assert(NULL != handle);
1160
1161     uint32_t instance;
1162
1163 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
1164     uint32_t ctrl        = base->CTRL;
1165     bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) ||
1166                             (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U)));
1167 #endif
1168
1169     /* Zero the handle. */
1170     (void)memset(handle, 0, sizeof(lpuart_handle_t));
1171
1172     /* Set the TX/RX state. */
1173     handle->rxState = (uint8_t)kLPUART_RxIdle;
1174     handle->txState = (uint8_t)kLPUART_TxIdle;
1175
1176     /* Set the callback and user data. */
1177     handle->callback = callback;
1178     handle->userData = userData;
1179
1180 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
1181     /* Initial seven data bits flag */
1182     handle->isSevenDataBits = isSevenDataBits;
1183 #endif
1184
1185     /* Get instance from peripheral base address. */
1186     instance = LPUART_GetInstance(base);
1187
1188     /* Save the handle in global variables to support the double weak mechanism. */
1189     s_lpuartHandle[instance] = handle;
1190
1191     s_lpuartIsr[instance] = LPUART_TransferHandleIRQ;
1192
1193 /* Enable interrupt in NVIC. */
1194 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1195     (void)EnableIRQ(s_lpuartRxIRQ[instance]);
1196     (void)EnableIRQ(s_lpuartTxIRQ[instance]);
1197 #else
1198     (void)EnableIRQ(s_lpuartIRQ[instance]);
1199 #endif
1200 }
1201
1202 /*!
1203  * brief Sets up the RX ring buffer.
1204  *
1205  * This function sets up the RX ring buffer to a specific UART handle.
1206  *
1207  * When the RX ring buffer is used, data received is stored into the ring buffer even when
1208  * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
1209  * in the ring buffer, the user can get the received data from the ring buffer directly.
1210  *
1211  * note When using RX ring buffer, one byte is reserved for internal use. In other
1212  * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data.
1213  *
1214  * param base LPUART peripheral base address.
1215  * param handle LPUART handle pointer.
1216  * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
1217  * param ringBufferSize size of the ring buffer.
1218  */
1219 void LPUART_TransferStartRingBuffer(LPUART_Type *base,
1220                                     lpuart_handle_t *handle,
1221                                     uint8_t *ringBuffer,
1222                                     size_t ringBufferSize)
1223 {
1224     assert(NULL != handle);
1225     assert(NULL != ringBuffer);
1226
1227     /* Setup the ring buffer address */
1228     handle->rxRingBuffer     = ringBuffer;
1229     handle->rxRingBufferSize = ringBufferSize;
1230     handle->rxRingBufferHead = 0U;
1231     handle->rxRingBufferTail = 0U;
1232
1233     /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */
1234     uint32_t irqMask = DisableGlobalIRQ();
1235     /* Enable the interrupt to accept the data when user need the ring buffer. */
1236     base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK);
1237     EnableGlobalIRQ(irqMask);
1238 }
1239
1240 /*!
1241  * brief Aborts the background transfer and uninstalls the ring buffer.
1242  *
1243  * This function aborts the background transfer and uninstalls the ring buffer.
1244  *
1245  * param base LPUART peripheral base address.
1246  * param handle LPUART handle pointer.
1247  */
1248 void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle)
1249 {
1250     assert(NULL != handle);
1251
1252     if (handle->rxState == (uint8_t)kLPUART_RxIdle)
1253     {
1254         /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
1255          */
1256         uint32_t irqMask = DisableGlobalIRQ();
1257         base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK);
1258         EnableGlobalIRQ(irqMask);
1259     }
1260
1261     handle->rxRingBuffer     = NULL;
1262     handle->rxRingBufferSize = 0U;
1263     handle->rxRingBufferHead = 0U;
1264     handle->rxRingBufferTail = 0U;
1265 }
1266
1267 /*!
1268  * brief Transmits a buffer of data using the interrupt method.
1269  *
1270  * This function send data using an interrupt method. This is a non-blocking function, which
1271  * returns directly without waiting for all data written to the transmitter register. When
1272  * all data is written to the TX register in the ISR, the LPUART driver calls the callback
1273  * function and passes the ref kStatus_LPUART_TxIdle as status parameter.
1274  *
1275  * note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written
1276  * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
1277  * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
1278  *
1279  * param base LPUART peripheral base address.
1280  * param handle LPUART handle pointer.
1281  * param xfer LPUART transfer structure, see #lpuart_transfer_t.
1282  * retval kStatus_Success Successfully start the data transmission.
1283  * retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
1284  * retval kStatus_InvalidArgument Invalid argument.
1285  */
1286 status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer)
1287 {
1288     assert(NULL != handle);
1289     assert(NULL != xfer);
1290     assert(NULL != xfer->txData);
1291     assert(0U != xfer->dataSize);
1292
1293     status_t status;
1294
1295     /* Return error if current TX busy. */
1296     if ((uint8_t)kLPUART_TxBusy == handle->txState)
1297     {
1298         status = kStatus_LPUART_TxBusy;
1299     }
1300     else
1301     {
1302         handle->txData        = xfer->txData;
1303         handle->txDataSize    = xfer->dataSize;
1304         handle->txDataSizeAll = xfer->dataSize;
1305         handle->txState       = (uint8_t)kLPUART_TxBusy;
1306
1307         /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
1308          */
1309         uint32_t irqMask = DisableGlobalIRQ();
1310         /* Enable transmitter interrupt. */
1311         base->CTRL |= (uint32_t)LPUART_CTRL_TIE_MASK;
1312         EnableGlobalIRQ(irqMask);
1313
1314         status = kStatus_Success;
1315     }
1316
1317     return status;
1318 }
1319
1320 /*!
1321  * brief Aborts the interrupt-driven data transmit.
1322  *
1323  * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
1324  * how many bytes are not sent out.
1325  *
1326  * param base LPUART peripheral base address.
1327  * param handle LPUART handle pointer.
1328  */
1329 void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle)
1330 {
1331     assert(NULL != handle);
1332
1333     /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */
1334     uint32_t irqMask = DisableGlobalIRQ();
1335     base->CTRL &= ~(uint32_t)(LPUART_CTRL_TIE_MASK | LPUART_CTRL_TCIE_MASK);
1336     EnableGlobalIRQ(irqMask);
1337
1338     handle->txDataSize = 0;
1339     handle->txState    = (uint8_t)kLPUART_TxIdle;
1340 }
1341
1342 /*!
1343  * brief Gets the number of bytes that have been sent out to bus.
1344  *
1345  * This function gets the number of bytes that have been sent out to bus by an interrupt method.
1346  *
1347  * param base LPUART peripheral base address.
1348  * param handle LPUART handle pointer.
1349  * param count Send bytes count.
1350  * retval kStatus_NoTransferInProgress No send in progress.
1351  * retval kStatus_InvalidArgument Parameter is invalid.
1352  * retval kStatus_Success Get successfully through the parameter \p count;
1353  */
1354 status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
1355 {
1356     assert(NULL != handle);
1357     assert(NULL != count);
1358
1359     status_t status      = kStatus_Success;
1360     size_t tmptxDataSize = handle->txDataSize;
1361
1362     if ((uint8_t)kLPUART_TxIdle == handle->txState)
1363     {
1364         status = kStatus_NoTransferInProgress;
1365     }
1366     else
1367     {
1368 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
1369         *count = handle->txDataSizeAll - tmptxDataSize -
1370                  ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
1371 #else
1372         if ((base->STAT & (uint32_t)kLPUART_TxDataRegEmptyFlag) != 0U)
1373         {
1374             *count = handle->txDataSizeAll - tmptxDataSize;
1375         }
1376         else
1377         {
1378             *count = handle->txDataSizeAll - tmptxDataSize - 1U;
1379         }
1380 #endif
1381     }
1382
1383     return status;
1384 }
1385
1386 /*!
1387  * brief Receives a buffer of data using the interrupt method.
1388  *
1389  * This function receives data using an interrupt method. This is a non-blocking function
1390  * which returns without waiting to ensure that all data are received.
1391  * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
1392  * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
1393  * After copying, if the data in the ring buffer is not enough for read, the receive
1394  * request is saved by the LPUART driver. When the new data arrives, the receive request
1395  * is serviced first. When all data is received, the LPUART driver notifies the upper layer
1396  * through a callback function and passes a status parameter ref kStatus_UART_RxIdle.
1397  * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
1398  * The 5 bytes are copied to xfer->data, which returns with the
1399  * parameter p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
1400  * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer.
1401  * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
1402  * to receive data to xfer->data. When all data is received, the upper layer is notified.
1403  *
1404  * param base LPUART peripheral base address.
1405  * param handle LPUART handle pointer.
1406  * param xfer LPUART transfer structure, see #uart_transfer_t.
1407  * param receivedBytes Bytes received from the ring buffer directly.
1408  * retval kStatus_Success Successfully queue the transfer into the transmit queue.
1409  * retval kStatus_LPUART_RxBusy Previous receive request is not finished.
1410  * retval kStatus_InvalidArgument Invalid argument.
1411  */
1412 status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
1413                                            lpuart_handle_t *handle,
1414                                            lpuart_transfer_t *xfer,
1415                                            size_t *receivedBytes)
1416 {
1417     assert(NULL != handle);
1418     assert(NULL != xfer);
1419     assert(NULL != xfer->rxData);
1420     assert(0U != xfer->dataSize);
1421
1422     uint32_t i;
1423     status_t status;
1424     uint32_t irqMask;
1425     /* How many bytes to copy from ring buffer to user memory. */
1426     size_t bytesToCopy = 0U;
1427     /* How many bytes to receive. */
1428     size_t bytesToReceive;
1429     /* How many bytes currently have received. */
1430     size_t bytesCurrentReceived;
1431
1432     /* How to get data:
1433        1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
1434           to lpuart handle, enable interrupt to store received data to xfer->data. When
1435           all data received, trigger callback.
1436        2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
1437           If there are enough data in ring buffer, copy them to xfer->data and return.
1438           If there are not enough data in ring buffer, copy all of them to xfer->data,
1439           save the xfer->data remained empty space to lpuart handle, receive data
1440           to this empty space and trigger callback when finished. */
1441
1442     if ((uint8_t)kLPUART_RxBusy == handle->rxState)
1443     {
1444         status = kStatus_LPUART_RxBusy;
1445     }
1446     else
1447     {
1448         bytesToReceive       = xfer->dataSize;
1449         bytesCurrentReceived = 0;
1450
1451         /* If RX ring buffer is used. */
1452         if (NULL != handle->rxRingBuffer)
1453         {
1454             /* Disable and re-enable the global interrupt to protect the interrupt enable register during
1455              * read-modify-wrte. */
1456             irqMask = DisableGlobalIRQ();
1457             /* Disable LPUART RX IRQ, protect ring buffer. */
1458             base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK);
1459             EnableGlobalIRQ(irqMask);
1460
1461             /* How many bytes in RX ring buffer currently. */
1462             bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle);
1463
1464             if (0U != bytesToCopy)
1465             {
1466                 bytesToCopy = MIN(bytesToReceive, bytesToCopy);
1467
1468                 bytesToReceive -= bytesToCopy;
1469
1470                 /* Copy data from ring buffer to user memory. */
1471                 for (i = 0U; i < bytesToCopy; i++)
1472                 {
1473                     xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail];
1474                     bytesCurrentReceived++;
1475
1476                     /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
1477                     if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize)
1478                     {
1479                         handle->rxRingBufferTail = 0U;
1480                     }
1481                     else
1482                     {
1483                         handle->rxRingBufferTail++;
1484                     }
1485                 }
1486             }
1487
1488             /* If ring buffer does not have enough data, still need to read more data. */
1489             if (0U != bytesToReceive)
1490             {
1491                 /* No data in ring buffer, save the request to LPUART handle. */
1492                 handle->rxData        = &xfer->rxData[bytesCurrentReceived];
1493                 handle->rxDataSize    = bytesToReceive;
1494                 handle->rxDataSizeAll = xfer->dataSize;
1495                 handle->rxState       = (uint8_t)kLPUART_RxBusy;
1496             }
1497
1498             /* Disable and re-enable the global interrupt to protect the interrupt enable register during
1499              * read-modify-wrte. */
1500             irqMask = DisableGlobalIRQ();
1501             /* Re-enable LPUART RX IRQ. */
1502             base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK);
1503             EnableGlobalIRQ(irqMask);
1504
1505             /* Call user callback since all data are received. */
1506             if (0U == bytesToReceive)
1507             {
1508                 if (NULL != handle->callback)
1509                 {
1510                     handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
1511                 }
1512             }
1513         }
1514         /* Ring buffer not used. */
1515         else
1516         {
1517             handle->rxData        = &xfer->rxData[bytesCurrentReceived];
1518             handle->rxDataSize    = bytesToReceive;
1519             handle->rxDataSizeAll = bytesToReceive;
1520             handle->rxState       = (uint8_t)kLPUART_RxBusy;
1521
1522             /* Disable and re-enable the global interrupt to protect the interrupt enable register during
1523              * read-modify-wrte. */
1524             irqMask = DisableGlobalIRQ();
1525             /* Enable RX interrupt. */
1526             base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK);
1527             EnableGlobalIRQ(irqMask);
1528         }
1529
1530         /* Return the how many bytes have read. */
1531         if (NULL != receivedBytes)
1532         {
1533             *receivedBytes = bytesCurrentReceived;
1534         }
1535
1536         status = kStatus_Success;
1537     }
1538
1539     return status;
1540 }
1541
1542 /*!
1543  * brief Aborts the interrupt-driven data receiving.
1544  *
1545  * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
1546  * how many bytes not received yet.
1547  *
1548  * param base LPUART peripheral base address.
1549  * param handle LPUART handle pointer.
1550  */
1551 void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle)
1552 {
1553     assert(NULL != handle);
1554
1555     /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
1556     if (NULL == handle->rxRingBuffer)
1557     {
1558         /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
1559          */
1560         uint32_t irqMask = DisableGlobalIRQ();
1561         /* Disable RX interrupt. */
1562         base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK);
1563         EnableGlobalIRQ(irqMask);
1564     }
1565
1566     handle->rxDataSize = 0U;
1567     handle->rxState    = (uint8_t)kLPUART_RxIdle;
1568 }
1569
1570 /*!
1571  * brief Gets the number of bytes that have been received.
1572  *
1573  * This function gets the number of bytes that have been received.
1574  *
1575  * param base LPUART peripheral base address.
1576  * param handle LPUART handle pointer.
1577  * param count Receive bytes count.
1578  * retval kStatus_NoTransferInProgress No receive in progress.
1579  * retval kStatus_InvalidArgument Parameter is invalid.
1580  * retval kStatus_Success Get successfully through the parameter \p count;
1581  */
1582 status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count)
1583 {
1584     assert(NULL != handle);
1585     assert(NULL != count);
1586
1587     status_t status      = kStatus_Success;
1588     size_t tmprxDataSize = handle->rxDataSize;
1589
1590     if ((uint8_t)kLPUART_RxIdle == handle->rxState)
1591     {
1592         status = kStatus_NoTransferInProgress;
1593     }
1594     else
1595     {
1596         *count = handle->rxDataSizeAll - tmprxDataSize;
1597     }
1598
1599     return status;
1600 }
1601
1602 static void LPUART_TransferHandleIDLEReady(LPUART_Type *base, lpuart_handle_t *handle)
1603 {
1604     uint32_t irqMask;
1605 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
1606     uint8_t count;
1607     uint8_t tempCount;
1608     count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
1609
1610     while ((0U != handle->rxDataSize) && (0U != count))
1611     {
1612         tempCount = (uint8_t)MIN(handle->rxDataSize, count);
1613
1614         /* Using non block API to read the data from the registers. */
1615         LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
1616         handle->rxData = &handle->rxData[tempCount];
1617         handle->rxDataSize -= tempCount;
1618         count -= tempCount;
1619
1620         /* If rxDataSize is 0, invoke rx idle callback.*/
1621         if (0U == (handle->rxDataSize))
1622         {
1623             handle->rxState = (uint8_t)kLPUART_RxIdle;
1624
1625             if (NULL != handle->callback)
1626             {
1627                 handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
1628             }
1629         }
1630     }
1631 #endif
1632     /* Clear IDLE flag.*/
1633     base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_IDLE_MASK);
1634
1635     /* If rxDataSize is 0, disable rx ready, overrun and idle line interrupt.*/
1636     if (0U == handle->rxDataSize)
1637     {
1638         /* Disable and re-enable the global interrupt to protect the interrupt enable register during
1639          * read-modify-wrte. */
1640         irqMask = DisableGlobalIRQ();
1641         base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK);
1642         EnableGlobalIRQ(irqMask);
1643     }
1644     /* Invoke callback if callback is not NULL and rxDataSize is not 0. */
1645     else if (NULL != handle->callback)
1646     {
1647         handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData);
1648     }
1649     else
1650     {
1651         /* Avoid MISRA 15.7 */
1652     }
1653 }
1654
1655 static void LPUART_TransferHandleReceiveDataFull(LPUART_Type *base, lpuart_handle_t *handle)
1656 {
1657     uint8_t count;
1658     uint8_t tempCount;
1659     uint16_t tpmRxRingBufferHead;
1660     uint32_t tpmData;
1661     uint32_t irqMask;
1662
1663     /* Get the size that can be stored into buffer for this interrupt. */
1664 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
1665     count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT));
1666 #else
1667     count = 1;
1668 #endif
1669
1670     /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
1671     while ((0U != handle->rxDataSize) && (0U != count))
1672     {
1673 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
1674         tempCount = (uint8_t)MIN(handle->rxDataSize, count);
1675 #else
1676         tempCount = 1;
1677 #endif
1678
1679         /* Using non block API to read the data from the registers. */
1680         LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
1681         handle->rxData = &handle->rxData[tempCount];
1682         handle->rxDataSize -= tempCount;
1683         count -= tempCount;
1684
1685         /* If all the data required for upper layer is ready, trigger callback. */
1686         if (0U == handle->rxDataSize)
1687         {
1688             handle->rxState = (uint8_t)kLPUART_RxIdle;
1689
1690             if (NULL != handle->callback)
1691             {
1692                 handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData);
1693             }
1694         }
1695     }
1696
1697     /* If use RX ring buffer, receive data to ring buffer. */
1698     if (NULL != handle->rxRingBuffer)
1699     {
1700         while (0U != count--)
1701         {
1702             /* If RX ring buffer is full, trigger callback to notify over run. */
1703             if (LPUART_TransferIsRxRingBufferFull(base, handle))
1704             {
1705                 if (NULL != handle->callback)
1706                 {
1707                     handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData);
1708                 }
1709             }
1710
1711             /* If ring buffer is still full after callback function, the oldest data is overridden. */
1712             if (LPUART_TransferIsRxRingBufferFull(base, handle))
1713             {
1714                 /* Increase handle->rxRingBufferTail to make room for new data. */
1715                 if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize)
1716                 {
1717                     handle->rxRingBufferTail = 0U;
1718                 }
1719                 else
1720                 {
1721                     handle->rxRingBufferTail++;
1722                 }
1723             }
1724
1725             /* Read data. */
1726             tpmRxRingBufferHead = handle->rxRingBufferHead;
1727             tpmData             = base->DATA;
1728 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
1729             if (handle->isSevenDataBits)
1730             {
1731                 handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)(tpmData & 0x7FU);
1732             }
1733             else
1734             {
1735                 handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
1736             }
1737 #else
1738             handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
1739 #endif
1740
1741             /* Increase handle->rxRingBufferHead. */
1742             if (((uint32_t)handle->rxRingBufferHead + 1U) == handle->rxRingBufferSize)
1743             {
1744                 handle->rxRingBufferHead = 0U;
1745             }
1746             else
1747             {
1748                 handle->rxRingBufferHead++;
1749             }
1750         }
1751     }
1752     /* If no receive requst pending, stop RX interrupt. */
1753     else if (0U == handle->rxDataSize)
1754     {
1755         /* Disable and re-enable the global interrupt to protect the interrupt enable register during
1756          * read-modify-wrte. */
1757         irqMask = DisableGlobalIRQ();
1758         base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK | LPUART_CTRL_ILIE_MASK);
1759         EnableGlobalIRQ(irqMask);
1760     }
1761     else
1762     {
1763         /* Avoid MISRA C-2012 15.7 voiation */
1764         return;
1765     }
1766 }
1767
1768 static void LPUART_TransferHandleSendDataEmpty(LPUART_Type *base, lpuart_handle_t *handle)
1769 {
1770     uint8_t count;
1771     uint8_t tempCount;
1772     uint32_t irqMask;
1773 /* Get the bytes that available at this moment. */
1774 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
1775     count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) -
1776             (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT);
1777 #else
1778     count = 1;
1779 #endif
1780
1781     while ((0U != handle->txDataSize) && (0U != count))
1782     {
1783 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
1784         tempCount = (uint8_t)MIN(handle->txDataSize, count);
1785 #else
1786         tempCount = 1;
1787 #endif
1788
1789         /* Using non block API to write the data to the registers. */
1790         LPUART_WriteNonBlocking(base, handle->txData, tempCount);
1791         handle->txData = &handle->txData[tempCount];
1792         handle->txDataSize -= tempCount;
1793         count -= tempCount;
1794
1795         /* If all the data are written to data register, notify user with the callback, then TX finished. */
1796         if (0U == handle->txDataSize)
1797         {
1798             /* Disable and re-enable the global interrupt to protect the interrupt enable register during
1799              * read-modify-wrte. */
1800             irqMask = DisableGlobalIRQ();
1801             /* Disable TX register empty interrupt and enable transmission completion interrupt. */
1802             base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK) | LPUART_CTRL_TCIE_MASK;
1803             EnableGlobalIRQ(irqMask);
1804         }
1805     }
1806 }
1807
1808 static void LPUART_TransferHandleTransmissionComplete(LPUART_Type *base, lpuart_handle_t *handle)
1809 {
1810     uint32_t irqMask;
1811     /* Set txState to idle only when all data has been sent out to bus. */
1812     handle->txState = (uint8_t)kLPUART_TxIdle;
1813
1814     /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte.
1815      */
1816     irqMask = DisableGlobalIRQ();
1817     /* Disable transmission complete interrupt. */
1818     base->CTRL &= ~(uint32_t)LPUART_CTRL_TCIE_MASK;
1819     EnableGlobalIRQ(irqMask);
1820
1821     /* Trigger callback. */
1822     if (NULL != handle->callback)
1823     {
1824         handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData);
1825     }
1826 }
1827
1828 /*!
1829  * brief LPUART IRQ handle function.
1830  *
1831  * This function handles the LPUART transmit and receive IRQ request.
1832  *
1833  * param base LPUART peripheral base address.
1834  * param irqHandle LPUART handle pointer.
1835  */
1836 void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle)
1837 {
1838     assert(NULL != irqHandle);
1839
1840     uint32_t status            = LPUART_GetStatusFlags(base);
1841     uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(base);
1842
1843     lpuart_handle_t *handle = (lpuart_handle_t *)irqHandle;
1844
1845     /* If RX overrun. */
1846     if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status))
1847     {
1848         /* Clear overrun flag, otherwise the RX does not work. */
1849         base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
1850
1851         /* Trigger callback. */
1852         if (NULL != (handle->callback))
1853         {
1854             handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData);
1855         }
1856     }
1857
1858     /* If IDLE flag is set and the IDLE interrupt is enabled. */
1859     if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) &&
1860         (0U != ((uint32_t)kLPUART_IdleLineInterruptEnable & enabledInterrupts)))
1861     {
1862         LPUART_TransferHandleIDLEReady(base, handle);
1863     }
1864     /* Receive data register full */
1865     if ((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) &&
1866         (0U != ((uint32_t)kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts)))
1867     {
1868         LPUART_TransferHandleReceiveDataFull(base, handle);
1869     }
1870
1871     /* Send data register empty and the interrupt is enabled. */
1872     if ((0U != ((uint32_t)kLPUART_TxDataRegEmptyFlag & status)) &&
1873         (0U != ((uint32_t)kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)))
1874     {
1875         LPUART_TransferHandleSendDataEmpty(base, handle);
1876     }
1877
1878     /* Transmission complete and the interrupt is enabled. */
1879     if ((0U != ((uint32_t)kLPUART_TransmissionCompleteFlag & status)) &&
1880         (0U != ((uint32_t)kLPUART_TransmissionCompleteInterruptEnable & enabledInterrupts)))
1881     {
1882         LPUART_TransferHandleTransmissionComplete(base, handle);
1883     }
1884 }
1885
1886 /*!
1887  * brief LPUART Error IRQ handle function.
1888  *
1889  * This function handles the LPUART error IRQ request.
1890  *
1891  * param base LPUART peripheral base address.
1892  * param irqHandle LPUART handle pointer.
1893  */
1894 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle)
1895 {
1896     /* To be implemented by User. */
1897 }
1898 #if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1
1899 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1900 void LPUART0_LPUART1_RX_DriverIRQHandler(void);
1901 void LPUART0_LPUART1_RX_DriverIRQHandler(void)
1902 {
1903     /* If handle is registered, treat the transfer function is enabled. */
1904     if (NULL != s_lpuartHandle[0])
1905     {
1906         s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]);
1907     }
1908     if (NULL != s_lpuartHandle[1])
1909     {
1910         s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]);
1911     }
1912     SDK_ISR_EXIT_BARRIER;
1913 }
1914 void LPUART0_LPUART1_TX_DriverIRQHandler(void);
1915 void LPUART0_LPUART1_TX_DriverIRQHandler(void)
1916 {
1917     /* If handle is registered, treat the transfer function is enabled. */
1918     if (NULL != s_lpuartHandle[0])
1919     {
1920         s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]);
1921     }
1922     if (NULL != s_lpuartHandle[1])
1923     {
1924         s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]);
1925     }
1926     SDK_ISR_EXIT_BARRIER;
1927 }
1928 #else
1929 void LPUART0_LPUART1_DriverIRQHandler(void);
1930 void LPUART0_LPUART1_DriverIRQHandler(void)
1931 {
1932     /* If handle is registered, treat the transfer function is enabled. */
1933     if (NULL != s_lpuartHandle[0])
1934     {
1935         s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]);
1936     }
1937     if (NULL != s_lpuartHandle[1])
1938     {
1939         s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]);
1940     }
1941     SDK_ISR_EXIT_BARRIER;
1942 }
1943 #endif
1944 #endif
1945
1946 #if defined(LPUART0)
1947 #if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
1948 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1949 void LPUART0_TX_DriverIRQHandler(void);
1950 void LPUART0_TX_DriverIRQHandler(void)
1951 {
1952     s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]);
1953     SDK_ISR_EXIT_BARRIER;
1954 }
1955 void LPUART0_RX_DriverIRQHandler(void);
1956 void LPUART0_RX_DriverIRQHandler(void)
1957 {
1958     s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]);
1959     SDK_ISR_EXIT_BARRIER;
1960 }
1961 #else
1962 void LPUART0_DriverIRQHandler(void);
1963 void LPUART0_DriverIRQHandler(void)
1964 {
1965     s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]);
1966     SDK_ISR_EXIT_BARRIER;
1967 }
1968 #endif
1969 #endif
1970 #endif
1971
1972 #if defined(LPUART1)
1973 #if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1)
1974 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
1975 void LPUART1_TX_DriverIRQHandler(void);
1976 void LPUART1_TX_DriverIRQHandler(void)
1977 {
1978     s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]);
1979     SDK_ISR_EXIT_BARRIER;
1980 }
1981 void LPUART1_RX_DriverIRQHandler(void);
1982 void LPUART1_RX_DriverIRQHandler(void)
1983 {
1984     s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]);
1985     SDK_ISR_EXIT_BARRIER;
1986 }
1987 #else
1988 void LPUART1_DriverIRQHandler(void);
1989 void LPUART1_DriverIRQHandler(void)
1990 {
1991     s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]);
1992     SDK_ISR_EXIT_BARRIER;
1993 }
1994 #endif
1995 #endif
1996 #endif
1997
1998 #if defined(LPUART2)
1999 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
2000 void LPUART2_TX_DriverIRQHandler(void);
2001 void LPUART2_TX_DriverIRQHandler(void)
2002 {
2003     s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]);
2004     SDK_ISR_EXIT_BARRIER;
2005 }
2006 void LPUART2_RX_DriverIRQHandler(void);
2007 void LPUART2_RX_DriverIRQHandler(void)
2008 {
2009     s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]);
2010     SDK_ISR_EXIT_BARRIER;
2011 }
2012 #else
2013 void LPUART2_DriverIRQHandler(void);
2014 void LPUART2_DriverIRQHandler(void)
2015 {
2016     s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]);
2017     SDK_ISR_EXIT_BARRIER;
2018 }
2019 #endif
2020 #endif
2021
2022 #if defined(LPUART3)
2023 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
2024 void LPUART3_TX_DriverIRQHandler(void);
2025 void LPUART3_TX_DriverIRQHandler(void)
2026 {
2027     s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]);
2028     SDK_ISR_EXIT_BARRIER;
2029 }
2030 void LPUART3_RX_DriverIRQHandler(void);
2031 void LPUART3_RX_DriverIRQHandler(void)
2032 {
2033     s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]);
2034     SDK_ISR_EXIT_BARRIER;
2035 }
2036 #else
2037 void LPUART3_DriverIRQHandler(void);
2038 void LPUART3_DriverIRQHandler(void)
2039 {
2040     s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]);
2041     SDK_ISR_EXIT_BARRIER;
2042 }
2043 #endif
2044 #endif
2045
2046 #if defined(LPUART4)
2047 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
2048 void LPUART4_TX_DriverIRQHandler(void);
2049 void LPUART4_TX_DriverIRQHandler(void)
2050 {
2051     s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]);
2052     SDK_ISR_EXIT_BARRIER;
2053 }
2054 void LPUART4_RX_DriverIRQHandler(void);
2055 void LPUART4_RX_DriverIRQHandler(void)
2056 {
2057     s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]);
2058     SDK_ISR_EXIT_BARRIER;
2059 }
2060 #else
2061 void LPUART4_DriverIRQHandler(void);
2062 void LPUART4_DriverIRQHandler(void)
2063 {
2064     s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]);
2065     SDK_ISR_EXIT_BARRIER;
2066 }
2067 #endif
2068 #endif
2069
2070 #if defined(LPUART5)
2071 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
2072 void LPUART5_TX_DriverIRQHandler(void);
2073 void LPUART5_TX_DriverIRQHandler(void)
2074 {
2075     s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]);
2076     SDK_ISR_EXIT_BARRIER;
2077 }
2078 void LPUART5_RX_DriverIRQHandler(void);
2079 void LPUART5_RX_DriverIRQHandler(void)
2080 {
2081     s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]);
2082     SDK_ISR_EXIT_BARRIER;
2083 }
2084 #else
2085 void LPUART5_DriverIRQHandler(void);
2086 void LPUART5_DriverIRQHandler(void)
2087 {
2088     s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]);
2089     SDK_ISR_EXIT_BARRIER;
2090 }
2091 #endif
2092 #endif
2093
2094 #if defined(LPUART6)
2095 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
2096 void LPUART6_TX_DriverIRQHandler(void);
2097 void LPUART6_TX_DriverIRQHandler(void)
2098 {
2099     s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]);
2100     SDK_ISR_EXIT_BARRIER;
2101 }
2102 void LPUART6_RX_DriverIRQHandler(void);
2103 void LPUART6_RX_DriverIRQHandler(void)
2104 {
2105     s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]);
2106     SDK_ISR_EXIT_BARRIER;
2107 }
2108 #else
2109 void LPUART6_DriverIRQHandler(void);
2110 void LPUART6_DriverIRQHandler(void)
2111 {
2112     s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]);
2113     SDK_ISR_EXIT_BARRIER;
2114 }
2115 #endif
2116 #endif
2117
2118 #if defined(LPUART7)
2119 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
2120 void LPUART7_TX_DriverIRQHandler(void);
2121 void LPUART7_TX_DriverIRQHandler(void)
2122 {
2123     s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]);
2124     SDK_ISR_EXIT_BARRIER;
2125 }
2126 void LPUART7_RX_DriverIRQHandler(void);
2127 void LPUART7_RX_DriverIRQHandler(void)
2128 {
2129     s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]);
2130     SDK_ISR_EXIT_BARRIER;
2131 }
2132 #else
2133 void LPUART7_DriverIRQHandler(void);
2134 void LPUART7_DriverIRQHandler(void)
2135 {
2136     s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]);
2137     SDK_ISR_EXIT_BARRIER;
2138 }
2139 #endif
2140 #endif
2141
2142 #if defined(LPUART8)
2143 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
2144 void LPUART8_TX_DriverIRQHandler(void);
2145 void LPUART8_TX_DriverIRQHandler(void)
2146 {
2147     s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]);
2148     SDK_ISR_EXIT_BARRIER;
2149 }
2150 void LPUART8_RX_DriverIRQHandler(void);
2151 void LPUART8_RX_DriverIRQHandler(void)
2152 {
2153     s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]);
2154     SDK_ISR_EXIT_BARRIER;
2155 }
2156 #else
2157 void LPUART8_DriverIRQHandler(void);
2158 void LPUART8_DriverIRQHandler(void)
2159 {
2160     s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]);
2161     SDK_ISR_EXIT_BARRIER;
2162 }
2163 #endif
2164 #endif
2165
2166 #if defined(LPUART9)
2167 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
2168 void LPUART9_TX_DriverIRQHandler(void);
2169 void LPUART9_TX_DriverIRQHandler(void)
2170 {
2171     s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]);
2172     SDK_ISR_EXIT_BARRIER;
2173 }
2174 void LPUART9_RX_DriverIRQHandler(void);
2175 void LPUART9_RX_DriverIRQHandler(void)
2176 {
2177     s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]);
2178     SDK_ISR_EXIT_BARRIER;
2179 }
2180 #else
2181 void LPUART9_DriverIRQHandler(void);
2182 void LPUART9_DriverIRQHandler(void)
2183 {
2184     s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]);
2185     SDK_ISR_EXIT_BARRIER;
2186 }
2187 #endif
2188 #endif
2189
2190 #if defined(LPUART10)
2191 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
2192 void LPUART10_TX_DriverIRQHandler(void);
2193 void LPUART10_TX_DriverIRQHandler(void)
2194 {
2195     s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]);
2196     SDK_ISR_EXIT_BARRIER;
2197 }
2198 void LPUART10_RX_DriverIRQHandler(void);
2199 void LPUART10_RX_DriverIRQHandler(void)
2200 {
2201     s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]);
2202     SDK_ISR_EXIT_BARRIER;
2203 }
2204 #else
2205 void LPUART10_DriverIRQHandler(void);
2206 void LPUART10_DriverIRQHandler(void)
2207 {
2208     s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]);
2209     SDK_ISR_EXIT_BARRIER;
2210 }
2211 #endif
2212 #endif
2213
2214 #if defined(LPUART11)
2215 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
2216 void LPUART11_TX_DriverIRQHandler(void);
2217 void LPUART11_TX_DriverIRQHandler(void)
2218 {
2219     s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]);
2220     SDK_ISR_EXIT_BARRIER;
2221 }
2222 void LPUART11_RX_DriverIRQHandler(void);
2223 void LPUART11_RX_DriverIRQHandler(void)
2224 {
2225     s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]);
2226     SDK_ISR_EXIT_BARRIER;
2227 }
2228 #else
2229 void LPUART11_DriverIRQHandler(void);
2230 void LPUART11_DriverIRQHandler(void)
2231 {
2232     s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]);
2233     SDK_ISR_EXIT_BARRIER;
2234 }
2235 #endif
2236 #endif
2237
2238 #if defined(LPUART12)
2239 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ
2240 void LPUART12_TX_DriverIRQHandler(void);
2241 void LPUART12_TX_DriverIRQHandler(void)
2242 {
2243     s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]);
2244     SDK_ISR_EXIT_BARRIER;
2245 }
2246 void LPUART12_RX_DriverIRQHandler(void);
2247 void LPUART12_RX_DriverIRQHandler(void)
2248 {
2249     s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]);
2250     SDK_ISR_EXIT_BARRIER;
2251 }
2252 #else
2253 void LPUART12_DriverIRQHandler(void);
2254 void LPUART12_DriverIRQHandler(void)
2255 {
2256     s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]);
2257     SDK_ISR_EXIT_BARRIER;
2258 }
2259 #endif
2260 #endif
2261
2262 #if defined(CM4_0__LPUART)
2263 void M4_0_LPUART_DriverIRQHandler(void);
2264 void M4_0_LPUART_DriverIRQHandler(void)
2265 {
2266     s_lpuartIsr[LPUART_GetInstance(CM4_0__LPUART)](CM4_0__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0__LPUART)]);
2267     SDK_ISR_EXIT_BARRIER;
2268 }
2269 #endif
2270
2271 #if defined(CM4_1__LPUART)
2272 void M4_1_LPUART_DriverIRQHandler(void);
2273 void M4_1_LPUART_DriverIRQHandler(void)
2274 {
2275     s_lpuartIsr[LPUART_GetInstance(CM4_1__LPUART)](CM4_1__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1__LPUART)]);
2276     SDK_ISR_EXIT_BARRIER;
2277 }
2278 #endif
2279
2280 #if defined(CM4__LPUART)
2281 void M4_LPUART_DriverIRQHandler(void);
2282 void M4_LPUART_DriverIRQHandler(void)
2283 {
2284     s_lpuartIsr[LPUART_GetInstance(CM4__LPUART)](CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]);
2285     SDK_ISR_EXIT_BARRIER;
2286 }
2287 #endif
2288
2289 #if defined(DMA__LPUART0)
2290 void DMA_UART0_INT_DriverIRQHandler(void);
2291 void DMA_UART0_INT_DriverIRQHandler(void)
2292 {
2293     s_lpuartIsr[LPUART_GetInstance(DMA__LPUART0)](DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]);
2294     SDK_ISR_EXIT_BARRIER;
2295 }
2296 #endif
2297
2298 #if defined(DMA__LPUART1)
2299 void DMA_UART1_INT_DriverIRQHandler(void);
2300 void DMA_UART1_INT_DriverIRQHandler(void)
2301 {
2302     s_lpuartIsr[LPUART_GetInstance(DMA__LPUART1)](DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]);
2303     SDK_ISR_EXIT_BARRIER;
2304 }
2305 #endif
2306
2307 #if defined(DMA__LPUART2)
2308 void DMA_UART2_INT_DriverIRQHandler(void);
2309 void DMA_UART2_INT_DriverIRQHandler(void)
2310 {
2311     s_lpuartIsr[LPUART_GetInstance(DMA__LPUART2)](DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]);
2312     SDK_ISR_EXIT_BARRIER;
2313 }
2314 #endif
2315
2316 #if defined(DMA__LPUART3)
2317 void DMA_UART3_INT_DriverIRQHandler(void);
2318 void DMA_UART3_INT_DriverIRQHandler(void)
2319 {
2320     s_lpuartIsr[LPUART_GetInstance(DMA__LPUART3)](DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]);
2321     SDK_ISR_EXIT_BARRIER;
2322 }
2323 #endif
2324
2325 #if defined(DMA__LPUART4)
2326 void DMA_UART4_INT_DriverIRQHandler(void);
2327 void DMA_UART4_INT_DriverIRQHandler(void)
2328 {
2329     s_lpuartIsr[LPUART_GetInstance(DMA__LPUART4)](DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]);
2330     SDK_ISR_EXIT_BARRIER;
2331 }
2332 #endif
2333
2334 #if defined(ADMA__LPUART0)
2335 void ADMA_UART0_INT_DriverIRQHandler(void);
2336 void ADMA_UART0_INT_DriverIRQHandler(void)
2337 {
2338     s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART0)](ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]);
2339     SDK_ISR_EXIT_BARRIER;
2340 }
2341 #endif
2342
2343 #if defined(ADMA__LPUART1)
2344 void ADMA_UART1_INT_DriverIRQHandler(void);
2345 void ADMA_UART1_INT_DriverIRQHandler(void)
2346 {
2347     s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART1)](ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]);
2348     SDK_ISR_EXIT_BARRIER;
2349 }
2350 #endif
2351
2352 #if defined(ADMA__LPUART2)
2353 void ADMA_UART2_INT_DriverIRQHandler(void);
2354 void ADMA_UART2_INT_DriverIRQHandler(void)
2355 {
2356     s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART2)](ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]);
2357     SDK_ISR_EXIT_BARRIER;
2358 }
2359 #endif
2360
2361 #if defined(ADMA__LPUART3)
2362 void ADMA_UART3_INT_DriverIRQHandler(void);
2363 void ADMA_UART3_INT_DriverIRQHandler(void)
2364 {
2365     s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART3)](ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]);
2366     SDK_ISR_EXIT_BARRIER;
2367 }
2368 #endif