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0001 /* 0002 * Copyright (c) 2015, Freescale Semiconductor, Inc. 0003 * Copyright 2016-2022 NXP 0004 * All rights reserved. 0005 * 0006 * SPDX-License-Identifier: BSD-3-Clause 0007 */ 0008 #ifndef _FSL_LPSPI_H_ 0009 #define _FSL_LPSPI_H_ 0010 0011 #include "fsl_common.h" 0012 0013 /*! 0014 * @addtogroup lpspi_driver 0015 * @{ 0016 */ 0017 0018 /********************************************************************************************************************** 0019 * Definitions 0020 *********************************************************************************************************************/ 0021 0022 /*! @name Driver version */ 0023 /*@{*/ 0024 /*! @brief LPSPI driver version. */ 0025 #define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) 0026 /*@}*/ 0027 0028 #ifndef LPSPI_DUMMY_DATA 0029 /*! @brief LPSPI dummy data if no Tx data.*/ 0030 #define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */ 0031 #endif 0032 0033 /*! @brief Retry times for waiting flag. */ 0034 #ifndef SPI_RETRY_TIMES 0035 #define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ 0036 #endif 0037 0038 /*! @brief Global variable for dummy data value setting. */ 0039 extern volatile uint8_t g_lpspiDummyData[]; 0040 0041 /*! @brief Status for the LPSPI driver.*/ 0042 enum 0043 { 0044 kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/ 0045 kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */ 0046 kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/ 0047 kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3), /*!< LPSPI transfer out Of range. */ 0048 kStatus_LPSPI_Timeout = MAKE_STATUS(kStatusGroup_LPSPI, 4) /*!< LPSPI timeout polling status flags. */ 0049 }; 0050 0051 /*! @brief LPSPI status flags in SPIx_SR register.*/ 0052 enum _lpspi_flags 0053 { 0054 kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */ 0055 kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */ 0056 kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */ 0057 kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */ 0058 kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */ 0059 kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */ 0060 kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */ 0061 kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */ 0062 kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */ 0063 kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK | 0064 LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK | 0065 LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */ 0066 }; 0067 0068 /*! @brief LPSPI interrupt source.*/ 0069 enum _lpspi_interrupt_enable 0070 { 0071 kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */ 0072 kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */ 0073 kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */ 0074 kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */ 0075 kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */ 0076 kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/ 0077 kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */ 0078 kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */ 0079 kLPSPI_AllInterruptEnable = 0080 (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK | 0081 LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/ 0082 }; 0083 0084 /*! @brief LPSPI DMA source.*/ 0085 enum _lpspi_dma_enable 0086 { 0087 kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */ 0088 kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK /*!< Receive data DMA enable */ 0089 }; 0090 0091 /*! @brief LPSPI master or slave mode configuration.*/ 0092 typedef enum _lpspi_master_slave_mode 0093 { 0094 kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/ 0095 kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/ 0096 } lpspi_master_slave_mode_t; 0097 0098 /*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/ 0099 typedef enum _lpspi_which_pcs_config 0100 { 0101 kLPSPI_Pcs0 = 0U, /*!< PCS[0] */ 0102 kLPSPI_Pcs1 = 1U, /*!< PCS[1] */ 0103 kLPSPI_Pcs2 = 2U, /*!< PCS[2] */ 0104 kLPSPI_Pcs3 = 3U /*!< PCS[3] */ 0105 } lpspi_which_pcs_t; 0106 0107 /*! @brief LPSPI Peripheral Chip Select (PCS) Polarity configuration.*/ 0108 typedef enum _lpspi_pcs_polarity_config 0109 { 0110 kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */ 0111 kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */ 0112 } lpspi_pcs_polarity_config_t; 0113 0114 /*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/ 0115 enum _lpspi_pcs_polarity 0116 { 0117 kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ 0118 kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ 0119 kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ 0120 kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ 0121 kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ 0122 }; 0123 0124 /*! @brief LPSPI clock polarity configuration.*/ 0125 typedef enum _lpspi_clock_polarity 0126 { 0127 kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/ 0128 kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/ 0129 } lpspi_clock_polarity_t; 0130 0131 /*! @brief LPSPI clock phase configuration.*/ 0132 typedef enum _lpspi_clock_phase 0133 { 0134 kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the 0135 following edge.*/ 0136 kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the 0137 following edge.*/ 0138 } lpspi_clock_phase_t; 0139 0140 /*! @brief LPSPI data shifter direction options.*/ 0141 typedef enum _lpspi_shift_direction 0142 { 0143 kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ 0144 kLPSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/ 0145 } lpspi_shift_direction_t; 0146 0147 /*! @brief LPSPI Host Request select configuration. */ 0148 typedef enum _lpspi_host_request_select 0149 { 0150 kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */ 0151 kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */ 0152 } lpspi_host_request_select_t; 0153 0154 /*! @brief LPSPI Match configuration options. */ 0155 typedef enum _lpspi_match_config 0156 { 0157 kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */ 0158 kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */ 0159 kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */ 0160 kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */ 0161 kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */ 0162 kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */ 0163 kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */ 0164 } lpspi_match_config_t; 0165 0166 /*! @brief LPSPI pin (SDO and SDI) configuration. */ 0167 typedef enum _lpspi_pin_config 0168 { 0169 kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */ 0170 kLPSPI_SdiInSdiOut = 1U, /*!< LPSPI SDI input, SDI output. */ 0171 kLPSPI_SdoInSdoOut = 2U, /*!< LPSPI SDO input, SDO output. */ 0172 kLPSPI_SdoInSdiOut = 3U /*!< LPSPI SDO input, SDI output. */ 0173 } lpspi_pin_config_t; 0174 0175 /*! @brief LPSPI data output configuration. */ 0176 typedef enum _lpspi_data_out_config 0177 { 0178 kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */ 0179 kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */ 0180 } lpspi_data_out_config_t; 0181 0182 /*! @brief LPSPI transfer width configuration. */ 0183 typedef enum _lpspi_transfer_width 0184 { 0185 kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */ 0186 kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */ 0187 kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */ 0188 } lpspi_transfer_width_t; 0189 0190 /*! @brief LPSPI delay type selection.*/ 0191 typedef enum _lpspi_delay_type 0192 { 0193 kLPSPI_PcsToSck = 1U, /*!< PCS-to-SCK delay. */ 0194 kLPSPI_LastSckToPcs, /*!< Last SCK edge to PCS delay. */ 0195 kLPSPI_BetweenTransfer /*!< Delay between transfers. */ 0196 } lpspi_delay_type_t; 0197 0198 #define LPSPI_MASTER_PCS_SHIFT (4U) /*!< LPSPI master PCS shift macro , internal used. */ 0199 #define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */ 0200 0201 /*! @brief Use this enumeration for LPSPI master transfer configFlags. */ 0202 enum _lpspi_transfer_config_flag_for_master 0203 { 0204 kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */ 0205 kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */ 0206 kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */ 0207 kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */ 0208 0209 kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */ 0210 0211 kLPSPI_MasterByteSwap = 0212 1U << 22 /*!< Is master swap the byte. 0213 * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set 0214 * lpspi_shift_direction_t to MSB). 0215 * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used 0216 * or not, the waveform is 1 2 3 4 5 6 7 8. 0217 * 2. If you set bitPerFrame = 16 : 0218 * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. 0219 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. 0220 * 3. If you set bitPerFrame = 32 : 0221 * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. 0222 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. 0223 */ 0224 }; 0225 0226 #define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */ 0227 #define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */ 0228 0229 /*! @brief Use this enumeration for LPSPI slave transfer configFlags. */ 0230 enum _lpspi_transfer_config_flag_for_slave 0231 { 0232 kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */ 0233 kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */ 0234 kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */ 0235 kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */ 0236 0237 kLPSPI_SlaveByteSwap = 0238 1U << 22 /*!< Is slave swap the byte. 0239 * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set 0240 * lpspi_shift_direction_t to MSB). 0241 * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used 0242 * or not, the waveform is 1 2 3 4 5 6 7 8. 0243 * 2. If you set bitPerFrame = 16 : 0244 * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. 0245 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. 0246 * 3. If you set bitPerFrame = 32 : 0247 * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. 0248 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. 0249 */ 0250 }; 0251 0252 /*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */ 0253 enum _lpspi_transfer_state 0254 { 0255 kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ 0256 kLPSPI_Busy, /*!< Transfer queue is not finished. */ 0257 kLPSPI_Error /*!< Transfer error. */ 0258 }; 0259 0260 /*! @brief LPSPI master configuration structure.*/ 0261 typedef struct _lpspi_master_config 0262 { 0263 uint32_t baudRate; /*!< Baud Rate for LPSPI. */ 0264 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ 0265 lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ 0266 lpspi_clock_phase_t cpha; /*!< Clock phase. */ 0267 lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ 0268 0269 uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. 0270 It sets the boundary value if out of range.*/ 0271 uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum 0272 delay. It sets the boundary value if out of range.*/ 0273 uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the 0274 minimum delay. It sets the boundary value if out of range.*/ 0275 0276 lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */ 0277 lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ 0278 0279 lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data 0280 *during single bit transfers.*/ 0281 0282 lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated 0283 * between accesses (LPSPI_PCS is negated). */ 0284 bool enableInputDelay; /*!< Enable master to sample the input data on a delayed SCK. This can help improve slave 0285 setup time. Refer to device data sheet for specific time length. */ 0286 } lpspi_master_config_t; 0287 0288 /*! @brief LPSPI slave configuration structure.*/ 0289 typedef struct _lpspi_slave_config 0290 { 0291 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ 0292 lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ 0293 lpspi_clock_phase_t cpha; /*!< Clock phase. */ 0294 lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ 0295 0296 lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */ 0297 lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ 0298 0299 lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data 0300 *during single bit transfers.*/ 0301 0302 lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated 0303 * between accesses (LPSPI_PCS is negated). */ 0304 } lpspi_slave_config_t; 0305 0306 /*! 0307 * @brief Forward declaration of the _lpspi_master_handle typedefs. 0308 */ 0309 typedef struct _lpspi_master_handle lpspi_master_handle_t; 0310 0311 /*! 0312 * @brief Forward declaration of the _lpspi_slave_handle typedefs. 0313 */ 0314 typedef struct _lpspi_slave_handle lpspi_slave_handle_t; 0315 0316 /*! 0317 * @brief Master completion callback function pointer type. 0318 * 0319 * @param base LPSPI peripheral address. 0320 * @param handle Pointer to the handle for the LPSPI master. 0321 * @param status Success or error code describing whether the transfer is completed. 0322 * @param userData Arbitrary pointer-dataSized value passed from the application. 0323 */ 0324 typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, 0325 lpspi_master_handle_t *handle, 0326 status_t status, 0327 void *userData); 0328 0329 /*! 0330 * @brief Slave completion callback function pointer type. 0331 * 0332 * @param base LPSPI peripheral address. 0333 * @param handle Pointer to the handle for the LPSPI slave. 0334 * @param status Success or error code describing whether the transfer is completed. 0335 * @param userData Arbitrary pointer-dataSized value passed from the application. 0336 */ 0337 typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, 0338 lpspi_slave_handle_t *handle, 0339 status_t status, 0340 void *userData); 0341 0342 /*! @brief LPSPI master/slave transfer structure.*/ 0343 typedef struct _lpspi_transfer 0344 { 0345 uint8_t *txData; /*!< Send buffer. */ 0346 uint8_t *rxData; /*!< Receive buffer. */ 0347 volatile size_t dataSize; /*!< Transfer bytes. */ 0348 0349 uint32_t configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if 0350 the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the 0351 transfer is used for slave.*/ 0352 } lpspi_transfer_t; 0353 0354 /*! @brief LPSPI master transfer handle structure used for transactional API. */ 0355 struct _lpspi_master_handle 0356 { 0357 volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ 0358 volatile bool writeTcrInIsr; /*!< A flag that whether should write TCR in ISR. */ 0359 0360 volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ 0361 volatile bool isTxMask; /*!< A flag that whether TCR[TXMSK] is set. */ 0362 volatile uint16_t bytesPerFrame; /*!< Number of bytes in each frame */ 0363 0364 volatile uint8_t fifoSize; /*!< FIFO dataSize. */ 0365 0366 volatile uint8_t rxWatermark; /*!< Rx watermark. */ 0367 0368 volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ 0369 volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ 0370 0371 uint8_t *volatile txData; /*!< Send buffer. */ 0372 uint8_t *volatile rxData; /*!< Receive buffer. */ 0373 volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ 0374 volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ 0375 0376 volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ 0377 volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ 0378 0379 uint32_t totalByteCount; /*!< Number of transfer bytes*/ 0380 0381 uint32_t txBuffIfNull; /*!< Used if the txData is NULL. */ 0382 0383 volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ 0384 0385 lpspi_master_transfer_callback_t callback; /*!< Completion callback. */ 0386 void *userData; /*!< Callback user data. */ 0387 }; 0388 0389 /*! @brief LPSPI slave transfer handle structure used for transactional API. */ 0390 struct _lpspi_slave_handle 0391 { 0392 volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ 0393 0394 volatile uint8_t fifoSize; /*!< FIFO dataSize. */ 0395 0396 volatile uint8_t rxWatermark; /*!< Rx watermark. */ 0397 0398 volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ 0399 volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ 0400 0401 uint8_t *volatile txData; /*!< Send buffer. */ 0402 uint8_t *volatile rxData; /*!< Receive buffer. */ 0403 0404 volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ 0405 volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ 0406 0407 volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ 0408 volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ 0409 0410 uint32_t totalByteCount; /*!< Number of transfer bytes*/ 0411 0412 volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ 0413 0414 volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ 0415 0416 lpspi_slave_transfer_callback_t callback; /*!< Completion callback. */ 0417 void *userData; /*!< Callback user data. */ 0418 }; 0419 0420 /********************************************************************************************************************** 0421 * API 0422 *********************************************************************************************************************/ 0423 #if defined(__cplusplus) 0424 extern "C" { 0425 #endif /*_cplusplus*/ 0426 0427 /*! 0428 * @name Initialization and deinitialization 0429 * @{ 0430 */ 0431 0432 /*! 0433 * @brief Initializes the LPSPI master. 0434 * 0435 * @param base LPSPI peripheral address. 0436 * @param masterConfig Pointer to structure lpspi_master_config_t. 0437 * @param srcClock_Hz Module source input clock in Hertz 0438 */ 0439 void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz); 0440 0441 /*! 0442 * @brief Sets the lpspi_master_config_t structure to default values. 0443 * 0444 * This API initializes the configuration structure for LPSPI_MasterInit(). 0445 * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified 0446 * before calling the LPSPI_MasterInit(). 0447 * Example: 0448 * @code 0449 * lpspi_master_config_t masterConfig; 0450 * LPSPI_MasterGetDefaultConfig(&masterConfig); 0451 * @endcode 0452 * @param masterConfig pointer to lpspi_master_config_t structure 0453 */ 0454 void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig); 0455 0456 /*! 0457 * @brief LPSPI slave configuration. 0458 * 0459 * @param base LPSPI peripheral address. 0460 * @param slaveConfig Pointer to a structure lpspi_slave_config_t. 0461 */ 0462 void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig); 0463 0464 /*! 0465 * @brief Sets the lpspi_slave_config_t structure to default values. 0466 * 0467 * This API initializes the configuration structure for LPSPI_SlaveInit(). 0468 * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified 0469 * before calling the LPSPI_SlaveInit(). 0470 * Example: 0471 * @code 0472 * lpspi_slave_config_t slaveConfig; 0473 * LPSPI_SlaveGetDefaultConfig(&slaveConfig); 0474 * @endcode 0475 * @param slaveConfig pointer to lpspi_slave_config_t structure. 0476 */ 0477 void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig); 0478 0479 /*! 0480 * @brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. 0481 * @param base LPSPI peripheral address. 0482 */ 0483 void LPSPI_Deinit(LPSPI_Type *base); 0484 0485 /*! 0486 * @brief Restores the LPSPI peripheral to reset state. Note that this function 0487 * sets all registers to reset state. As a result, the LPSPI module can't work after calling 0488 * this API. 0489 * @param base LPSPI peripheral address. 0490 */ 0491 void LPSPI_Reset(LPSPI_Type *base); 0492 0493 /*! 0494 * @brief Get the LPSPI instance from peripheral base address. 0495 * 0496 * @param base LPSPI peripheral base address. 0497 * @return LPSPI instance. 0498 */ 0499 uint32_t LPSPI_GetInstance(LPSPI_Type *base); 0500 0501 /*! 0502 * @brief Enables the LPSPI peripheral and sets the MCR MDIS to 0. 0503 * 0504 * @param base LPSPI peripheral address. 0505 * @param enable Pass true to enable module, false to disable module. 0506 */ 0507 static inline void LPSPI_Enable(LPSPI_Type *base, bool enable) 0508 { 0509 if (enable) 0510 { 0511 base->CR |= LPSPI_CR_MEN_MASK; 0512 } 0513 else 0514 { 0515 base->CR &= ~LPSPI_CR_MEN_MASK; 0516 } 0517 } 0518 0519 /*! 0520 *@} 0521 */ 0522 0523 /*! 0524 * @name Status 0525 * @{ 0526 */ 0527 0528 /*! 0529 * @brief Gets the LPSPI status flag state. 0530 * @param base LPSPI peripheral address. 0531 * @return The LPSPI status(in SR register). 0532 */ 0533 static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base) 0534 { 0535 return (base->SR); 0536 } 0537 0538 /*! 0539 * @brief Gets the LPSPI Tx FIFO size. 0540 * @param base LPSPI peripheral address. 0541 * @return The LPSPI Tx FIFO size. 0542 */ 0543 static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base) 0544 { 0545 return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT)); 0546 } 0547 0548 /*! 0549 * @brief Gets the LPSPI Rx FIFO size. 0550 * @param base LPSPI peripheral address. 0551 * @return The LPSPI Rx FIFO size. 0552 */ 0553 static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base) 0554 { 0555 return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT)); 0556 } 0557 0558 /*! 0559 * @brief Gets the LPSPI Tx FIFO count. 0560 * @param base LPSPI peripheral address. 0561 * @return The number of words in the transmit FIFO. 0562 */ 0563 static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base) 0564 { 0565 return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT); 0566 } 0567 0568 /*! 0569 * @brief Gets the LPSPI Rx FIFO count. 0570 * @param base LPSPI peripheral address. 0571 * @return The number of words in the receive FIFO. 0572 */ 0573 static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base) 0574 { 0575 return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT); 0576 } 0577 0578 /*! 0579 * @brief Clears the LPSPI status flag. 0580 * 0581 * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the 0582 * desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. 0583 * Example usage: 0584 * @code 0585 * LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag); 0586 * @endcode 0587 * 0588 * @param base LPSPI peripheral address. 0589 * @param statusFlags The status flag used from type _lpspi_flags. 0590 */ 0591 static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags) 0592 { 0593 base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ 0594 } 0595 0596 /*! 0597 *@} 0598 */ 0599 0600 /*! 0601 * @name Interrupts 0602 * @{ 0603 */ 0604 0605 /*! 0606 * @brief Enables the LPSPI interrupts. 0607 * 0608 * This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. 0609 * Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request. 0610 * 0611 * @code 0612 * LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); 0613 * @endcode 0614 * 0615 * @param base LPSPI peripheral address. 0616 * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. 0617 */ 0618 static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask) 0619 { 0620 base->IER |= mask; 0621 } 0622 0623 /*! 0624 * @brief Disables the LPSPI interrupts. 0625 * 0626 * @code 0627 * LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); 0628 * @endcode 0629 * 0630 * @param base LPSPI peripheral address. 0631 * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. 0632 */ 0633 static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask) 0634 { 0635 base->IER &= ~mask; 0636 } 0637 0638 /*! 0639 *@} 0640 */ 0641 0642 /*! 0643 * @name DMA Control 0644 * @{ 0645 */ 0646 0647 /*! 0648 * @brief Enables the LPSPI DMA request. 0649 * 0650 * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. 0651 * @code 0652 * LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); 0653 * @endcode 0654 * 0655 * @param base LPSPI peripheral address. 0656 * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. 0657 */ 0658 static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask) 0659 { 0660 base->DER |= mask; 0661 } 0662 0663 /*! 0664 * @brief Disables the LPSPI DMA request. 0665 * 0666 * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. 0667 * @code 0668 * SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); 0669 * @endcode 0670 * 0671 * @param base LPSPI peripheral address. 0672 * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. 0673 */ 0674 static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask) 0675 { 0676 base->DER &= ~mask; 0677 } 0678 0679 /*! 0680 * @brief Gets the LPSPI Transmit Data Register address for a DMA operation. 0681 * 0682 * This function gets the LPSPI Transmit Data Register address because this value is needed 0683 * for the DMA operation. 0684 * This function can be used for either master or slave mode. 0685 * 0686 * @param base LPSPI peripheral address. 0687 * @return The LPSPI Transmit Data Register address. 0688 */ 0689 static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base) 0690 { 0691 return (uint32_t) & (base->TDR); 0692 } 0693 0694 /*! 0695 * @brief Gets the LPSPI Receive Data Register address for a DMA operation. 0696 * 0697 * This function gets the LPSPI Receive Data Register address because this value is needed 0698 * for the DMA operation. 0699 * This function can be used for either master or slave mode. 0700 * 0701 * @param base LPSPI peripheral address. 0702 * @return The LPSPI Receive Data Register address. 0703 */ 0704 static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base) 0705 { 0706 return (uint32_t) & (base->RDR); 0707 } 0708 0709 /*! 0710 *@} 0711 */ 0712 0713 /*! 0714 * @name Bus Operations 0715 * @{ 0716 */ 0717 0718 /*! 0719 * @brief Check the argument for transfer . 0720 * 0721 * @param base LPSPI peripheral address. 0722 * @param transfer the transfer struct to be used. 0723 * @param isEdma True to check for EDMA transfer, false to check interrupt non-blocking transfer 0724 * @return Return true for right and false for wrong. 0725 */ 0726 bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma); 0727 0728 /*! 0729 * @brief Configures the LPSPI for either master or slave. 0730 * 0731 * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). 0732 * 0733 * @param base LPSPI peripheral address. 0734 * @param mode Mode setting (master or slave) of type lpspi_master_slave_mode_t. 0735 */ 0736 static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode) 0737 { 0738 base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); 0739 } 0740 0741 /*! 0742 * @brief Configures the peripheral chip select used for the transfer. 0743 * 0744 * @param base LPSPI peripheral address. 0745 * @param select LPSPI Peripheral Chip Select (PCS) configuration. 0746 */ 0747 static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select) 0748 { 0749 base->TCR = (base->TCR & (~LPSPI_TCR_PCS_MASK)) | LPSPI_TCR_PCS((uint8_t)select); 0750 } 0751 0752 /*! 0753 * @brief Set the PCS signal to continuous or uncontinuous mode. 0754 * 0755 * @note In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command 0756 * word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes. 0757 * In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after 0758 * that the LPSPI will transmit received data back (assuming a 32-bit shift register). 0759 * 0760 * @param base LPSPI peripheral address. 0761 * @param IsContinous True to set the transfer PCS to continuous mode, false to set to uncontinuous mode. 0762 */ 0763 static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous) 0764 { 0765 if (IsContinous) 0766 { 0767 base->TCR |= LPSPI_TCR_CONT_MASK; 0768 } 0769 else 0770 { 0771 base->TCR &= ~LPSPI_TCR_CONT_MASK; 0772 } 0773 } 0774 0775 /*! 0776 * @brief Returns whether the LPSPI module is in master mode. 0777 * 0778 * @param base LPSPI peripheral address. 0779 * @return Returns true if the module is in master mode or false if the module is in slave mode. 0780 */ 0781 static inline bool LPSPI_IsMaster(LPSPI_Type *base) 0782 { 0783 return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); 0784 } 0785 0786 /*! 0787 * @brief Flushes the LPSPI FIFOs. 0788 * 0789 * @param base LPSPI peripheral address. 0790 * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO. 0791 * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO. 0792 */ 0793 static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo) 0794 { 0795 base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT); 0796 } 0797 0798 /*! 0799 * @brief Sets the transmit and receive FIFO watermark values. 0800 * 0801 * This function allows the user to set the receive and transmit FIFO watermarks. The function 0802 * does not compare the watermark settings to the FIFO size. The FIFO watermark should not be 0803 * equal to or greater than the FIFO size. It is up to the higher level driver to make this check. 0804 * 0805 * @param base LPSPI peripheral address. 0806 * @param txWater The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. 0807 * @param rxWater The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. 0808 */ 0809 static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater) 0810 { 0811 base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater); 0812 } 0813 0814 /*! 0815 * @brief Configures all LPSPI peripheral chip select polarities simultaneously. 0816 * 0817 * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). 0818 * 0819 * This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of 0820 * PCS is device-specific. 0821 * @code 0822 * LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow); 0823 * @endcode 0824 * 0825 * @param base LPSPI peripheral address. 0826 * @param mask The PCS polarity mask; Use the enum _lpspi_pcs_polarity. 0827 */ 0828 static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask) 0829 { 0830 base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); 0831 } 0832 0833 /*! 0834 * @brief Configures the frame size. 0835 * 0836 * The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal 0837 * to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word 0838 * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not 0839 * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported. 0840 * 0841 * Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although 0842 * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command 0843 * register 0844 * should only be changed if the LPSPI is idle. 0845 * 0846 * Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That 0847 * means the TCR register should be written to when the Tx FIFO is not full. 0848 * 0849 * @param base LPSPI peripheral address. 0850 * @param frameSize The frame size in number of bits. 0851 */ 0852 static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize) 0853 { 0854 base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1U); 0855 } 0856 0857 /*! 0858 * @brief Sets the LPSPI baud rate in bits per second. 0859 * 0860 * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest 0861 * possible baud rate without exceeding the desired baud rate and returns the 0862 * calculated baud rate in bits-per-second. It requires the caller to provide 0863 * the frequency of the module source clock (in Hertz). Note that the baud rate 0864 * does not go into effect until the Transmit Control Register (TCR) is programmed 0865 * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue 0866 * parameter for later programming in the TCR. The higher level 0867 * peripheral driver should alert the user of an out of range baud rate input. 0868 * 0869 * Note that the LPSPI module must first be disabled before configuring this. 0870 * Note that the LPSPI module must be configured for master mode before configuring this. 0871 * 0872 * @param base LPSPI peripheral address. 0873 * @param baudRate_Bps The desired baud rate in bits per second. 0874 * @param srcClock_Hz Module source input clock in Hertz. 0875 * @param tcrPrescaleValue The TCR prescale value needed to program the TCR. 0876 * @return The actual calculated baud rate. This function may also return a "0" if the 0877 * LPSPI is not configured for master mode or if the LPSPI module is not disabled. 0878 */ 0879 0880 uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, 0881 uint32_t baudRate_Bps, 0882 uint32_t srcClock_Hz, 0883 uint32_t *tcrPrescaleValue); 0884 0885 /*! 0886 * @brief Manually configures a specific LPSPI delay parameter (module must be disabled to 0887 * change the delay values). 0888 * 0889 * This function configures the following: 0890 * SCK to PCS delay, or 0891 * PCS to SCK delay, or 0892 * The configurations must occur between the transfer delay. 0893 * 0894 * The delay names are available in type lpspi_delay_type_t. 0895 * 0896 * The user passes the desired delay along with the delay value. 0897 * This allows the user to directly set the delay values if they have 0898 * pre-calculated them or if they simply wish to manually increment the value. 0899 * 0900 * Note that the LPSPI module must first be disabled before configuring this. 0901 * Note that the LPSPI module must be configured for master mode before configuring this. 0902 * 0903 * @param base LPSPI peripheral address. 0904 * @param scaler The 8-bit delay value 0x00 to 0xFF (255). 0905 * @param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. 0906 */ 0907 void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay); 0908 0909 /*! 0910 * @brief Calculates the delay based on the desired delay input in nanoseconds (module must be 0911 * disabled to change the delay values). 0912 * 0913 * This function calculates the values for the following: 0914 * SCK to PCS delay, or 0915 * PCS to SCK delay, or 0916 * The configurations must occur between the transfer delay. 0917 * 0918 * The delay names are available in type lpspi_delay_type_t. 0919 * 0920 * The user passes the desired delay and the desired delay value in 0921 * nano-seconds. The function calculates the value needed for the desired delay parameter 0922 * and returns the actual calculated delay because an exact delay match may not be possible. In this 0923 * case, the closest match is calculated without going below the desired delay value input. 0924 * It is possible to input a very large delay value that exceeds the capability of the part, in 0925 * which case the maximum supported delay is returned. It is up to the higher level 0926 * peripheral driver to alert the user of an out of range delay input. 0927 * 0928 * Note that the LPSPI module must be configured for master mode before configuring this. And note that 0929 * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). 0930 * 0931 * @param base LPSPI peripheral address. 0932 * @param delayTimeInNanoSec The desired delay value in nano-seconds. 0933 * @param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. 0934 * @param srcClock_Hz Module source input clock in Hertz. 0935 * @return actual Calculated delay value in nano-seconds. 0936 */ 0937 uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, 0938 uint32_t delayTimeInNanoSec, 0939 lpspi_delay_type_t whichDelay, 0940 uint32_t srcClock_Hz); 0941 0942 /*! 0943 * @brief Writes data into the transmit data buffer. 0944 * 0945 * This function writes data passed in by the user to the Transmit Data Register (TDR). 0946 * The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, 0947 * the user has to manage sending the data one 32-bit word at a time. 0948 * Any writes to the TDR result in an immediate push to the transmit FIFO. 0949 * This function can be used for either master or slave modes. 0950 * 0951 * @param base LPSPI peripheral address. 0952 * @param data The data word to be sent. 0953 */ 0954 static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data) 0955 { 0956 base->TDR = data; 0957 } 0958 0959 /*! 0960 * @brief Reads data from the data buffer. 0961 * 0962 * This function reads the data from the Receive Data Register (RDR). 0963 * This function can be used for either master or slave mode. 0964 * 0965 * @param base LPSPI peripheral address. 0966 * @return The data read from the data buffer. 0967 */ 0968 static inline uint32_t LPSPI_ReadData(LPSPI_Type *base) 0969 { 0970 return (base->RDR); 0971 } 0972 0973 /*! 0974 * @brief Set up the dummy data. 0975 * 0976 * @param base LPSPI peripheral address. 0977 * @param dummyData Data to be transferred when tx buffer is NULL. 0978 * Note: 0979 * This API has no effect when LPSPI in slave interrupt mode, because driver 0980 * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit 0981 * FIFO and output pin is tristated. 0982 */ 0983 void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData); 0984 0985 /*! 0986 *@} 0987 */ 0988 0989 /*! 0990 * @name Transactional 0991 * @{ 0992 */ 0993 /*Transactional APIs*/ 0994 0995 /*! 0996 * @brief Initializes the LPSPI master handle. 0997 * 0998 * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a 0999 * specified LPSPI instance, call this API once to get the initialized handle. 1000 1001 * @param base LPSPI peripheral address. 1002 * @param handle LPSPI handle pointer to lpspi_master_handle_t. 1003 * @param callback DSPI callback. 1004 * @param userData callback function parameter. 1005 */ 1006 void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, 1007 lpspi_master_handle_t *handle, 1008 lpspi_master_transfer_callback_t callback, 1009 void *userData); 1010 1011 /*! 1012 * @brief LPSPI master transfer data using a polling method. 1013 * 1014 * This function transfers data using a polling method. This is a blocking function, which does not return until all 1015 * transfers have been 1016 * completed. 1017 * 1018 * Note: 1019 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. 1020 * For bytesPerFrame greater than 4: 1021 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. 1022 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. 1023 * 1024 * @param base LPSPI peripheral address. 1025 * @param transfer pointer to lpspi_transfer_t structure. 1026 * @return status of status_t. 1027 */ 1028 status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer); 1029 1030 /*! 1031 * @brief LPSPI master transfer data using an interrupt method. 1032 * 1033 * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. 1034 * When all data is transferred, the callback function is called. 1035 * 1036 * Note: 1037 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. 1038 * For bytesPerFrame greater than 4: 1039 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. 1040 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. 1041 * 1042 * @param base LPSPI peripheral address. 1043 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. 1044 * @param transfer pointer to lpspi_transfer_t structure. 1045 * @return status of status_t. 1046 */ 1047 status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer); 1048 1049 /*! 1050 * @brief Gets the master transfer remaining bytes. 1051 * 1052 * This function gets the master transfer remaining bytes. 1053 * 1054 * @param base LPSPI peripheral address. 1055 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. 1056 * @param count Number of bytes transferred so far by the non-blocking transaction. 1057 * @return status of status_t. 1058 */ 1059 status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count); 1060 1061 /*! 1062 * @brief LPSPI master abort transfer which uses an interrupt method. 1063 * 1064 * This function aborts a transfer which uses an interrupt method. 1065 * 1066 * @param base LPSPI peripheral address. 1067 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. 1068 */ 1069 void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle); 1070 1071 /*! 1072 * @brief LPSPI Master IRQ handler function. 1073 * 1074 * This function processes the LPSPI transmit and receive IRQ. 1075 * 1076 * @param base LPSPI peripheral address. 1077 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. 1078 */ 1079 void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle); 1080 1081 /*! 1082 * @brief Initializes the LPSPI slave handle. 1083 * 1084 * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a 1085 * specified LPSPI instance, call this API once to get the initialized handle. 1086 * 1087 * @param base LPSPI peripheral address. 1088 * @param handle LPSPI handle pointer to lpspi_slave_handle_t. 1089 * @param callback DSPI callback. 1090 * @param userData callback function parameter. 1091 */ 1092 void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, 1093 lpspi_slave_handle_t *handle, 1094 lpspi_slave_transfer_callback_t callback, 1095 void *userData); 1096 1097 /*! 1098 * @brief LPSPI slave transfer data using an interrupt method. 1099 * 1100 * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. 1101 * When all data is transferred, the callback function is called. 1102 * 1103 * Note: 1104 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. 1105 * For bytesPerFrame greater than 4: 1106 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. 1107 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. 1108 * 1109 * @param base LPSPI peripheral address. 1110 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. 1111 * @param transfer pointer to lpspi_transfer_t structure. 1112 * @return status of status_t. 1113 */ 1114 status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer); 1115 1116 /*! 1117 * @brief Gets the slave transfer remaining bytes. 1118 * 1119 * This function gets the slave transfer remaining bytes. 1120 * 1121 * @param base LPSPI peripheral address. 1122 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. 1123 * @param count Number of bytes transferred so far by the non-blocking transaction. 1124 * @return status of status_t. 1125 */ 1126 status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count); 1127 1128 /*! 1129 * @brief LPSPI slave aborts a transfer which uses an interrupt method. 1130 * 1131 * This function aborts a transfer which uses an interrupt method. 1132 * 1133 * @param base LPSPI peripheral address. 1134 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. 1135 */ 1136 void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle); 1137 1138 /*! 1139 * @brief LPSPI Slave IRQ handler function. 1140 * 1141 * This function processes the LPSPI transmit and receives an IRQ. 1142 * 1143 * @param base LPSPI peripheral address. 1144 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. 1145 */ 1146 void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle); 1147 1148 /*! 1149 *@} 1150 */ 1151 1152 #if defined(__cplusplus) 1153 } 1154 #endif 1155 1156 /*! @}*/ 1157 1158 #endif /*_FSL_LPSPI_H_*/
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