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0001 /* 0002 * Copyright (c) 2016, Freescale Semiconductor, Inc. 0003 * Copyright 2016-2022 NXP 0004 * All rights reserved. 0005 * 0006 * SPDX-License-Identifier: BSD-3-Clause 0007 */ 0008 #ifndef _FSL_LPADC_H_ 0009 #define _FSL_LPADC_H_ 0010 0011 #include "fsl_common.h" 0012 0013 /*! 0014 * @addtogroup lpadc 0015 * @{ 0016 */ 0017 0018 /*! @file */ 0019 0020 /******************************************************************************* 0021 * Definitions 0022 ******************************************************************************/ 0023 0024 /*! @name Driver version */ 0025 /*@{*/ 0026 /*! @brief LPADC driver version 2.6.1. */ 0027 #define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 6, 1)) 0028 /*@}*/ 0029 0030 /*! 0031 * @brief Define the MACRO function to get command status from status value. 0032 * 0033 * The statusVal is the return value from LPADC_GetStatusFlags(). 0034 */ 0035 #define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) 0036 0037 /*! 0038 * @brief Define the MACRO function to get trigger status from status value. 0039 * 0040 * The statusVal is the return value from LPADC_GetStatusFlags(). 0041 */ 0042 #define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) 0043 0044 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) 0045 /*! 0046 * @brief Define hardware flags of the module. 0047 */ 0048 enum _lpadc_status_flags 0049 { 0050 kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result 0051 FIFO 0 than it can hold. */ 0052 kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result 0053 FIFO 0 is greater than the setting watermark level. */ 0054 kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result 0055 FIFO 1 than it can hold. */ 0056 kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result 0057 FIFO 1 is greater than the setting watermark level. */ 0058 }; 0059 0060 /*! 0061 * @brief Define interrupt switchers of the module. 0062 */ 0063 enum _lpadc_interrupt_enable 0064 { 0065 kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt 0066 requests when FOF0 flag is asserted. */ 0067 kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt 0068 requests when RDY0 flag is asserted. */ 0069 kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt 0070 requests when FOF1 flag is asserted. */ 0071 kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt 0072 requests when RDY1 flag is asserted. */ 0073 #if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) 0074 kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception 0075 interrupt. */ 0076 kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt 0077 when trigger 0 completion. */ 0078 kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt 0079 when trigger 1 completion. */ 0080 kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL), /*!< Configures ADC to generate interrupt 0081 when trigger 2 completion. */ 0082 kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL), /*!< Configures ADC to generate interrupt 0083 when trigger 3 completion. */ 0084 kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL), /*!< Configures ADC to generate interrupt 0085 when trigger 4 completion. */ 0086 kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL), /*!< Configures ADC to generate interrupt 0087 when trigger 5 completion. */ 0088 kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL), /*!< Configures ADC to generate interrupt 0089 when trigger 6 completion. */ 0090 kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL), /*!< Configures ADC to generate interrupt 0091 when trigger 7 completion. */ 0092 kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL), /*!< Configures ADC to generate interrupt 0093 when trigger 8 completion. */ 0094 kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL), /*!< Configures ADC to generate interrupt 0095 when trigger 9 completion. */ 0096 kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt 0097 when trigger 10 completion. */ 0098 kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt 0099 when trigger 11 completion. */ 0100 kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt 0101 when trigger 12 completion. */ 0102 kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt 0103 when trigger 13 completion. */ 0104 kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt 0105 when trigger 14 completion. */ 0106 kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt 0107 when trigger 15 completion. */ 0108 #endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ 0109 }; 0110 #else 0111 /*! 0112 * @brief Define hardware flags of the module. 0113 */ 0114 enum _lpadc_status_flags 0115 { 0116 kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO 0117 than it can hold. */ 0118 kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO 0119 is greater than the setting watermark level. */ 0120 }; 0121 0122 /*! 0123 * @brief Define interrupt switchers of the module. 0124 */ 0125 enum _lpadc_interrupt_enable 0126 { 0127 kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt 0128 requests when FOF flag is asserted. */ 0129 kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt 0130 requests when RDY flag is asserted. */ 0131 }; 0132 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ 0133 0134 #if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) 0135 /*! 0136 * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. 0137 */ 0138 enum _lpadc_trigger_status_flags 0139 { 0140 kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ 0141 kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ 0142 kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ 0143 kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ 0144 kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ 0145 kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ 0146 kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ 0147 kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ 0148 kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ 0149 kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ 0150 kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ 0151 kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ 0152 kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ 0153 kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ 0154 kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ 0155 kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ 0156 0157 kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and 0158 trigger 0 has enabled completion interrupts. */ 0159 kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and 0160 trigger 1 has enabled completion interrupts. */ 0161 kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and 0162 trigger 2 has enabled completion interrupts. */ 0163 kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and 0164 trigger 3 has enabled completion interrupts. */ 0165 kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and 0166 trigger 4 has enabled completion interrupts. */ 0167 kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and 0168 trigger 5 has enabled completion interrupts. */ 0169 kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and 0170 trigger 6 has enabled completion interrupts. */ 0171 kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and 0172 trigger 7 has enabled completion interrupts. */ 0173 kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and 0174 trigger 8 has enabled completion interrupts. */ 0175 kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and 0176 trigger 9 has enabled completion interrupts. */ 0177 kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and 0178 trigger 10 has enabled completion interrupts. */ 0179 kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and 0180 trigger 11 has enabled completion interrupts. */ 0181 kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and 0182 trigger 12 has enabled completion interrupts. */ 0183 kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and 0184 trigger 13 has enabled completion interrupts. */ 0185 kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and 0186 trigger 14 has enabled completion interrupts. */ 0187 kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and 0188 trigger 15 has enabled completion interrupts. */ 0189 }; 0190 #endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ 0191 0192 /*! 0193 * @brief Define enumeration of sample scale mode. 0194 * 0195 * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum 0196 * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the 0197 * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows 0198 * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. 0199 */ 0200 typedef enum _lpadc_sample_scale_mode 0201 { 0202 kLPADC_SamplePartScale = 0203 0U, /*!< Use divided input voltage signal. (For scale select,please refer to the reference manual). */ 0204 kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ 0205 } lpadc_sample_scale_mode_t; 0206 0207 /*! 0208 * @brief Define enumeration of channel sample mode. 0209 * 0210 * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. 0211 */ 0212 typedef enum _lpadc_sample_channel_mode 0213 { 0214 kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ 0215 kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ 0216 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF 0217 kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minus side. */ 0218 kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minus side. */ 0219 #elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE 0220 kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ 0221 kLPADC_SampleChannelDualSingleEndBothSide = 0222 3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ 0223 #endif 0224 } lpadc_sample_channel_mode_t; 0225 0226 /*! 0227 * @brief Define enumeration of hardware average selection. 0228 * 0229 * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to 0230 * capture temporary results while the averaging iterations are executed. 0231 */ 0232 typedef enum _lpadc_hardware_average_mode 0233 { 0234 kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ 0235 kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ 0236 kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ 0237 kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ 0238 kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ 0239 kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ 0240 kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ 0241 kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ 0242 #if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ 0243 (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4)) 0244 kLPADC_HardwareAverageCount256 = 8U, /*!< 256 conversions averaged. */ 0245 kLPADC_HardwareAverageCount512 = 9U, /*!< 512 conversions averaged. */ 0246 kLPADC_HardwareAverageCount1024 = 10U, /*!< 1024 conversions averaged. */ 0247 #endif /* FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH */ 0248 } lpadc_hardware_average_mode_t; 0249 0250 /*! 0251 * @brief Define enumeration of sample time selection. 0252 * 0253 * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher 0254 * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption 0255 * when command looping and sequencing is configured and high conversion rates are not required. 0256 */ 0257 typedef enum _lpadc_sample_time_mode 0258 { 0259 kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ 0260 kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ 0261 kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ 0262 kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ 0263 kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ 0264 kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ 0265 kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ 0266 kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ 0267 } lpadc_sample_time_mode_t; 0268 0269 /*! 0270 * @brief Define enumeration of hardware compare mode. 0271 * 0272 * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting 0273 * guides operation of the automatic compare function to optionally only store when the compare operation is true. 0274 * When compare is enabled, the conversion result is compared to the compare values. 0275 */ 0276 typedef enum _lpadc_hardware_compare_mode 0277 { 0278 kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ 0279 kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ 0280 kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ 0281 } lpadc_hardware_compare_mode_t; 0282 0283 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE 0284 /*! 0285 * @brief Define enumeration of conversion resolution mode. 0286 * 0287 * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to 0288 * #lpadc_sample_channel_mode_t 0289 */ 0290 typedef enum _lpadc_conversion_resolution_mode 0291 { 0292 kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential 0293 13-bit conversion with 2's complement output. */ 0294 kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit 0295 conversion with 2's complement output. */ 0296 } lpadc_conversion_resolution_mode_t; 0297 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ 0298 0299 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS 0300 /*! 0301 * @brief Define enumeration of conversion averages mode. 0302 * 0303 * Configure the converion average number for auto-calibration. 0304 */ 0305 typedef enum _lpadc_conversion_average_mode 0306 { 0307 kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ 0308 kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ 0309 kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ 0310 kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ 0311 kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ 0312 kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ 0313 kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ 0314 kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ 0315 #if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ 0316 (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4)) 0317 kLPADC_ConversionAverage256 = 8U, /*!< 256 conversions averaged. */ 0318 kLPADC_ConversionAverage512 = 9U, /*!< 512 conversions averaged. */ 0319 kLPADC_ConversionAverage1024 = 10U, /*!< 1024 conversions averaged. */ 0320 #endif /* FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH */ 0321 } lpadc_conversion_average_mode_t; 0322 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ 0323 0324 /*! 0325 * @brief Define enumeration of reference voltage source. 0326 * 0327 * For detail information, need to check the SoC's specification. 0328 */ 0329 typedef enum _lpadc_reference_voltage_mode 0330 { 0331 kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ 0332 kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ 0333 kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ 0334 } lpadc_reference_voltage_source_t; 0335 0336 /*! 0337 * @brief Define enumeration of power configuration. 0338 * 0339 * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be 0340 * possible. Refer to the device data sheet for power and performance capabilities for each setting. 0341 */ 0342 typedef enum _lpadc_power_level_mode 0343 { 0344 kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ 0345 kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ 0346 kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ 0347 kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ 0348 } lpadc_power_level_mode_t; 0349 0350 #if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) 0351 /*! 0352 * @brief Define enumeration of offset calibration mode. 0353 * 0354 */ 0355 typedef enum _lpadc_offset_calibration_mode 0356 { 0357 kLPADC_OffsetCalibration12bitMode = 0U, /*!< 12 bit offset calibration mode. */ 0358 kLPADC_OffsetCalibration16bitMode = 1U, /*!< 16 bit offset calibration mode. */ 0359 } lpadc_offset_calibration_mode_t; 0360 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ 0361 0362 /*! 0363 * @brief Define enumeration of trigger priority policy. 0364 * 0365 * This selection controls how higher priority triggers are handled. 0366 */ 0367 typedef enum _lpadc_trigger_priority_policy 0368 { 0369 kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command 0370 processing, the current conversion is aborted and the new 0371 command specified by the trigger is started. */ 0372 kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing, 0373 the current conversion is completed (including averaging iterations 0374 and compare function if enabled) and stored to the result FIFO 0375 before the higher priority trigger/command is initiated. */ 0376 #if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY 0377 kLPADC_TriggerPriorityPreemptSubsequently = 2U, /*!< If a higher priority trigger is received during command 0378 processing, the current command will be completed (averaging, 0379 looping, compare) before servicing the higher priority trigger. */ 0380 #endif /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */ 0381 } lpadc_trigger_priority_policy_t; 0382 0383 /*! 0384 * @brief LPADC global configuration. 0385 * 0386 * This structure would used to keep the settings for initialization. 0387 */ 0388 typedef struct 0389 { 0390 #if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN 0391 bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock 0392 selection logic at the chip level and is optionally used for the ADC clock source. */ 0393 #endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ 0394 #if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG 0395 bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". 0396 If voltage reference option1 input is above 1.8V, it should be "false". */ 0397 #endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ 0398 bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When 0399 enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the 0400 ADC will wait for the current averaging iteration/FIFO storage to complete before 0401 acknowledging stop or wait mode entry. */ 0402 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS 0403 lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ 0404 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ 0405 bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without 0406 startup delays(at the cost of higher DC current consumption). */ 0407 uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered 0408 while the ADC is active and there is a counted delay defined by this field after an 0409 initial trigger transitions the ADC from its Idle state to allow time for the analog 0410 circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must 0411 result in a longer delay than the analog startup time. */ 0412 lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for 0413 conversions.*/ 0414 0415 #if !(defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 0)) 0416 lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ 0417 #endif /* FSL_FEATURE_LPADC_HAS_CFG_PWRSEL */ 0418 lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to 0419 lpadc_trigger_priority_policy_t. */ 0420 bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during 0421 command execution sequencing between LOOP iterations, between commands in a sequence, and 0422 between conversions when command is executing in "Compare Until True" configuration. */ 0423 uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay 0424 is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing 0425 function is enabled. The available value range is in 9-bit. */ 0426 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) 0427 /* for FIFO0. */ 0428 uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords 0429 stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag 0430 would be asserted to indicate stored data has reached the programmable threshold. */ 0431 /* for FIFO1. */ 0432 uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords 0433 stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag 0434 would be asserted to indicate stored data has reached the programmable threshold. */ 0435 #else 0436 /* for FIFO. */ 0437 uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored 0438 in the ADC Result FIFO is greater than the value in this field, the ready flag would be 0439 asserted to indicate stored data has reached the programmable threshold. */ 0440 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ 0441 } lpadc_config_t; 0442 0443 /*! 0444 * @brief Define structure to keep the configuration for conversion command. 0445 */ 0446 typedef struct 0447 { 0448 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE 0449 lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ 0450 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ 0451 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE 0452 lpadc_sample_scale_mode_t channelBScaleMode; /*!< Alternate channe B Scale mode. */ 0453 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ 0454 lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ 0455 uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ 0456 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH 0457 uint32_t channelBNumber; /*!< Alternate Channel B number, select the channel. */ 0458 #endif 0459 uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. 0460 1-15 is available, 0 is to terminate the chain after this command. */ 0461 bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number 0462 of times the selected channel is converted consecutively; when enabled, the 0463 "loopCount" field defines how many consecutive channels are converted as part 0464 of the command execution. */ 0465 uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next 0466 command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ 0467 lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ 0468 lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ 0469 0470 lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ 0471 uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ 0472 uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ 0473 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE 0474 lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ 0475 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ 0476 #if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG 0477 bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be 0478 automatically executed; when enabled, the active trigger must be asserted again before 0479 executing this command. */ 0480 #endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ 0481 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN 0482 bool enableChannelB; /*! Enable alternate Channel B */ 0483 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ 0484 } lpadc_conv_command_config_t; 0485 0486 /*! 0487 * @brief Define structure to keep the configuration for conversion trigger. 0488 */ 0489 typedef struct 0490 { 0491 uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated 0492 trigger event. */ 0493 uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. 0494 When this field is clear, then no delay is incurred. When this field is set to a non-zero 0495 value, the duration for the delay is 2^delayPower ADCK cycles. The available value range 0496 is 4-bit. */ 0497 uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same 0498 priority level setting, the lower order trigger event has the higher priority. The lower 0499 value for this field is for the higher priority, the available value range is 1-bit. */ 0500 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) 0501 uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ 0502 uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ 0503 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ 0504 bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the 0505 input trigger source or not. THe software trigger is always available. */ 0506 } lpadc_conv_trigger_config_t; 0507 0508 /*! 0509 * @brief Define the structure to keep the conversion result. 0510 */ 0511 typedef struct 0512 { 0513 uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ 0514 uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ 0515 uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ 0516 uint16_t convValue; /*!< Data result. */ 0517 } lpadc_conv_result_t; 0518 0519 #if defined(__cplusplus) 0520 extern "C" { 0521 #endif 0522 0523 /******************************************************************************* 0524 * API 0525 ******************************************************************************/ 0526 /*! 0527 * @name Initialization & de-initialization. 0528 * @{ 0529 */ 0530 0531 /*! 0532 * @brief Initializes the LPADC module. 0533 * 0534 * @param base LPADC peripheral base address. 0535 * @param config Pointer to configuration structure. See "lpadc_config_t". 0536 */ 0537 void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); 0538 0539 /*! 0540 * @brief Gets an available pre-defined settings for initial configuration. 0541 * 0542 * This function initializes the converter configuration structure with an available settings. The default values are: 0543 * @code 0544 * config->enableInDozeMode = true; 0545 * config->enableAnalogPreliminary = false; 0546 * config->powerUpDelay = 0x80; 0547 * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; 0548 * config->powerLevelMode = kLPADC_PowerLevelAlt1; 0549 * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; 0550 * config->enableConvPause = false; 0551 * config->convPauseDelay = 0U; 0552 * config->FIFOWatermark = 0U; 0553 * @endcode 0554 * @param config Pointer to configuration structure. 0555 */ 0556 void LPADC_GetDefaultConfig(lpadc_config_t *config); 0557 0558 /*! 0559 * @brief De-initializes the LPADC module. 0560 * 0561 * @param base LPADC peripheral base address. 0562 */ 0563 void LPADC_Deinit(ADC_Type *base); 0564 0565 /*! 0566 * @brief Switch on/off the LPADC module. 0567 * 0568 * @param base LPADC peripheral base address. 0569 * @param enable switcher to the module. 0570 */ 0571 static inline void LPADC_Enable(ADC_Type *base, bool enable) 0572 { 0573 if (enable) 0574 { 0575 base->CTRL |= ADC_CTRL_ADCEN_MASK; 0576 } 0577 else 0578 { 0579 base->CTRL &= ~ADC_CTRL_ADCEN_MASK; 0580 } 0581 } 0582 0583 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) 0584 /*! 0585 * @brief Do reset the conversion FIFO0. 0586 * 0587 * @param base LPADC peripheral base address. 0588 */ 0589 static inline void LPADC_DoResetFIFO0(ADC_Type *base) 0590 { 0591 base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; 0592 } 0593 0594 /*! 0595 * @brief Do reset the conversion FIFO1. 0596 * 0597 * @param base LPADC peripheral base address. 0598 */ 0599 static inline void LPADC_DoResetFIFO1(ADC_Type *base) 0600 { 0601 base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; 0602 } 0603 #else 0604 /*! 0605 * @brief Do reset the conversion FIFO. 0606 * 0607 * @param base LPADC peripheral base address. 0608 */ 0609 static inline void LPADC_DoResetFIFO(ADC_Type *base) 0610 { 0611 base->CTRL |= ADC_CTRL_RSTFIFO_MASK; 0612 } 0613 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ 0614 0615 /*! 0616 * @brief Do reset the module's configuration. 0617 * 0618 * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). 0619 * 0620 * @param base LPADC peripheral base address. 0621 */ 0622 static inline void LPADC_DoResetConfig(ADC_Type *base) 0623 { 0624 base->CTRL |= ADC_CTRL_RST_MASK; 0625 base->CTRL &= ~ADC_CTRL_RST_MASK; 0626 } 0627 0628 /* @} */ 0629 0630 /*! 0631 * @name Status 0632 * @{ 0633 */ 0634 0635 /*! 0636 * @brief Get status flags. 0637 * 0638 * @param base LPADC peripheral base address. 0639 * @return status flags' mask. See to #_lpadc_status_flags. 0640 */ 0641 static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) 0642 { 0643 return base->STAT; 0644 } 0645 0646 /*! 0647 * @brief Clear status flags. 0648 * 0649 * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. 0650 * 0651 * @param base LPADC peripheral base address. 0652 * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. 0653 */ 0654 static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) 0655 { 0656 base->STAT = mask; 0657 } 0658 0659 #if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) 0660 /*! 0661 * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high 0662 * priority trigger exception. 0663 * 0664 * @param base LPADC peripheral base address. 0665 * @return The OR'ed value of @ref _lpadc_trigger_status_flags. 0666 */ 0667 static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) 0668 { 0669 return base->TSTAT; 0670 } 0671 0672 /*! 0673 * @brief Clear trigger status flags. 0674 * 0675 * @param base LPADC peripheral base address. 0676 * @param mask The mask of trigger status flags to be cleared, should be the 0677 * OR'ed value of @ref _lpadc_trigger_status_flags. 0678 */ 0679 static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) 0680 { 0681 base->TSTAT = mask; 0682 } 0683 #endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ 0684 0685 /* @} */ 0686 0687 /*! 0688 * @name Interrupts 0689 * @{ 0690 */ 0691 0692 /*! 0693 * @brief Enable interrupts. 0694 * 0695 * @param base LPADC peripheral base address. 0696 * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. 0697 */ 0698 static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) 0699 { 0700 base->IE |= mask; 0701 } 0702 0703 /*! 0704 * @brief Disable interrupts. 0705 * 0706 * @param base LPADC peripheral base address. 0707 * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. 0708 */ 0709 static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) 0710 { 0711 base->IE &= ~mask; 0712 } 0713 0714 /*! 0715 * @name DMA Control 0716 * @{ 0717 */ 0718 0719 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) 0720 /*! 0721 * @brief Switch on/off the DMA trigger for FIFO0 watermark event. 0722 * 0723 * @param base LPADC peripheral base address. 0724 * @param enable Switcher to the event. 0725 */ 0726 static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) 0727 { 0728 if (enable) 0729 { 0730 base->DE |= ADC_DE_FWMDE0_MASK; 0731 } 0732 else 0733 { 0734 base->DE &= ~ADC_DE_FWMDE0_MASK; 0735 } 0736 } 0737 0738 /*! 0739 * @brief Switch on/off the DMA trigger for FIFO1 watermark event. 0740 * 0741 * @param base LPADC peripheral base address. 0742 * @param enable Switcher to the event. 0743 */ 0744 static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) 0745 { 0746 if (enable) 0747 { 0748 base->DE |= ADC_DE_FWMDE1_MASK; 0749 } 0750 else 0751 { 0752 base->DE &= ~ADC_DE_FWMDE1_MASK; 0753 } 0754 } 0755 #else 0756 /*! 0757 * @brief Switch on/off the DMA trigger for FIFO watermark event. 0758 * 0759 * @param base LPADC peripheral base address. 0760 * @param enable Switcher to the event. 0761 */ 0762 static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) 0763 { 0764 if (enable) 0765 { 0766 base->DE |= ADC_DE_FWMDE_MASK; 0767 } 0768 else 0769 { 0770 base->DE &= ~ADC_DE_FWMDE_MASK; 0771 } 0772 } 0773 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ 0774 /* @} */ 0775 0776 /*! 0777 * @name Trigger and conversion with FIFO. 0778 * @{ 0779 */ 0780 0781 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) 0782 /*! 0783 * @brief Get the count of result kept in conversion FIFOn. 0784 * 0785 * @param base LPADC peripheral base address. 0786 * @param index Result FIFO index. 0787 * @return The count of result kept in conversion FIFOn. 0788 */ 0789 static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) 0790 { 0791 return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; 0792 } 0793 0794 /*! 0795 * brief Get the result in conversion FIFOn. 0796 * 0797 * param base LPADC peripheral base address. 0798 * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. 0799 * param index Result FIFO index. 0800 * 0801 * return Status whether FIFOn entry is valid. 0802 */ 0803 bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); 0804 #else 0805 /*! 0806 * @brief Get the count of result kept in conversion FIFO. 0807 * 0808 * @param base LPADC peripheral base address. 0809 * @return The count of result kept in conversion FIFO. 0810 */ 0811 static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) 0812 { 0813 return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; 0814 } 0815 0816 /*! 0817 * @brief Get the result in conversion FIFO. 0818 * 0819 * @param base LPADC peripheral base address. 0820 * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. 0821 * 0822 * @return Status whether FIFO entry is valid. 0823 */ 0824 bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); 0825 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ 0826 0827 /*! 0828 * @brief Configure the conversion trigger source. 0829 * 0830 * Each programmable trigger can launch the conversion command in command buffer. 0831 * 0832 * @param base LPADC peripheral base address. 0833 * @param triggerId ID for each trigger. Typically, the available value range is from 0. 0834 * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. 0835 */ 0836 void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); 0837 0838 /*! 0839 * @brief Gets an available pre-defined settings for trigger's configuration. 0840 * 0841 * This function initializes the trigger's configuration structure with an available settings. The default values are: 0842 * @code 0843 * config->commandIdSource = 0U; 0844 * config->loopCountIndex = 0U; 0845 * config->triggerIdSource = 0U; 0846 * config->enableHardwareTrigger = false; 0847 * @endcode 0848 * @param config Pointer to configuration structure. 0849 */ 0850 void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); 0851 0852 /*! 0853 * @brief Do software trigger to conversion command. 0854 * 0855 * @param base LPADC peripheral base address. 0856 * @param triggerIdMask Mask value for software trigger indexes, which count from zero. 0857 */ 0858 static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) 0859 { 0860 /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ 0861 base->SWTRIG = triggerIdMask; 0862 } 0863 0864 #if defined(FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL) && FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL 0865 /*! 0866 * @brief Enable hardware trigger command selection. 0867 * 0868 * This function will use the hardware trigger command from ADC_ETC.The trigger command is then defined 0869 * by ADC hardware trigger command selection field in ADC_ETC- >TRIGx_CHAINy_z_n[CSEL]. 0870 * 0871 * @param base LPADC peripheral base address. 0872 * @param triggerId ID for each trigger. Typically, the available value range is from 0. 0873 * @param enable True to enable or flase to disable. 0874 */ 0875 static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, uint32_t triggerId, bool enable) 0876 { 0877 if (enable) 0878 { 0879 base->TCTRL[triggerId] |= ADC_TCTRL_CMD_SEL_MASK; 0880 } 0881 else 0882 { 0883 base->TCTRL[triggerId] &= ~ADC_TCTRL_CMD_SEL_MASK; 0884 } 0885 } 0886 #endif /* FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL*/ 0887 0888 /*! 0889 * @brief Configure conversion command. 0890 * 0891 * @param base LPADC peripheral base address. 0892 * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. 0893 * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. 0894 */ 0895 void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); 0896 0897 /*! 0898 * @brief Gets an available pre-defined settings for conversion command's configuration. 0899 * 0900 * This function initializes the conversion command's configuration structure with an available settings. The default 0901 * values are: 0902 * @code 0903 * config->sampleScaleMode = kLPADC_SampleFullScale; 0904 * config->channelBScaleMode = kLPADC_SampleFullScale; 0905 * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA; 0906 * config->channelNumber = 0U; 0907 * config->chainedNextCmdNumber = 0U; 0908 * config->enableAutoChannelIncrement = false; 0909 * config->loopCount = 0U; 0910 * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; 0911 * config->sampleTimeMode = kLPADC_SampleTimeADCK3; 0912 * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; 0913 * config->hardwareCompareValueHigh = 0U; 0914 * config->hardwareCompareValueLow = 0U; 0915 * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; 0916 * config->enableWaitTrigger = false; 0917 * config->enableChannelB = false; 0918 * @endcode 0919 * @param config Pointer to configuration structure. 0920 */ 0921 void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); 0922 0923 #if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS 0924 /*! 0925 * @brief Enable the calibration function. 0926 * 0927 * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes 0928 * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value 0929 * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- 0930 * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the 0931 * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. 0932 * 0933 * @param base LPADC peripheral base address. 0934 * @param enable switcher to the calibration function. 0935 */ 0936 void LPADC_EnableCalibration(ADC_Type *base, bool enable); 0937 #if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM 0938 /*! 0939 * @brief Set proper offset value to trim ADC. 0940 * 0941 * To minimize the offset during normal operation, software should read the conversion result from 0942 * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. 0943 * 0944 * @param base LPADC peripheral base address. 0945 * @param value Setting offset value. 0946 */ 0947 static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) 0948 { 0949 base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; 0950 } 0951 0952 /*! 0953 * @brief Do auto calibration. 0954 * 0955 * Calibration function should be executed before using converter in application. It used the software trigger and a 0956 * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API 0957 * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) 0958 * -LPADC_SetConvTriggerConfig(...) 0959 * 0960 * @param base LPADC peripheral base address. 0961 */ 0962 void LPADC_DoAutoCalibration(ADC_Type *base); 0963 #endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ 0964 #endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ 0965 0966 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS 0967 #if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM 0968 /*! 0969 * @brief Set proper offset value to trim ADC. 0970 * 0971 * Set the offset trim value for offset calibration manually. 0972 * 0973 * @param base LPADC peripheral base address. 0974 * @param valueA Setting offset value A. 0975 * @param valueB Setting offset value B. 0976 * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. 0977 */ 0978 static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) 0979 { 0980 base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); 0981 } 0982 #else 0983 /*! 0984 * @brief Set proper offset value to trim 12 bit ADC conversion. 0985 * 0986 * Set the offset trim value for offset calibration manually. 0987 * 0988 * @param base LPADC peripheral base address. 0989 * @param valueA Setting offset value A. 0990 * @param valueB Setting offset value B. 0991 * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. 0992 */ 0993 static inline void LPADC_SetOffset12BitValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) 0994 { 0995 base->OFSTRIM12 = ADC_OFSTRIM12_OFSTRIM_A(valueA) | ADC_OFSTRIM12_OFSTRIM_A(valueB); 0996 } 0997 0998 /*! 0999 * @brief Set proper offset value to trim 16 bit ADC conversion. 1000 * 1001 * Set the offset trim value for offset calibration manually. 1002 * 1003 * @param base LPADC peripheral base address. 1004 * @param valueA Setting offset value A. 1005 * @param valueB Setting offset value B. 1006 * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. 1007 */ 1008 static inline void LPADC_SetOffset16BitValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) 1009 { 1010 base->OFSTRIM16 = ADC_OFSTRIM16_OFSTRIM_A(valueA) | ADC_OFSTRIM16_OFSTRIM_B(valueB); 1011 } 1012 #endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ 1013 1014 /*! 1015 * @brief Enable the offset calibration function. 1016 * 1017 * @param base LPADC peripheral base address. 1018 * @param enable switcher to the calibration function. 1019 */ 1020 static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) 1021 { 1022 if (enable) 1023 { 1024 base->CTRL |= ADC_CTRL_CALOFS_MASK; 1025 } 1026 else 1027 { 1028 base->CTRL &= ~ADC_CTRL_CALOFS_MASK; 1029 } 1030 } 1031 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE 1032 /*! 1033 * @brief Set offset calibration mode. 1034 * 1035 * @param base LPADC peripheral base address. 1036 * @param mode set offset calibration mode.see to #lpadc_offset_calibration_mode_t . 1037 */ 1038 static inline void LPADC_SetOffsetCalibrationMode(ADC_Type *base, lpadc_offset_calibration_mode_t mode) 1039 { 1040 base->CTRL = (base->CTRL & ~ADC_CTRL_CALOFSMODE_MASK) | ADC_CTRL_CALOFSMODE(mode); 1041 } 1042 1043 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ 1044 1045 /*! 1046 * @brief Do offset calibration. 1047 * 1048 * @param base LPADC peripheral base address. 1049 */ 1050 void LPADC_DoOffsetCalibration(ADC_Type *base); 1051 1052 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ 1053 /*! 1054 * brief Do auto calibration. 1055 * 1056 * param base LPADC peripheral base address. 1057 */ 1058 void LPADC_DoAutoCalibration(ADC_Type *base); 1059 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ 1060 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ 1061 1062 /* @} */ 1063 1064 #if defined(__cplusplus) 1065 } 1066 #endif 1067 /*! 1068 * @} 1069 */ 1070 #endif /* _FSL_LPADC_H_ */
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