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File indexing completed on 2025-05-11 08:22:59
0001 /* 0002 * Copyright (c) 2016, Freescale Semiconductor, Inc. 0003 * Copyright 2017-2021 NXP 0004 * All rights reserved. 0005 * 0006 * SPDX-License-Identifier: BSD-3-Clause 0007 */ 0008 0009 #ifndef _FSL_IEE_H_ 0010 #define _FSL_IEE_H_ 0011 0012 #include "fsl_common.h" 0013 0014 /*! 0015 * @addtogroup iee 0016 * @{ 0017 */ 0018 0019 /******************************************************************************* 0020 * Definitions 0021 ******************************************************************************/ 0022 0023 /*! @name Driver version */ 0024 /*@{*/ 0025 /*! @brief IEE driver version. Version 2.1.1. 0026 * 0027 * Current version: 2.1.1 0028 * 0029 * Change log: 0030 * - Version 2.0.0 0031 * - Initial version 0032 * - Version 2.1.0 0033 * - Add region lock function IEE_LockRegionConfig() and driver clock control 0034 * - Version 2.1.1 0035 * - Fixed MISRA issues. 0036 */ 0037 #define FSL_IEE_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) 0038 /*@}*/ 0039 0040 /*! @brief IEE region. */ 0041 typedef enum _iee_region 0042 { 0043 kIEE_Region0 = 0U, /*!< IEE region 0 */ 0044 kIEE_Region1 = 1U, /*!< IEE region 1 */ 0045 kIEE_Region2 = 2U, /*!< IEE region 2 */ 0046 kIEE_Region3 = 3U, /*!< IEE region 3 */ 0047 kIEE_Region4 = 4U, /*!< IEE region 4 */ 0048 kIEE_Region5 = 5U, /*!< IEE region 5 */ 0049 kIEE_Region6 = 6U, /*!< IEE region 6 */ 0050 kIEE_Region7 = 7U /*!< IEE region 7 */ 0051 } iee_region_t; 0052 0053 /*! @brief IEE AES enablement/bypass. */ 0054 typedef enum _iee_aes_bypass 0055 { 0056 kIEE_AesUseMdField = 0U, /*!< AES encryption/decryption enabled */ 0057 kIEE_AesBypass = 1U /*!< AES encryption/decryption bypass */ 0058 } iee_aes_bypass_t; 0059 0060 /*! @brief IEE AES mode. */ 0061 typedef enum _iee_aes_mode 0062 { 0063 kIEE_ModeNone = 0U, /*!< AES NONE mode */ 0064 kIEE_ModeAesXTS = 1U, /*!< AES XTS mode */ 0065 kIEE_ModeAesCTRWAddress = 2U, /*!< CTR w address binding mode */ 0066 kIEE_ModeAesCTRWOAddress = 3U, /*!< AES CTR w/o address binding mode */ 0067 kIEE_ModeAesCTRkeystream = 4U /*!< AES CTR keystream only */ 0068 } iee_aes_mode_t; 0069 0070 /*! @brief IEE AES key size. */ 0071 typedef enum _iee_aes_key_size 0072 { 0073 kIEE_AesCTR128XTS256 = 0U, /*!< AES 128 bits (CTR), 256 bits (XTS) */ 0074 kIEE_AesCTR256XTS512 = 1U /*!< AES 256 bits (CTR), 512 bits (XTS) */ 0075 } iee_aes_key_size_t; 0076 0077 /*! @brief IEE AES ke number. */ 0078 typedef enum _iee_aes_key_num 0079 { 0080 kIEE_AesKey1 = 1U, /*!< AES Key 1 */ 0081 kIEE_AesKey2 = 2U /*!< AES Key 2 */ 0082 } iee_aes_key_num_t; 0083 0084 /*! @brief IEE configuration structure. */ 0085 typedef struct _iee_config 0086 { 0087 iee_aes_bypass_t bypass; /*!< AES encryption/decryption bypass */ 0088 iee_aes_mode_t mode; /*!< AES mode */ 0089 iee_aes_key_size_t keySize; /*!< size of AES key */ 0090 uint32_t pageOffset; /*!< Offset to physical memory location from IEE start address */ 0091 } iee_config_t; 0092 0093 /******************************************************************************* 0094 * API 0095 ******************************************************************************/ 0096 #if defined(__cplusplus) 0097 extern "C" { 0098 #endif 0099 0100 /*! 0101 * @brief Resets IEE module to factory default values. 0102 * 0103 * This function performs hardware reset of IEE module. Attributes and keys of all regions are cleared. 0104 * 0105 * @param base IEER peripheral address. 0106 */ 0107 void IEE_Init(IEE_Type *base); 0108 0109 /*! 0110 * @brief Loads default values to the IEE configuration structure. 0111 * 0112 * Loads default values to the IEE region configuration structure. The default values are as follows. 0113 * @code 0114 * config->bypass = kIEE_AesUseMdField; 0115 * config->mode = kIEE_ModeNone; 0116 * config->keySize = kIEE_AesCTR128XTS256; 0117 * config->pageOffset = 0U; 0118 * @endcode 0119 * 0120 * @param config Configuration for the selected IEE region. 0121 */ 0122 void IEE_GetDefaultConfig(iee_config_t *config); 0123 0124 /*! 0125 * @brief Sets the IEE module according to the configuration structure. 0126 * 0127 * This function configures IEE region according to configuration structure. 0128 * 0129 * @param base IEE peripheral address. 0130 * @param region Selection of the IEE region to be configured. 0131 * @param config Configuration for the selected IEE region. 0132 */ 0133 void IEE_SetRegionConfig(IEE_Type *base, iee_region_t region, iee_config_t *config); 0134 0135 /*! 0136 * @brief Sets the IEE module key. 0137 * 0138 * This function sets specified AES key for the given region. 0139 * 0140 * @param base IEE peripheral address. 0141 * @param region Selection of the IEE region to be configured. 0142 * @param keyNum Selection of AES KEY1 or KEY2. 0143 * @param key AES key. 0144 * @param keySize Size of AES key. 0145 */ 0146 status_t IEE_SetRegionKey( 0147 IEE_Type *base, iee_region_t region, iee_aes_key_num_t keyNum, const uint8_t *key, size_t keySize); 0148 0149 /*! 0150 * @brief Computes IEE offset to be set for specifed memory location. 0151 * 0152 * This function calculates offset that must be set for IEE region to access physical memory location. 0153 * 0154 * @param addressIee Address of IEE peripheral. 0155 * @param addressMemory Address of physical memory location. 0156 */ 0157 static inline uint32_t IEE_GetOffset(uint32_t addressIee, uint32_t addressMemory) 0158 { 0159 return (addressMemory - addressIee) >> 12; 0160 } 0161 0162 /*! 0163 * @brief Lock the IEE region configuration. 0164 * 0165 * This function locks IEE region registers for Key, Offset and Attribute. 0166 * Only system reset can clear the Lock bit. 0167 * 0168 * @param base IEE peripheral address. 0169 * @param region Selection of the IEE region to be locked. 0170 */ 0171 void IEE_LockRegionConfig(IEE_Type *base, iee_region_t region); 0172 0173 #if defined(__cplusplus) 0174 } 0175 #endif 0176 0177 /*! 0178 *@} 0179 */ 0180 0181 #endif /* _FSL_IEE_H_ */
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