drivers/gpt/fsl_gpt.h

0001 /*
0002  * Copyright (c) 2015, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2020 NXP
0004  * All rights reserved.
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #ifndef _FSL_GPT_H_
0010 #define _FSL_GPT_H_
0011
0012 #include "fsl_common.h"
0013
0014 /*!
0015  * @addtogroup gpt
0016  * @{
0017  */
0018
0019 /*******************************************************************************
0020  * Definitions
0021  ******************************************************************************/
0022
0023 /*! @name Driver version */
0024 /*@{*/
0025 #define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
0026 /*@}*/
0027
0028 /*!
0029  * @brief List of clock sources
0030  * @note Actual number of clock sources is SoC dependent
0031  */
0032 typedef enum _gpt_clock_source
0033 {
0034     kGPT_ClockSource_Off      = 0U, /*!< GPT Clock Source Off.*/
0035     kGPT_ClockSource_Periph   = 1U, /*!< GPT Clock Source from Peripheral Clock.*/
0036     kGPT_ClockSource_HighFreq = 2U, /*!< GPT Clock Source from High Frequency Reference Clock.*/
0037     kGPT_ClockSource_Ext      = 3U, /*!< GPT Clock Source from external pin.*/
0038     kGPT_ClockSource_LowFreq  = 4U, /*!< GPT Clock Source from Low Frequency Reference Clock.*/
0039     kGPT_ClockSource_Osc      = 5U, /*!< GPT Clock Source from Crystal oscillator.*/
0040 } gpt_clock_source_t;
0041
0042 /*! @brief List of input capture channel number. */
0043 typedef enum _gpt_input_capture_channel
0044 {
0045     kGPT_InputCapture_Channel1 = 0U, /*!< GPT Input Capture Channel1.*/
0046     kGPT_InputCapture_Channel2 = 1U, /*!< GPT Input Capture Channel2.*/
0047 } gpt_input_capture_channel_t;
0048
0049 /*! @brief List of input capture operation mode. */
0050 typedef enum _gpt_input_operation_mode
0051 {
0052     kGPT_InputOperation_Disabled = 0U, /*!< Don't capture.*/
0053     kGPT_InputOperation_RiseEdge = 1U, /*!< Capture on rising edge of input pin.*/
0054     kGPT_InputOperation_FallEdge = 2U, /*!< Capture on falling edge of input pin.*/
0055     kGPT_InputOperation_BothEdge = 3U, /*!< Capture on both edges of input pin.*/
0056 } gpt_input_operation_mode_t;
0057
0058 /*! @brief List of output compare channel number. */
0059 typedef enum _gpt_output_compare_channel
0060 {
0061     kGPT_OutputCompare_Channel1 = 0U, /*!< Output Compare Channel1.*/
0062     kGPT_OutputCompare_Channel2 = 1U, /*!< Output Compare Channel2.*/
0063     kGPT_OutputCompare_Channel3 = 2U, /*!< Output Compare Channel3.*/
0064 } gpt_output_compare_channel_t;
0065
0066 /*! @brief List of output compare operation mode. */
0067 typedef enum _gpt_output_operation_mode
0068 {
0069     kGPT_OutputOperation_Disconnected = 0U, /*!< Don't change output pin.*/
0070     kGPT_OutputOperation_Toggle       = 1U, /*!< Toggle output pin.*/
0071     kGPT_OutputOperation_Clear        = 2U, /*!< Set output pin low.*/
0072     kGPT_OutputOperation_Set          = 3U, /*!< Set output pin high.*/
0073     kGPT_OutputOperation_Activelow    = 4U, /*!< Generate a active low pulse on output pin.*/
0074 } gpt_output_operation_mode_t;
0075
0076 /*! @brief List of GPT interrupts */
0077 typedef enum _gpt_interrupt_enable
0078 {
0079     kGPT_OutputCompare1InterruptEnable = GPT_IR_OF1IE_MASK, /*!< Output Compare Channel1 interrupt enable*/
0080     kGPT_OutputCompare2InterruptEnable = GPT_IR_OF2IE_MASK, /*!< Output Compare Channel2 interrupt enable*/
0081     kGPT_OutputCompare3InterruptEnable = GPT_IR_OF3IE_MASK, /*!< Output Compare Channel3 interrupt enable*/
0082     kGPT_InputCapture1InterruptEnable  = GPT_IR_IF1IE_MASK, /*!< Input Capture Channel1 interrupt enable*/
0083     kGPT_InputCapture2InterruptEnable  = GPT_IR_IF2IE_MASK, /*!< Input Capture Channel1 interrupt enable*/
0084     kGPT_RollOverFlagInterruptEnable   = GPT_IR_ROVIE_MASK, /*!< Counter rolled over interrupt enable*/
0085 } gpt_interrupt_enable_t;
0086
0087 /*! @brief Status flag. */
0088 typedef enum _gpt_status_flag
0089 {
0090     kGPT_OutputCompare1Flag = GPT_SR_OF1_MASK, /*!< Output compare channel 1 event.*/
0091     kGPT_OutputCompare2Flag = GPT_SR_OF2_MASK, /*!< Output compare channel 2 event.*/
0092     kGPT_OutputCompare3Flag = GPT_SR_OF3_MASK, /*!< Output compare channel 3 event.*/
0093     kGPT_InputCapture1Flag  = GPT_SR_IF1_MASK, /*!< Input Capture channel 1 event.*/
0094     kGPT_InputCapture2Flag  = GPT_SR_IF2_MASK, /*!< Input Capture channel 2 event.*/
0095     kGPT_RollOverFlag       = GPT_SR_ROV_MASK, /*!< Counter reaches maximum value and rolled over to 0 event.*/
0096 } gpt_status_flag_t;
0097
0098 /*! @brief Structure to configure the running mode. */
0099 typedef struct _gpt_init_config
0100 {
0101     gpt_clock_source_t clockSource; /*!< clock source for GPT module. */
0102     uint32_t divider;               /*!< clock divider (prescaler+1) from clock source to counter. */
0103     bool enableFreeRun;             /*!< true: FreeRun mode, false: Restart mode. */
0104     bool enableRunInWait;           /*!< GPT enabled in wait mode. */
0105     bool enableRunInStop;           /*!< GPT enabled in stop mode. */
0106     bool enableRunInDoze;           /*!< GPT enabled in doze mode. */
0107     bool enableRunInDbg;            /*!< GPT enabled in debug mode. */
0108     bool enableMode;                /*!< true:  counter reset to 0 when enabled;
0109                                     false: counter retain its value when enabled. */
0110 } gpt_config_t;
0111
0112 /*******************************************************************************
0113  * API
0114  ******************************************************************************/
0115
0116 #if defined(__cplusplus)
0117 extern "C" {
0118 #endif
0119
0120 /*!
0121  * @name Initialization and deinitialization
0122  * @{
0123  */
0124
0125 /*!
0126  * @brief Initialize GPT to reset state and initialize running mode.
0127  *
0128  * @param base GPT peripheral base address.
0129  * @param initConfig GPT mode setting configuration.
0130  */
0131 void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig);
0132
0133 /*!
0134  * @brief Disables the module and gates the GPT clock.
0135  *
0136  * @param base GPT peripheral base address.
0137  */
0138 void GPT_Deinit(GPT_Type *base);
0139
0140 /*!
0141  * @brief Fills in the GPT configuration structure with default settings.
0142  *
0143  * The default values are:
0144  * @code
0145  *    config->clockSource = kGPT_ClockSource_Periph;
0146  *    config->divider = 1U;
0147  *    config->enableRunInStop = true;
0148  *    config->enableRunInWait = true;
0149  *    config->enableRunInDoze = false;
0150  *    config->enableRunInDbg = false;
0151  *    config->enableFreeRun = false;
0152  *    config->enableMode  = true;
0153  * @endcode
0154  * @param config Pointer to the user configuration structure.
0155  */
0156 void GPT_GetDefaultConfig(gpt_config_t *config);
0157
0158 /*!
0159  * @name Software Reset
0160  * @{
0161  */
0162
0163 /*!
0164  * @brief Software reset of GPT module.
0165  *
0166  * @param base GPT peripheral base address.
0167  */
0168 static inline void GPT_SoftwareReset(GPT_Type *base)
0169 {
0170     base->CR |= GPT_CR_SWR_MASK;
0171     /* Wait reset finished. */
0172     while ((base->CR & GPT_CR_SWR_MASK) == GPT_CR_SWR_MASK)
0173     {
0174     }
0175 }
0176
0177 /*!
0178  * @name Clock source and frequency control
0179  * @{
0180  */
0181
0182 /*!
0183  * @brief Set clock source of GPT.
0184  *
0185  * @param base GPT peripheral base address.
0186  * @param gptClkSource Clock source (see @ref gpt_clock_source_t typedef enumeration).
0187  */
0188 static inline void GPT_SetClockSource(GPT_Type *base, gpt_clock_source_t gptClkSource)
0189 {
0190     if (gptClkSource == kGPT_ClockSource_Osc)
0191     {
0192         base->CR = (base->CR & ~GPT_CR_CLKSRC_MASK) | GPT_CR_EN_24M_MASK | GPT_CR_CLKSRC(gptClkSource);
0193     }
0194     else
0195     {
0196         base->CR = (base->CR & ~(GPT_CR_CLKSRC_MASK | GPT_CR_EN_24M_MASK)) | GPT_CR_CLKSRC(gptClkSource);
0197     }
0198 }
0199
0200 /*!
0201  * @brief Get clock source of GPT.
0202  *
0203  * @param base GPT peripheral base address.
0204  * @return clock source (see @ref gpt_clock_source_t typedef enumeration).
0205  */
0206 static inline gpt_clock_source_t GPT_GetClockSource(GPT_Type *base)
0207 {
0208     return (gpt_clock_source_t)(uint8_t)((base->CR & GPT_CR_CLKSRC_MASK) >> GPT_CR_CLKSRC_SHIFT);
0209 }
0210
0211 /*!
0212  * @brief Set pre scaler of GPT.
0213  *
0214  * @param base GPT peripheral base address.
0215  * @param divider Divider of GPT (1-4096).
0216  */
0217 static inline void GPT_SetClockDivider(GPT_Type *base, uint32_t divider)
0218 {
0219     assert(divider - 1U <= GPT_PR_PRESCALER_MASK);
0220
0221     base->PR = (base->PR & ~GPT_PR_PRESCALER_MASK) | GPT_PR_PRESCALER(divider - 1U);
0222 }
0223
0224 /*!
0225  * @brief Get clock divider in GPT module.
0226  *
0227  * @param base GPT peripheral base address.
0228  * @return clock divider in GPT module (1-4096).
0229  */
0230 static inline uint32_t GPT_GetClockDivider(GPT_Type *base)
0231 {
0232     return ((base->PR & GPT_PR_PRESCALER_MASK) >> GPT_PR_PRESCALER_SHIFT) + 1U;
0233 }
0234
0235 /*!
0236  * @brief OSC 24M pre-scaler before selected by clock source.
0237  *
0238  * @param base GPT peripheral base address.
0239  * @param divider OSC Divider(1-16).
0240  */
0241 static inline void GPT_SetOscClockDivider(GPT_Type *base, uint32_t divider)
0242 {
0243     assert(divider - 1U <= (GPT_PR_PRESCALER24M_MASK >> GPT_PR_PRESCALER24M_SHIFT));
0244
0245     base->PR = (base->PR & ~GPT_PR_PRESCALER24M_MASK) | GPT_PR_PRESCALER24M(divider - 1U);
0246 }
0247
0248 /*!
0249  * @brief Get OSC 24M clock divider in GPT module.
0250  *
0251  * @param base GPT peripheral base address.
0252  * @return OSC clock divider in GPT module (1-16).
0253  */
0254 static inline uint32_t GPT_GetOscClockDivider(GPT_Type *base)
0255 {
0256     return ((base->PR & GPT_PR_PRESCALER24M_MASK) >> GPT_PR_PRESCALER24M_SHIFT) + 1U;
0257 }
0258
0259 /*! @}*/
0260
0261 /*!
0262  * @name Timer Start and Stop
0263  * @{
0264  */
0265 /*!
0266  * @brief Start GPT timer.
0267  *
0268  * @param base GPT peripheral base address.
0269  */
0270 static inline void GPT_StartTimer(GPT_Type *base)
0271 {
0272     base->CR |= GPT_CR_EN_MASK;
0273 }
0274
0275 /*!
0276  * @brief Stop GPT timer.
0277  *
0278  * @param base GPT peripheral base address.
0279  */
0280 static inline void GPT_StopTimer(GPT_Type *base)
0281 {
0282     base->CR &= ~GPT_CR_EN_MASK;
0283 }
0284
0285 /*!
0286  * @name Read the timer period
0287  * @{
0288  */
0289
0290 /*!
0291  * @brief Reads the current GPT counting value.
0292  *
0293  * @param base GPT peripheral base address.
0294  * @return Current GPT counter value.
0295  */
0296 static inline uint32_t GPT_GetCurrentTimerCount(GPT_Type *base)
0297 {
0298     return base->CNT;
0299 }
0300
0301 /*@}*/
0302
0303 /*!
0304  * @name GPT Input/Output Signal Control
0305  * @{
0306  */
0307
0308 /*!
0309  * @brief Set GPT operation mode of input capture channel.
0310  *
0311  * @param base GPT peripheral base address.
0312  * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration).
0313  * @param mode GPT input capture operation mode (see @ref gpt_input_operation_mode_t typedef enumeration).
0314  */
0315 static inline void GPT_SetInputOperationMode(GPT_Type *base,
0316                                              gpt_input_capture_channel_t channel,
0317                                              gpt_input_operation_mode_t mode)
0318 {
0319     assert(channel <= kGPT_InputCapture_Channel2);
0320
0321     base->CR =
0322         (base->CR & ~(GPT_CR_IM1_MASK << ((uint32_t)channel * 2UL))) | (GPT_CR_IM1(mode) << ((uint32_t)channel * 2UL));
0323 }
0324
0325 /*!
0326  * @brief Get GPT operation mode of input capture channel.
0327  *
0328  * @param base GPT peripheral base address.
0329  * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration).
0330  * @return GPT input capture operation mode (see @ref gpt_input_operation_mode_t typedef enumeration).
0331  */
0332 static inline gpt_input_operation_mode_t GPT_GetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel)
0333 {
0334     assert(channel <= kGPT_InputCapture_Channel2);
0335
0336     return (gpt_input_operation_mode_t)(uint8_t)((base->CR >> (GPT_CR_IM1_SHIFT + (uint32_t)channel * 2UL)) &
0337                                                  (GPT_CR_IM1_MASK >> GPT_CR_IM1_SHIFT));
0338 }
0339
0340 /*!
0341  * @brief Get GPT input capture value of certain channel.
0342  *
0343  * @param base GPT peripheral base address.
0344  * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration).
0345  * @return GPT input capture value.
0346  */
0347 static inline uint32_t GPT_GetInputCaptureValue(GPT_Type *base, gpt_input_capture_channel_t channel)
0348 {
0349     assert(channel <= kGPT_InputCapture_Channel2);
0350
0351     return base->ICR[(uint32_t)channel];
0352 }
0353
0354 /*!
0355  * @brief Set GPT operation mode of output compare channel.
0356  *
0357  * @param base GPT peripheral base address.
0358  * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration).
0359  * @param mode GPT output operation mode (see @ref gpt_output_operation_mode_t typedef enumeration).
0360  */
0361 static inline void GPT_SetOutputOperationMode(GPT_Type *base,
0362                                               gpt_output_compare_channel_t channel,
0363                                               gpt_output_operation_mode_t mode)
0364 {
0365     assert(channel <= kGPT_OutputCompare_Channel3);
0366
0367     base->CR =
0368         (base->CR & ~(GPT_CR_OM1_MASK << ((uint32_t)channel * 3UL))) | (GPT_CR_OM1(mode) << ((uint32_t)channel * 3UL));
0369 }
0370
0371 /*!
0372  * @brief Get GPT operation mode of output compare channel.
0373  *
0374  * @param base GPT peripheral base address.
0375  * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration).
0376  * @return GPT output operation mode (see @ref gpt_output_operation_mode_t typedef enumeration).
0377  */
0378 static inline gpt_output_operation_mode_t GPT_GetOutputOperationMode(GPT_Type *base,
0379                                                                      gpt_output_compare_channel_t channel)
0380 {
0381     assert(channel <= kGPT_OutputCompare_Channel3);
0382
0383     return (gpt_output_operation_mode_t)(uint8_t)((base->CR >> (GPT_CR_OM1_SHIFT + (uint32_t)channel * 3UL)) &
0384                                                   (GPT_CR_OM1_MASK >> GPT_CR_OM1_SHIFT));
0385 }
0386
0387 /*!
0388  * @brief Set GPT output compare value of output compare channel.
0389  *
0390  * @param base GPT peripheral base address.
0391  * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration).
0392  * @param value GPT output compare value.
0393  */
0394 static inline void GPT_SetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel, uint32_t value)
0395 {
0396     assert(channel <= kGPT_OutputCompare_Channel3);
0397
0398     base->OCR[(uint32_t)channel] = value;
0399 }
0400
0401 /*!
0402  * @brief Get GPT output compare value of output compare channel.
0403  *
0404  * @param base GPT peripheral base address.
0405  * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration).
0406  * @return GPT output compare value.
0407  */
0408 static inline uint32_t GPT_GetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel)
0409 {
0410     assert(channel <= kGPT_OutputCompare_Channel3);
0411
0412     return base->OCR[(uint32_t)channel];
0413 }
0414
0415 /*!
0416  * @brief Force GPT output action on output compare channel, ignoring comparator.
0417  *
0418  * @param base GPT peripheral base address.
0419  * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration).
0420  */
0421 static inline void GPT_ForceOutput(GPT_Type *base, gpt_output_compare_channel_t channel)
0422 {
0423     assert(channel <= kGPT_OutputCompare_Channel3);
0424
0425     base->CR |= (GPT_CR_FO1_MASK << (uint32_t)channel);
0426 }
0427
0428 /*@}*/
0429
0430 /*!
0431  * @name GPT Interrupt and Status Interface
0432  * @{
0433  */
0434
0435 /*!
0436  * @brief Enables the selected GPT interrupts.
0437  *
0438  * @param base GPT peripheral base address.
0439  * @param mask The interrupts to enable. This is a logical OR of members of the
0440  *             enumeration ::gpt_interrupt_enable_t
0441  */
0442 static inline void GPT_EnableInterrupts(GPT_Type *base, uint32_t mask)
0443 {
0444     base->IR |= mask;
0445 }
0446
0447 /*!
0448  * @brief Disables the selected GPT interrupts.
0449  *
0450  * @param base    GPT peripheral base address
0451  * @param mask    The interrupts to disable. This is a logical OR of members of the
0452  *                enumeration ::gpt_interrupt_enable_t
0453  */
0454 static inline void GPT_DisableInterrupts(GPT_Type *base, uint32_t mask)
0455 {
0456     base->IR &= ~mask;
0457 }
0458
0459 /*!
0460  * @brief Gets the enabled GPT interrupts.
0461  *
0462  * @param base    GPT peripheral base address
0463  *
0464  * @return The enabled interrupts. This is the logical OR of members of the
0465  *         enumeration ::gpt_interrupt_enable_t
0466  */
0467 static inline uint32_t GPT_GetEnabledInterrupts(GPT_Type *base)
0468 {
0469     return (base->IR & (GPT_IR_OF1IE_MASK | GPT_IR_OF2IE_MASK | GPT_IR_OF3IE_MASK | GPT_IR_IF1IE_MASK |
0470                         GPT_IR_IF2IE_MASK | GPT_IR_ROVIE_MASK));
0471 }
0472
0473 /*!
0474  * @name Status Interface
0475  * @{
0476  */
0477
0478 /*!
0479  * @brief Get GPT status flags.
0480  *
0481  * @param base GPT peripheral base address.
0482  * @param flags GPT status flag mask (see @ref gpt_status_flag_t for bit definition).
0483  * @return GPT status, each bit represents one status flag.
0484  */
0485 static inline uint32_t GPT_GetStatusFlags(GPT_Type *base, gpt_status_flag_t flags)
0486 {
0487     return base->SR & (uint32_t)flags;
0488 }
0489
0490 /*!
0491  * @brief Clears the GPT status flags.
0492  *
0493  * @param base GPT peripheral base address.
0494  * @param flags GPT status flag mask (see @ref gpt_status_flag_t for bit definition).
0495  */
0496 static inline void GPT_ClearStatusFlags(GPT_Type *base, gpt_status_flag_t flags)
0497 {
0498     base->SR = (uint32_t)flags;
0499 }
0500
0501 /*@}*/
0502
0503 #if defined(__cplusplus)
0504 }
0505 #endif
0506
0507 /*! @}*/
0508
0509 #endif /* _FSL_GPT_H_ */