drivers/gpc_1/fsl_gpc.h

0001 /*
0002  * Copyright (c) 2016, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2019 NXP
0004  * All rights reserved.
0005  *
0006  *
0007  * SPDX-License-Identifier: BSD-3-Clause
0008  */
0009
0010 #ifndef _FSL_GPC_H_
0011 #define _FSL_GPC_H_
0012
0013 #include "fsl_common.h"
0014
0015 /*!
0016  * @addtogroup gpc
0017  * @{
0018  */
0019
0020 /*******************************************************************************
0021  * Definitions
0022  ******************************************************************************/
0023
0024 /*! @name Driver version */
0025 /*@{*/
0026 /*! @brief GPC driver version 2.1.1. */
0027 #define FSL_GPC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
0028 /*@}*/
0029
0030 #if defined(__cplusplus)
0031 extern "C" {
0032 #endif
0033
0034 /*******************************************************************************
0035  * API
0036  ******************************************************************************/
0037
0038 #if (defined(FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM) && FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM)
0039 /*!
0040  * @brief Allow all the IRQ/Events within the charge of GPC.
0041  *
0042  * @param base GPC peripheral base address.
0043  */
0044 static inline void GPC_AllowIRQs(GPC_Type *base)
0045 {
0046     base->CNTR &= ~GPC_CNTR_GPCIRQM_MASK; /* Events would not be masked. */
0047 }
0048
0049 /*!
0050  * @brief Disallow all the IRQ/Events within the charge of GPC.
0051  *
0052  * @param base GPC peripheral base address.
0053  */
0054 static inline void GPC_DisallowIRQs(GPC_Type *base)
0055 {
0056     base->CNTR |= GPC_CNTR_GPCIRQM_MASK; /* Mask all the events. */
0057 }
0058 #endif /* FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM */
0059
0060 /*!
0061  * @brief Enable the IRQ.
0062  *
0063  * @param base GPC peripheral base address.
0064  * @param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms.
0065  */
0066 void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId);
0067
0068 /*!
0069  * @brief Disable the IRQ.
0070  *
0071  * @param base GPC peripheral base address.
0072  * @param irqId ID number of IRQ to be disabled, available range is 32-159. 0-31 is available in some platforms.
0073  */
0074 void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId);
0075
0076 /*!
0077  * @brief Get the IRQ/Event flag.
0078  *
0079  * @param base GPC peripheral base address.
0080  * @param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms.
0081  * @return Indicated IRQ/Event is asserted or not.
0082  */
0083 bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId);
0084
0085 #if (defined(FSL_FEATURE_GPC_HAS_CNTR_L2PGE) && FSL_FEATURE_GPC_HAS_CNTR_L2PGE)
0086 /*!
0087  * @brief L2 Cache Power Gate Enable
0088  *
0089  * This function configures the L2 cache if it will keep power when in low power mode.
0090  * When the L2 cache power is OFF, L2 cache will be power down once when CPU core is power down
0091  * and will be hardware invalidated automatically when CPU core is re-power up.
0092  * When the L2 cache power is ON, L2 cache will keep power on even if CPU core is power down and
0093  * will not be hardware invalidated.
0094  * When CPU core is re-power up, the default setting is OFF.
0095  *
0096  * @param base GPC peripheral base address.
0097  * @param enable Enable the request or not.
0098  */
0099 static inline void GPC_RequestL2CachePowerDown(GPC_Type *base, bool enable)
0100 {
0101     if (enable)
0102     {
0103         base->CNTR |= GPC_CNTR_L2_PGE_MASK; /* OFF. */
0104     }
0105     else
0106     {
0107         base->CNTR &= ~GPC_CNTR_L2_PGE_MASK; /* ON. */
0108     }
0109 }
0110 #endif /* FSL_FEATURE_GPC_HAS_CNTR_L2PGE */
0111
0112 #if (defined(FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE) && FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE)
0113 /*!
0114  * @brief FLEXRAM PDRAM0 Power Gate Enable
0115  *
0116  * This function configures the FLEXRAM PDRAM0 if it will keep power when cpu core is power down.
0117  * When the PDRAM0 Power is 1, PDRAM0 will be power down once when CPU core is power down.
0118  * When the PDRAM0 Power is 0, PDRAM0 will keep power on even if CPU core is power down.
0119  * When CPU core is re-power up, the default setting is 1.
0120  *
0121  * @param base GPC peripheral base address.
0122  * @param enable Enable the request or not.
0123  */
0124 static inline void GPC_RequestPdram0PowerDown(GPC_Type *base, bool enable)
0125 {
0126     if (enable)
0127     {
0128         base->CNTR |= GPC_CNTR_PDRAM0_PGE_MASK; /* OFF. */
0129     }
0130     else
0131     {
0132         base->CNTR &= ~GPC_CNTR_PDRAM0_PGE_MASK; /* ON. */
0133     }
0134 }
0135 #endif /* FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE */
0136
0137 #if (defined(FSL_FEATURE_GPC_HAS_CNTR_VADC) && FSL_FEATURE_GPC_HAS_CNTR_VADC)
0138 /*!
0139  * @brief VADC power down.
0140  *
0141  * This function requests the VADC power down.
0142  *
0143  * @param base GPC peripheral base address.
0144  * @param enable Enable the request or not.
0145  */
0146 static inline void GPC_RequestVADCPowerDown(GPC_Type *base, bool enable)
0147 {
0148     if (enable)
0149     {
0150         base->CNTR &= ~GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC power down. */
0151     }
0152     else
0153     {
0154         base->CNTR |= GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC not power down. */
0155     }
0156 }
0157
0158 /*!
0159  * @brief Checks if the VADC is power off.
0160  *
0161  * @param base GPC peripheral base address.
0162  * @return Whether the VADC is power off or not.
0163  */
0164 static inline bool GPC_GetVADCPowerDownFlag(GPC_Type *base)
0165 {
0166     return (GPC_CNTR_VADC_ANALOG_OFF_MASK == (GPC_CNTR_VADC_ANALOG_OFF_MASK & base->CNTR));
0167 }
0168 #endif /* FSL_FEATURE_GPC_HAS_CNTR_VADC */
0169
0170 #if (defined(FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR) && FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR)
0171 /*!
0172  * @brief Checks if the DVFS0 is requesting for frequency/voltage update.
0173  *
0174  * @param base GPC peripheral base address.
0175  * @return Whether the DVFS0 is requesting for frequency/voltage update.
0176  */
0177 static inline bool GPC_HasDVFS0ChangeRequest(GPC_Type *base)
0178 {
0179     return (GPC_CNTR_DVFS0CR_MASK == (GPC_CNTR_DVFS0CR_MASK & base->CNTR));
0180 }
0181 #endif /* FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR */
0182
0183 #if (defined(FSL_FEATURE_GPC_HAS_CNTR_DISPLAY) && FSL_FEATURE_GPC_HAS_CNTR_DISPLAY)
0184 /*!
0185  * @brief Requests the display power switch sequence.
0186  *
0187  * @param base GPC peripheral base address.
0188  * @param enable Enable the power on sequence, or the power down sequence.
0189  */
0190 static inline void GPC_RequestDisplayPowerOn(GPC_Type *base, bool enable)
0191 {
0192     if (enable)
0193     {
0194         base->CNTR |= GPC_CNTR_DISPLAY_PUP_REQ_MASK; /* Power on sequence. */
0195     }
0196     else
0197     {
0198         base->CNTR |= GPC_CNTR_DISPLAY_PDN_REQ_MASK; /* Power down sequence. */
0199     }
0200 }
0201 #endif /* FSL_FEATURE_GPC_HAS_CNTR_DISPLAY */
0202
0203 /*!
0204  * @brief Requests the MEGA power switch sequence.
0205  *
0206  * @param base GPC peripheral base address.
0207  * @param enable Enable the power on sequence, or the power down sequence.
0208  */
0209 static inline void GPC_RequestMEGAPowerOn(GPC_Type *base, bool enable)
0210 {
0211     if (enable)
0212     {
0213         base->CNTR |= GPC_CNTR_MEGA_PUP_REQ_MASK; /* Power on sequence. */
0214     }
0215     else
0216     {
0217         base->CNTR |= GPC_CNTR_MEGA_PDN_REQ_MASK; /* Power down sequence. */
0218     }
0219 }
0220
0221 /*!
0222  * @}
0223  */
0224
0225 #if defined(__cplusplus)
0226 }
0227 #endif
0228 /*!
0229  * @}
0230  */
0231 #endif /* _FSL_GPC_H_ */