drivers/gpc_1/fsl_gpc.c

0001 /*
0002  * Copyright (c) 2016, Freescale Semiconductor, Inc.
0003  * Copyright 2016-2019 NXP
0004  * All rights reserved.
0005  *
0006  *
0007  * SPDX-License-Identifier: BSD-3-Clause
0008  */
0009
0010 #include "fsl_gpc.h"
0011
0012 /* Component ID definition, used by tools. */
0013 #ifndef FSL_COMPONENT_ID
0014 #define FSL_COMPONENT_ID "platform.drivers.gpc_1"
0015 #endif
0016
0017 /*!
0018  * brief Enable the IRQ.
0019  *
0020  * param base GPC peripheral base address.
0021  * param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms.
0022  */
0023 void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId)
0024 {
0025     uint32_t irqRegNum      = irqId / 32U;
0026     uint32_t irqRegShiftNum = irqId % 32U;
0027
0028     assert(irqRegNum <= GPC_IMR_COUNT);
0029
0030 #if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31)
0031     if (irqRegNum == GPC_IMR_COUNT)
0032     {
0033         base->IMR5 &= ~(1UL << irqRegShiftNum);
0034     }
0035     else
0036     {
0037         base->IMR[irqRegNum] &= ~(1UL << irqRegShiftNum);
0038     }
0039 #else
0040     assert(irqRegNum > 0U);
0041     base->IMR[irqRegNum - 1UL] &= ~(1UL << irqRegShiftNum);
0042 #endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
0043 }
0044
0045 /*!
0046  * brief Disable the IRQ.
0047  *
0048  * param base GPC peripheral base address.
0049  * param irqId ID number of IRQ to be disabled, available range is 32-159. 0-31 is available in some platforms.
0050  */
0051 void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId)
0052 {
0053     uint32_t irqRegNum      = irqId / 32U;
0054     uint32_t irqRegShiftNum = irqId % 32U;
0055
0056     assert(irqRegNum <= GPC_IMR_COUNT);
0057
0058 #if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31)
0059     if (irqRegNum == GPC_IMR_COUNT)
0060     {
0061         base->IMR5 |= (1UL << irqRegShiftNum);
0062     }
0063     else
0064     {
0065         base->IMR[irqRegNum] |= (1UL << irqRegShiftNum);
0066     }
0067 #else
0068     assert(irqRegNum > 0U);
0069     base->IMR[irqRegNum - 1UL] |= (1UL << irqRegShiftNum);
0070 #endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
0071 }
0072
0073 /*!
0074  * brief Get the IRQ/Event flag.
0075  *
0076  * param base GPC peripheral base address.
0077  * param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms.
0078  * return Indicated IRQ/Event is asserted or not.
0079  */
0080 bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId)
0081 {
0082     uint32_t irqRegNum      = irqId / 32U;
0083     uint32_t irqRegShiftNum = irqId % 32U;
0084     uint32_t ret;
0085
0086     assert(irqRegNum <= GPC_IMR_COUNT);
0087
0088 #if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31)
0089     if (irqRegNum == GPC_IMR_COUNT)
0090     {
0091         ret = base->ISR5 & (1UL << irqRegShiftNum);
0092     }
0093     else
0094     {
0095         ret = base->ISR[irqRegNum] & (1UL << irqRegShiftNum);
0096     }
0097 #else
0098     assert(irqRegNum > 0U);
0099     ret = base->ISR[irqRegNum - 1UL] & (1UL << irqRegShiftNum);
0100 #endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
0101
0102     return (1UL << irqRegShiftNum) == ret;
0103 }