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0001 /* 0002 * Copyright (c) 2016, Freescale Semiconductor, Inc. 0003 * Copyright 2016-2022 NXP 0004 * All rights reserved. 0005 * 0006 * SPDX-License-Identifier: BSD-3-Clause 0007 */ 0008 0009 #ifndef __FSL_FLEXSPI_H_ 0010 #define __FSL_FLEXSPI_H_ 0011 0012 #include <stddef.h> 0013 #include "fsl_device_registers.h" 0014 #include "fsl_common.h" 0015 0016 /*! 0017 * @addtogroup flexspi 0018 * @{ 0019 */ 0020 0021 /******************************************************************************* 0022 * Definitions 0023 ******************************************************************************/ 0024 0025 /*! @name Driver version */ 0026 /*@{*/ 0027 /*! @brief FLEXSPI driver version. */ 0028 #define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) 0029 /*@}*/ 0030 0031 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0) 0032 0033 /*! @brief Formula to form FLEXSPI instructions in LUT table. */ 0034 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 0035 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 0036 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 0037 0038 /*! @brief Status structure of FLEXSPI.*/ 0039 enum 0040 { 0041 kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */ 0042 kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout 0043 error occurred during FLEXSPI transfer. */ 0044 kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), /*!< IP command Sequence execution 0045 timeout error occurred during FLEXSPI transfer. */ 0046 kStatus_FLEXSPI_IpCommandGrantTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 3), /*!< IP command grant timeout error 0047 occurred during FLEXSPI transfer. */ 0048 }; 0049 0050 /*! @brief CMD definition of FLEXSPI, use to form LUT instruction, _flexspi_command. */ 0051 enum 0052 { 0053 kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */ 0054 kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */ 0055 kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */ 0056 kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */ 0057 kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */ 0058 kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */ 0059 kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */ 0060 kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */ 0061 kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */ 0062 kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */ 0063 kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */ 0064 kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */ 0065 kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/ 0066 kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller, 0067 dummy cycles decided by RWDS. */ 0068 kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */ 0069 kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */ 0070 kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */ 0071 kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */ 0072 kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */ 0073 kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */ 0074 kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */ 0075 kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */ 0076 kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */ 0077 kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */ 0078 kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */ 0079 kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/ 0080 kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller, 0081 dummy cycles decided by RWDS. */ 0082 kFLEXSPI_Command_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as the 0083 instruction start pointer for next sequence */ 0084 }; 0085 0086 /*! @brief pad definition of FLEXSPI, use to form LUT instruction. */ 0087 typedef enum _flexspi_pad 0088 { 0089 kFLEXSPI_1PAD = 0x00U, /*!< Transmit command/address and transmit/receive data only through DATA0/DATA1. */ 0090 kFLEXSPI_2PAD = 0x01U, /*!< Transmit command/address and transmit/receive data only through DATA[1:0]. */ 0091 kFLEXSPI_4PAD = 0x02U, /*!< Transmit command/address and transmit/receive data only through DATA[3:0]. */ 0092 kFLEXSPI_8PAD = 0x03U, /*!< Transmit command/address and transmit/receive data only through DATA[7:0]. */ 0093 } flexspi_pad_t; 0094 0095 /*! @brief FLEXSPI interrupt status flags.*/ 0096 typedef enum _flexspi_flags 0097 { 0098 kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */ 0099 #if defined(FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN) && FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN 0100 kFLEXSPI_AhbBusErrorFlag = FLEXSPI_INTEN_AHBBUSERROREN_MASK, /*!< AHB Bus error flag. */ 0101 #else 0102 kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */ 0103 #endif 0104 kFLEXSPI_SckStoppedBecauseTxEmptyFlag = 0105 FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command 0106 sequence because Async TX FIFO empty. */ 0107 kFLEXSPI_SckStoppedBecauseRxFullFlag = 0108 FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK, /*!< SCK is stopped during command 0109 sequence because Async RX FIFO full. */ 0110 #if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) 0111 kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */ 0112 #endif 0113 kFLEXSPI_IpTxFifoWatermarkEmptyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */ 0114 kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */ 0115 kFLEXSPI_AhbCommandSequenceErrorFlag = 0116 FLEXSPI_INTEN_AHBCMDERREN_MASK, /*!< AHB triggered Command Sequences Error. */ 0117 kFLEXSPI_IpCommandSequenceErrorFlag = FLEXSPI_INTEN_IPCMDERREN_MASK, /*!< IP triggered Command Sequences Error. */ 0118 kFLEXSPI_AhbCommandGrantTimeoutFlag = 0119 FLEXSPI_INTEN_AHBCMDGEEN_MASK, /*!< AHB triggered Command Sequences Grant Timeout. */ 0120 kFLEXSPI_IpCommandGrantTimeoutFlag = 0121 FLEXSPI_INTEN_IPCMDGEEN_MASK, /*!< IP triggered Command Sequences Grant Timeout. */ 0122 kFLEXSPI_IpCommandExecutionDoneFlag = 0123 FLEXSPI_INTEN_IPCMDDONEEN_MASK, /*!< IP triggered Command Sequences Execution finished. */ 0124 kFLEXSPI_AllInterruptFlags = 0xFFFU, /*!< All flags. */ 0125 } flexspi_flags_t; 0126 0127 /*! @brief FLEXSPI sample clock source selection for Flash Reading.*/ 0128 typedef enum _flexspi_read_sample_clock 0129 { 0130 kFLEXSPI_ReadSampleClkLoopbackInternally = 0x0U, /*!< Dummy Read strobe generated by FlexSPI Controller 0131 and loopback internally. */ 0132 kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by FlexSPI Controller 0133 and loopback from DQS pad. */ 0134 kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */ 0135 kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */ 0136 } flexspi_read_sample_clock_t; 0137 0138 /*! @brief FLEXSPI interval unit for flash device select.*/ 0139 typedef enum _flexspi_cs_interval_cycle_unit 0140 { 0141 kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */ 0142 kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */ 0143 } flexspi_cs_interval_cycle_unit_t; 0144 0145 /*! @brief FLEXSPI AHB wait interval unit for writing.*/ 0146 typedef enum _flexspi_ahb_write_wait_unit 0147 { 0148 kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */ 0149 kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */ 0150 kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */ 0151 kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */ 0152 kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */ 0153 kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */ 0154 kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */ 0155 kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */ 0156 } flexspi_ahb_write_wait_unit_t; 0157 0158 /*! @brief Error Code when IP command Error detected.*/ 0159 typedef enum _flexspi_ip_error_code 0160 { 0161 kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */ 0162 kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */ 0163 kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ 0164 kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR 0165 used in DDR sequence. */ 0166 kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR 0167 used in SDR sequence. */ 0168 kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U, /*!< Flash access start address exceed the whole 0169 flash address range (A1/A2/B1/B2). */ 0170 kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */ 0171 kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */ 0172 } flexspi_ip_error_code_t; 0173 0174 /*! @brief Error Code when AHB command Error detected.*/ 0175 typedef enum _flexspi_ahb_error_code 0176 { 0177 kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */ 0178 kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U, /*!< AHB Write command with JMP_ON_CS instruction 0179 used in the sequence. */ 0180 kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ 0181 kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used 0182 in DDR sequence. */ 0183 kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR 0184 used in SDR sequence. */ 0185 kFLEXSPI_AhbCmdSequenceExecutionTimeout = 0x6U, /*!< Sequence execution timeout. */ 0186 } flexspi_ahb_error_code_t; 0187 0188 /*! @brief FLEXSPI operation port select.*/ 0189 typedef enum _flexspi_port 0190 { 0191 kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */ 0192 kFLEXSPI_PortA2, /*!< Access flash on A2 port. */ 0193 #if !((defined(FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) && (FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) 0194 kFLEXSPI_PortB1, /*!< Access flash on B1 port. */ 0195 kFLEXSPI_PortB2, /*!< Access flash on B2 port. */ 0196 #endif 0197 kFLEXSPI_PortCount 0198 } flexspi_port_t; 0199 0200 /*! @brief Trigger source of current command sequence granted by arbitrator.*/ 0201 typedef enum _flexspi_arb_command_source 0202 { 0203 kFLEXSPI_AhbReadCommand = 0x0U, 0204 kFLEXSPI_AhbWriteCommand = 0x1U, 0205 kFLEXSPI_IpCommand = 0x2U, 0206 kFLEXSPI_SuspendedCommand = 0x3U, 0207 } flexspi_arb_command_source_t; 0208 0209 /*! @brief Command type. */ 0210 typedef enum _flexspi_command_type 0211 { 0212 kFLEXSPI_Command, /*!< FlexSPI operation: Only command, both TX and Rx buffer are ignored. */ 0213 kFLEXSPI_Config, /*!< FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT. */ 0214 kFLEXSPI_Read, /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */ 0215 kFLEXSPI_Write, /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */ 0216 } flexspi_command_type_t; 0217 0218 typedef struct _flexspi_ahbBuffer_config 0219 { 0220 uint8_t priority; /*!< This priority for AHB Master Read which this AHB RX Buffer is assigned. */ 0221 uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */ 0222 uint16_t bufferSize; /*!< AHB buffer size in byte. */ 0223 bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows 0224 prefetch disable/enable separately for each master. */ 0225 } flexspi_ahbBuffer_config_t; 0226 0227 /*! @brief FLEXSPI configuration structure. */ 0228 typedef struct _flexspi_config 0229 { 0230 flexspi_read_sample_clock_t rxSampleClock; /*!< Sample Clock source selection for Flash Reading. */ 0231 bool enableSckFreeRunning; /*!< Enable/disable SCK output free-running. */ 0232 #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) 0233 bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins 0234 (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */ 0235 #endif 0236 bool enableDoze; /*!< Enable/disable doze mode support. */ 0237 bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half 0238 speed commands. */ 0239 #if defined(FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB) && FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB 0240 flexspi_read_sample_clock_t rxSampleClockPortB; /*!< Sample Clock source_b selection for Flash Reading. */ 0241 #endif 0242 #if defined(FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF) && FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF 0243 bool rxSampleClockDiff; /*!< Sample Clock source or source_b selection for Flash Reading. */ 0244 #endif 0245 #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) 0246 bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock 0247 output, when enable, Port B flash access is not available. */ 0248 #endif 0249 bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices 0250 when enabled, same configuration in FLASHA1CRx is applied to all. */ 0251 uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution, 0252 timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles. */ 0253 uint8_t ipGrantTimeoutCycle; /*!< Timeout wait cycle for IP command grant, timeout after 0254 ipGrantTimeoutCycle*1024 AHB clock cycles. */ 0255 uint8_t txWatermark; /*!< FLEXSPI IP transmit watermark value. */ 0256 uint8_t rxWatermark; /*!< FLEXSPI receive watermark value. */ 0257 struct 0258 { 0259 #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) 0260 bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */ 0261 #endif 0262 #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) 0263 bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */ 0264 #endif 0265 uint8_t ahbGrantTimeoutCycle; /*!< Timeout wait cycle for AHB command grant, 0266 timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles. */ 0267 uint16_t ahbBusTimeoutCycle; /*!< Timeout wait cycle for AHB read/write access, 0268 timeout after ahbBusTimeoutCycle*1024 AHB clock cycles. */ 0269 uint8_t resumeWaitCycle; /*!< Wait cycle for idle state before suspended command sequence 0270 resume, timeout after ahbBusTimeoutCycle AHB clock cycles. */ 0271 flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */ 0272 bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer 0273 when FLEXSPI returns STOP mode ACK. */ 0274 bool enableReadAddressOpt; /*!< Enable/disable remove AHB read burst start address alignment limitation. 0275 when enable, there is no AHB read burst start address alignment limitation. */ 0276 bool enableAHBPrefetch; /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI 0277 will fetch more data than current AHB burst. */ 0278 bool enableAHBBufferable; /*!< Enable/disable AHB bufferable write access support, when enabled, 0279 FLEXSPI return before waiting for command execution finished. */ 0280 bool enableAHBCachable; /*!< Enable AHB bus cachable read access support. */ 0281 } ahbConfig; 0282 } flexspi_config_t; 0283 0284 /*! @brief External device configuration items. */ 0285 typedef struct _flexspi_device_config 0286 { 0287 uint32_t flexspiRootClk; /*!< FLEXSPI serial root clock. */ 0288 bool isSck2Enabled; /*!< FLEXSPI use SCK2. */ 0289 uint32_t flashSize; /*!< Flash size in KByte. */ 0290 #if defined(FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT) && (FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT) 0291 bool addressShift; /*!< Address shift. */ 0292 #endif /* FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT */ 0293 flexspi_cs_interval_cycle_unit_t CSIntervalUnit; /*!< CS interval unit, 1 or 256 cycle. */ 0294 uint16_t CSInterval; /*!< CS line assert interval, multiply CS interval unit to 0295 get the CS line assert interval cycles. */ 0296 uint8_t CSHoldTime; /*!< CS line hold time. */ 0297 uint8_t CSSetupTime; /*!< CS line setup time. */ 0298 uint8_t dataValidTime; /*!< Data valid time for external device. */ 0299 uint8_t columnspace; /*!< Column space size. */ 0300 bool enableWordAddress; /*!< If enable word address.*/ 0301 uint8_t AWRSeqIndex; /*!< Sequence ID for AHB write command. */ 0302 uint8_t AWRSeqNumber; /*!< Sequence number for AHB write command. */ 0303 uint8_t ARDSeqIndex; /*!< Sequence ID for AHB read command. */ 0304 uint8_t ARDSeqNumber; /*!< Sequence number for AHB read command. */ 0305 flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit; /*!< AHB write wait unit. */ 0306 uint16_t AHBWriteWaitInterval; /*!< AHB write wait interval, multiply AHB write interval 0307 unit to get the AHB write wait cycles. */ 0308 bool enableWriteMask; /*!< Enable/Disable FLEXSPI drive DQS pin as write mask 0309 when writing to external device. */ 0310 #if defined(FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426) && (FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426) 0311 bool isFroClockSource; /*!< Is FRO clock source or not. */ 0312 #endif 0313 } flexspi_device_config_t; 0314 0315 /*! @brief Transfer structure for FLEXSPI. */ 0316 typedef struct _flexspi_transfer 0317 { 0318 uint32_t deviceAddress; /*!< Operation device address. */ 0319 flexspi_port_t port; /*!< Operation port. */ 0320 flexspi_command_type_t cmdType; /*!< Execution command type. */ 0321 uint8_t seqIndex; /*!< Sequence ID for command. */ 0322 uint8_t SeqNumber; /*!< Sequence number for command. */ 0323 uint32_t *data; /*!< Data buffer. */ 0324 size_t dataSize; /*!< Data size in bytes. */ 0325 } flexspi_transfer_t; 0326 0327 /* Forward declaration of the handle typedef. */ 0328 typedef struct _flexspi_handle flexspi_handle_t; 0329 0330 /*! @brief FLEXSPI transfer callback function. */ 0331 typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base, 0332 flexspi_handle_t *handle, 0333 status_t status, 0334 void *userData); 0335 0336 /*! @brief Transfer handle structure for FLEXSPI. */ 0337 struct _flexspi_handle 0338 { 0339 uint32_t state; /*!< Internal state for FLEXSPI transfer */ 0340 uint8_t *data; /*!< Data buffer. */ 0341 size_t dataSize; /*!< Remaining Data size in bytes. */ 0342 size_t transferTotalSize; /*!< Total Data size in bytes. */ 0343 flexspi_transfer_callback_t completionCallback; /*!< Callback for users while transfer finish or error occurred */ 0344 void *userData; /*!< FLEXSPI callback function parameter.*/ 0345 }; 0346 0347 /******************************************************************************* 0348 * API 0349 ******************************************************************************/ 0350 0351 #if defined(__cplusplus) 0352 extern "C" { 0353 #endif /*_cplusplus. */ 0354 0355 /*! 0356 * @name Initialization and deinitialization 0357 * @{ 0358 */ 0359 0360 /*! 0361 * @brief Get the instance number for FLEXSPI. 0362 * 0363 * @param base FLEXSPI base pointer. 0364 */ 0365 uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base); 0366 0367 /*! 0368 * @brief Check and clear IP command execution errors. 0369 * 0370 * @param base FLEXSPI base pointer. 0371 * @param status interrupt status. 0372 */ 0373 status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status); 0374 0375 /*! 0376 * @brief Initializes the FLEXSPI module and internal state. 0377 * 0378 * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the 0379 * input configure parameters. Users should call this function before any FLEXSPI operations. 0380 * 0381 * @param base FLEXSPI peripheral base address. 0382 * @param config FLEXSPI configure structure. 0383 */ 0384 void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config); 0385 0386 /*! 0387 * @brief Gets default settings for FLEXSPI. 0388 * 0389 * @param config FLEXSPI configuration structure. 0390 */ 0391 void FLEXSPI_GetDefaultConfig(flexspi_config_t *config); 0392 0393 /*! 0394 * @brief Deinitializes the FLEXSPI module. 0395 * 0396 * Clears the FLEXSPI state and FLEXSPI module registers. 0397 * @param base FLEXSPI peripheral base address. 0398 */ 0399 void FLEXSPI_Deinit(FLEXSPI_Type *base); 0400 0401 /*! 0402 * @brief Update FLEXSPI DLL value depending on currently flexspi root clock. 0403 * 0404 * @param base FLEXSPI peripheral base address. 0405 * @param config Flash configuration parameters. 0406 * @param port FLEXSPI Operation port. 0407 */ 0408 void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port); 0409 0410 /*! 0411 * @brief Configures the connected device parameter. 0412 * 0413 * This function configures the connected device relevant parameters, such as the size, command, and so on. 0414 * The flash configuration value cannot have a default value. The user needs to configure it according to the 0415 * connected device. 0416 * 0417 * @param base FLEXSPI peripheral base address. 0418 * @param config Flash configuration parameters. 0419 * @param port FLEXSPI Operation port. 0420 */ 0421 void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port); 0422 0423 /*! 0424 * @brief Software reset for the FLEXSPI logic. 0425 * 0426 * This function sets the software reset flags for both AHB and buffer domain and 0427 * resets both AHB buffer and also IP FIFOs. 0428 * 0429 * @param base FLEXSPI peripheral base address. 0430 */ 0431 static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base) 0432 { 0433 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; 0434 while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)) 0435 { 0436 } 0437 } 0438 0439 /*! 0440 * @brief Enables or disables the FLEXSPI module. 0441 * 0442 * @param base FLEXSPI peripheral base address. 0443 * @param enable True means enable FLEXSPI, false means disable. 0444 */ 0445 static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable) 0446 { 0447 if (enable) 0448 { 0449 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; 0450 } 0451 else 0452 { 0453 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; 0454 } 0455 } 0456 0457 /* @} */ 0458 0459 /*! 0460 * @name Interrupts 0461 * @{ 0462 */ 0463 /*! 0464 * @brief Enables the FLEXSPI interrupts. 0465 * 0466 * @param base FLEXSPI peripheral base address. 0467 * @param mask FLEXSPI interrupt source. 0468 */ 0469 static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask) 0470 { 0471 base->INTEN |= mask; 0472 } 0473 0474 /*! 0475 * @brief Disable the FLEXSPI interrupts. 0476 * 0477 * @param base FLEXSPI peripheral base address. 0478 * @param mask FLEXSPI interrupt source. 0479 */ 0480 static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask) 0481 { 0482 base->INTEN &= ~mask; 0483 } 0484 0485 /* @} */ 0486 0487 /*! @name DMA control */ 0488 /*@{*/ 0489 0490 /*! 0491 * @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests. 0492 * 0493 * @param base FLEXSPI peripheral base address. 0494 * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable. 0495 */ 0496 static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable) 0497 { 0498 if (enable) 0499 { 0500 base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK; 0501 } 0502 else 0503 { 0504 base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK; 0505 } 0506 } 0507 0508 /*! 0509 * @brief Enables or disables FLEXSPI IP Rx FIFO DMA requests. 0510 * 0511 * @param base FLEXSPI peripheral base address. 0512 * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable. 0513 */ 0514 static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable) 0515 { 0516 if (enable) 0517 { 0518 base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK; 0519 } 0520 else 0521 { 0522 base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK; 0523 } 0524 } 0525 0526 /*! 0527 * @brief Gets FLEXSPI IP tx fifo address for DMA transfer. 0528 * 0529 * @param base FLEXSPI peripheral base address. 0530 * @retval The tx fifo address. 0531 */ 0532 static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base) 0533 { 0534 return (uint32_t)&base->TFDR[0]; 0535 } 0536 0537 /*! 0538 * @brief Gets FLEXSPI IP rx fifo address for DMA transfer. 0539 * 0540 * @param base FLEXSPI peripheral base address. 0541 * @retval The rx fifo address. 0542 */ 0543 static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base) 0544 { 0545 return (uint32_t)&base->RFDR[0]; 0546 } 0547 0548 /*@}*/ 0549 0550 /*! @name FIFO control */ 0551 /*@{*/ 0552 0553 /*! @brief Clears the FLEXSPI IP FIFO logic. 0554 * 0555 * @param base FLEXSPI peripheral base address. 0556 * @param txFifo Pass true to reset TX FIFO. 0557 * @param rxFifo Pass true to reset RX FIFO. 0558 */ 0559 static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo) 0560 { 0561 if (txFifo) 0562 { 0563 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; 0564 } 0565 if (rxFifo) 0566 { 0567 base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; 0568 } 0569 } 0570 0571 /*! 0572 * @brief Gets the valid data entries in the FLEXSPI FIFOs. 0573 * 0574 * @param base FLEXSPI peripheral base address. 0575 * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. 0576 * Pass NULL if this value is not required. 0577 * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. 0578 * Pass NULL if this value is not required. 0579 */ 0580 static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount) 0581 { 0582 if (NULL != txCount) 0583 { 0584 *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U; 0585 } 0586 if (NULL != rxCount) 0587 { 0588 *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U; 0589 } 0590 } 0591 0592 /*@}*/ 0593 0594 /*! 0595 * @name Status 0596 * @{ 0597 */ 0598 /*! 0599 * @brief Get the FLEXSPI interrupt status flags. 0600 * 0601 * @param base FLEXSPI peripheral base address. 0602 * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status. 0603 */ 0604 static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base) 0605 { 0606 return base->INTR; 0607 } 0608 0609 /*! 0610 * @brief Get the FLEXSPI interrupt status flags. 0611 * 0612 * @param base FLEXSPI peripheral base address. 0613 * @param mask FLEXSPI interrupt source. 0614 */ 0615 static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask) 0616 { 0617 base->INTR |= mask; 0618 } 0619 0620 #if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) 0621 /*! @brief Gets the sampling clock phase selection after Data Learning. 0622 * 0623 * @param base FLEXSPI peripheral base address. 0624 * @param portAPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTA. 0625 * @param portBPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTB. 0626 */ 0627 static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *portAPhase, uint8_t *portBPhase) 0628 { 0629 if (portAPhase != NULL) 0630 { 0631 *portAPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT); 0632 } 0633 0634 #if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) 0635 if (portBPhase != NULL) 0636 { 0637 *portBPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT); 0638 } 0639 #endif 0640 } 0641 #endif 0642 0643 /*! @brief Gets the trigger source of current command sequence granted by arbitrator. 0644 * 0645 * @param base FLEXSPI peripheral base address. 0646 * @retval trigger source of current command sequence. 0647 */ 0648 static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base) 0649 { 0650 return (flexspi_arb_command_source_t)( 0651 (uint32_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT)); 0652 } 0653 0654 /*! @brief Gets the error code when IP command error detected. 0655 * 0656 * @param base FLEXSPI peripheral base address. 0657 * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. 0658 * @retval error code when IP command error detected. 0659 */ 0660 static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) 0661 { 0662 *index = (uint8_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT); 0663 return (flexspi_ip_error_code_t)( 0664 (uint32_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT)); 0665 } 0666 0667 /*! @brief Gets the error code when AHB command error detected. 0668 * 0669 * @param base FLEXSPI peripheral base address. 0670 * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. 0671 * @retval error code when AHB command error detected. 0672 */ 0673 static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) 0674 { 0675 *index = (uint8_t)(base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT; 0676 return (flexspi_ahb_error_code_t)( 0677 (uint32_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)); 0678 } 0679 0680 /*! @brief Returns whether the bus is idle. 0681 * 0682 * @param base FLEXSPI peripheral base address. 0683 * @retval true Bus is idle. 0684 * @retval false Bus is busy. 0685 */ 0686 static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base) 0687 { 0688 return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)); 0689 } 0690 /*@}*/ 0691 0692 /*! 0693 * @name Bus Operations 0694 * @{ 0695 */ 0696 0697 /*! @brief Update read sample clock source 0698 * 0699 * @param base FLEXSPI peripheral base address. 0700 * @param clockSource clockSource of type #flexspi_read_sample_clock_t 0701 */ 0702 void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource); 0703 0704 #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE) && FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE) 0705 /*! @brief Enables/disables the FLEXSPI IP command parallel mode. 0706 * 0707 * @param base FLEXSPI peripheral base address. 0708 * @param enable True means enable parallel mode, false means disable parallel mode. 0709 */ 0710 static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable) 0711 { 0712 if (enable) 0713 { 0714 base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK; 0715 } 0716 else 0717 { 0718 base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK; 0719 } 0720 } 0721 #endif 0722 0723 #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE) && FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE) 0724 /*! @brief Enables/disables the FLEXSPI AHB command parallel mode. 0725 * 0726 * @param base FLEXSPI peripheral base address. 0727 * @param enable True means enable parallel mode, false means disable parallel mode. 0728 */ 0729 static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable) 0730 { 0731 if (enable) 0732 { 0733 base->AHBCR |= FLEXSPI_AHBCR_APAREN_MASK; 0734 } 0735 else 0736 { 0737 base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK; 0738 } 0739 } 0740 #endif 0741 0742 /*! @brief Updates the LUT table. 0743 * 0744 * @param base FLEXSPI peripheral base address. 0745 * @param index From which index start to update. It could be any index of the LUT table, which 0746 * also allows user to update command content inside a command. Each command consists of up to 0747 * 8 instructions and occupy 4*32-bit memory. 0748 * @param cmd Command sequence array. 0749 * @param count Number of sequences. 0750 */ 0751 void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count); 0752 0753 /*! 0754 * @brief Writes data into FIFO. 0755 * 0756 * @param base FLEXSPI peripheral base address 0757 * @param data The data bytes to send 0758 * @param fifoIndex Destination fifo index. 0759 */ 0760 static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex) 0761 { 0762 base->TFDR[fifoIndex] = data; 0763 } 0764 0765 /*! 0766 * @brief Receives data from data FIFO. 0767 * 0768 * @param base FLEXSPI peripheral base address 0769 * @param fifoIndex Source fifo index. 0770 * @return The data in the FIFO. 0771 */ 0772 static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex) 0773 { 0774 return base->RFDR[fifoIndex]; 0775 } 0776 0777 /*! 0778 * @brief Sends a buffer of data bytes using blocking method. 0779 * @note This function blocks via polling until all bytes have been sent. 0780 * @param base FLEXSPI peripheral base address 0781 * @param buffer The data bytes to send 0782 * @param size The number of data bytes to send 0783 * @retval kStatus_Success write success without error 0784 * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout 0785 * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected 0786 * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected 0787 */ 0788 status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size); 0789 0790 /*! 0791 * @brief Receives a buffer of data bytes using a blocking method. 0792 * @note This function blocks via polling until all bytes have been sent. 0793 * @param base FLEXSPI peripheral base address 0794 * @param buffer The data bytes to send 0795 * @param size The number of data bytes to receive 0796 * @retval kStatus_Success read success without error 0797 * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout 0798 * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected 0799 * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected 0800 */ 0801 status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size); 0802 0803 /*! 0804 * @brief Execute command to transfer a buffer data bytes using a blocking method. 0805 * @param base FLEXSPI peripheral base address 0806 * @param xfer pointer to the transfer structure. 0807 * @retval kStatus_Success command transfer success without error 0808 * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout 0809 * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected 0810 * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected 0811 */ 0812 status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer); 0813 /*! @} */ 0814 0815 /*! 0816 * @name Transactional 0817 * @{ 0818 */ 0819 0820 /*! 0821 * @brief Initializes the FLEXSPI handle which is used in transactional functions. 0822 * 0823 * @param base FLEXSPI peripheral base address. 0824 * @param handle pointer to flexspi_handle_t structure to store the transfer state. 0825 * @param callback pointer to user callback function. 0826 * @param userData user parameter passed to the callback function. 0827 */ 0828 void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, 0829 flexspi_handle_t *handle, 0830 flexspi_transfer_callback_t callback, 0831 void *userData); 0832 0833 /*! 0834 * @brief Performs a interrupt non-blocking transfer on the FLEXSPI bus. 0835 * 0836 * @note Calling the API returns immediately after transfer initiates. The user needs 0837 * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether 0838 * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer 0839 * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark level, or 0840 * FLEXSPI could not read data properly. 0841 * 0842 * @param base FLEXSPI peripheral base address. 0843 * @param handle pointer to flexspi_handle_t structure which stores the transfer state. 0844 * @param xfer pointer to flexspi_transfer_t structure. 0845 * @retval kStatus_Success Successfully start the data transmission. 0846 * @retval kStatus_FLEXSPI_Busy Previous transmission still not finished. 0847 */ 0848 status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer); 0849 0850 /*! 0851 * @brief Gets the master transfer status during a interrupt non-blocking transfer. 0852 * 0853 * @param base FLEXSPI peripheral base address. 0854 * @param handle pointer to flexspi_handle_t structure which stores the transfer state. 0855 * @param count Number of bytes transferred so far by the non-blocking transaction. 0856 * @retval kStatus_InvalidArgument count is Invalid. 0857 * @retval kStatus_Success Successfully return the count. 0858 */ 0859 status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count); 0860 0861 /*! 0862 * @brief Aborts an interrupt non-blocking transfer early. 0863 * 0864 * @note This API can be called at any time when an interrupt non-blocking transfer initiates 0865 * to abort the transfer early. 0866 * 0867 * @param base FLEXSPI peripheral base address. 0868 * @param handle pointer to flexspi_handle_t structure which stores the transfer state 0869 */ 0870 void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle); 0871 0872 /*! 0873 * @brief Master interrupt handler. 0874 * 0875 * @param base FLEXSPI peripheral base address. 0876 * @param handle pointer to flexspi_handle_t structure. 0877 */ 0878 void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle); 0879 /*! @} */ 0880 0881 #if defined(__cplusplus) 0882 } 0883 #endif /*_cplusplus. */ 0884 /*@}*/ 0885 0886 #endif /* __FSL_FLEXSPI_H_ */
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