drivers/flexram/fsl_flexram.h

0001 /*
0002  * Copyright 2017-2022 NXP
0003  * All rights reserved.
0004  *
0005  *
0006  * SPDX-License-Identifier: BSD-3-Clause
0007  */
0008
0009 #ifndef _FSL_FLEXRAM_H_
0010 #define _FSL_FLEXRAM_H_
0011
0012 #include "fsl_common.h"
0013 #include "fsl_flexram_allocate.h"
0014
0015 /*!
0016  * @addtogroup flexram
0017  * @{
0018  */
0019
0020 /******************************************************************************
0021  * Definitions.
0022  *****************************************************************************/
0023
0024 /*! @name Driver version */
0025 /*@{*/
0026 /*! @brief Driver version. */
0027 #define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 0U))
0028 /*@}*/
0029
0030 /*! @brief Get ECC error detailed information. */
0031 #ifndef FLEXRAM_ECC_ERROR_DETAILED_INFO
0032 #define FLEXRAM_ECC_ERROR_DETAILED_INFO \
0033     0U /* Define to zero means get raw ECC error information, which needs parse it by user. */
0034 #endif
0035
0036 /*! @brief Flexram write/read selection. */
0037 enum
0038 {
0039     kFLEXRAM_Read  = 0U, /*!< read */
0040     kFLEXRAM_Write = 1U, /*!< write */
0041 };
0042
0043 /*! @brief Interrupt status flag mask */
0044 enum
0045 {
0046     kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< OCRAM accesses unallocated address */
0047     kFLEXRAM_DTCMAccessError  = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK,  /*!< DTCM accesses unallocated address */
0048     kFLEXRAM_ITCMAccessError  = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK,  /*!< ITCM accesses unallocated address */
0049
0050 #if defined(FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR) && FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR
0051     kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, /*!< OCRAM magic address match */
0052     kFLEXRAM_DTCMMagicAddrMatch  = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK,  /*!< DTCM magic address match */
0053     kFLEXRAM_ITCMMagicAddrMatch  = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK,  /*!< ITCM magic address match */
0054
0055 #if defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC
0056     kFLEXRAM_OCRAMECCMultiError  = FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK,
0057     kFLEXRAM_OCRAMECCSingleError = FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK,
0058     kFLEXRAM_ITCMECCMultiError   = FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK,
0059     kFLEXRAM_ITCMECCSingleError  = FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK,
0060     kFLEXRAM_D0TCMECCMultiError  = FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK,
0061     kFLEXRAM_D0TCMECCSingleError = FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK,
0062     kFLEXRAM_D1TCMECCMultiError  = FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK,
0063     kFLEXRAM_D1TCMECCSingleError = FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK,
0064
0065     kFLEXRAM_InterruptStatusAll =
0066         FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
0067         FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK |
0068         FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK |
0069         FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK |
0070         FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK |
0071         FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK |
0072         FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK,
0073 #else
0074     kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
0075                                   FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK |
0076                                   FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK,
0077 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
0078
0079 /*!< all the interrupt status mask */
0080 #else
0081     kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
0082                                   FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< all the interrupt status mask */
0083 #endif /* FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR */
0084
0085 };
0086
0087 /*! @brief FLEXRAM TCM access mode.
0088  * Fast access mode expected to be finished in 1-cycle;
0089  * Wait access mode expected to be finished in 2-cycle.
0090  * Wait access mode is a feature of the flexram and it should be used when
0091  * the CPU clock is too fast to finish TCM access in 1-cycle.
0092  * Normally, fast mode is the default mode, the efficiency of the TCM access will better.
0093  */
0094 typedef enum _flexram_tcm_access_mode
0095 {
0096     kFLEXRAM_TCMAccessFastMode = 0U, /*!< fast access mode */
0097     kFLEXRAM_TCMAccessWaitMode = 1U, /*!< wait access mode */
0098 } flexram_tcm_access_mode_t;
0099
0100 /*! @brief FLEXRAM TCM support size */
0101 enum
0102 {
0103     kFLEXRAM_TCMSize32KB  = 32 * 1024U,  /*!< TCM total size be 32KB */
0104     kFLEXRAM_TCMSize64KB  = 64 * 1024U,  /*!< TCM total size be 64KB */
0105     kFLEXRAM_TCMSize128KB = 128 * 1024U, /*!< TCM total size be 128KB */
0106     kFLEXRAM_TCMSize256KB = 256 * 1024U, /*!< TCM total size be 256KB */
0107     kFLEXRAM_TCMSize512KB = 512 * 1024U, /*!< TCM total size be 512KB */
0108 };
0109
0110 #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
0111 /*! @brief FLEXRAM memory type, such as OCRAM/ITCM/D0TCM/D1TCM */
0112 typedef enum _flexram_memory_type
0113 {
0114     kFLEXRAM_OCRAM = 0U, /*!< Memory type OCRAM */
0115     kFLEXRAM_ITCM  = 1U, /*!< Memory type ITCM */
0116     kFLEXRAM_D0TCM = 2U, /*!< Memory type D0TCM */
0117     kFLEXRAM_D1TCM = 3U, /*!< Memory type D1TCM */
0118 } flexram_memory_type_t;
0119
0120 /*! @brief FLEXRAM error type, such as single bit error position, multi-bit error position */
0121 typedef struct _flexram_ecc_error_type
0122 {
0123     uint8_t SingleBitPos;          /*!< Bit position of the bit to inject ECC Error. */
0124     uint8_t SecondBitPos;          /*!< Bit position of the second bit to inject multi-bit ECC Error */
0125     bool Fource1BitDataInversion;  /*!< Force One 1-Bit Data Inversion (single-bit ECC error) on memory write access */
0126     bool FourceOneNCDataInversion; /*!< Force One Non-correctable Data Inversion(multi-bit ECC error) on memory write
0127                                       access */
0128     bool FourceConti1BitDataInversion; /*!< Force Continuous 1-Bit Data Inversions (single-bit ECC error) on memory
0129                                           write access */
0130     bool FourceContiNCDataInversion;   /*!< Force Continuous Non-correctable Data Inversions (multi-bit ECC error) on
0131                                           memory write access */
0132 } flexram_ecc_error_type_t;
0133
0134 /*! @brief FLEXRAM ocram ecc single error information, including single error information, error address, error data */
0135 typedef struct _flexram_ocram_ecc_single_error_info
0136 {
0137 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0138     uint8_t OcramSingleErrorECCCipher;   /*!< OCRAM corresponding ECC cipher of OCRAM single-bit ECC error. */
0139     uint8_t OcramSingleErrorECCSyndrome; /*!< OCRAM corresponding ECC syndrome of OCRAM single-bit ECC error,
0140                                               which can be used to locate the Error bit using a look-up table. */
0141 #else
0142     uint32_t OcramSingleErrorInfo; /*!< Ocram single error information, user should parse it by themself. */
0143 #endif                                /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0144     uint32_t OcramSingleErrorAddr;    /*!< Ocram single error address */
0145     uint32_t OcramSingleErrorDataLSB; /*!< Ocram single error data LSB */
0146     uint32_t OcramSingleErrorDataMSB; /*!< Ocram single error data MSB */
0147 } flexram_ocram_ecc_single_error_info_t;
0148
0149 /*! @brief FLEXRAM ocram ecc multiple error information, including multiple error information, error address, error data
0150  */
0151 typedef struct _flexram_ocram_ecc_multi_error_info
0152 {
0153 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0154     uint8_t OcramMultiErrorECCCipher; /*!< OCRAM corresponding ECC cipher of OCRAM multi-bit ECC error. */
0155 #else
0156     uint32_t OcramMultiErrorInfo;  /*!< Ocram single error information, user should parse it by themself. */
0157 #endif                               /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0158     uint32_t OcramMultiErrorAddr;    /*!< Ocram multiple error address */
0159     uint32_t OcramMultiErrorDataLSB; /*!< Ocram multiple error data LSB */
0160     uint32_t OcramMultiErrorDataMSB; /*!< Ocram multiple error data MSB */
0161 } flexram_ocram_ecc_multi_error_info_t;
0162
0163 /*! @brief FLEXRAM itcm ecc single error information, including single error information, error address, error data */
0164 typedef struct _flexram_itcm_ecc_single_error_info
0165 {
0166 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0167     uint8_t ItcmSingleErrorTCMWriteRead;  /*!< itcm single-bit ECC error corresponding tcm_wr value, which is to tell
0168                                                whether it is a write access(0x01) or a read access(0x00). */
0169     uint8_t ItcmSingleErrorTCMAccessSize; /*!< itcm single-bit ECC error corresponding tcm access size,
0170                                                which should be 3 (64bit). */
0171     uint8_t ItcmSingleErrorTCMMaster;     /*!< itcm single-bit ECC error corresponding tcm_master,
0172                                                which is to tell the requester of the current access. */
0173     uint8_t ItcmSingleErrorTCMPrivilege;  /*!< itcm single-bit ECC error corresponding tcm_priv,
0174                                                which is to tell the privilege level of access. */
0175     uint8_t ItcmSingleErrorBitPostion;    /*!< itcm single-bit ECC error corresponding bit postion. */
0176 #else
0177     uint32_t ItcmSingleErrorInfo;  /*!< itcm single error information, user should parse it by themself. */
0178 #endif                               /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0179     uint32_t ItcmSingleErrorAddr;    /*!< itcm single error address */
0180     uint32_t ItcmSingleErrorDataLSB; /*!< itcm single error data LSB */
0181     uint32_t ItcmSingleErrorDataMSB; /*!< itcm single error data MSB */
0182 } flexram_itcm_ecc_single_error_info_t;
0183
0184 /*! @brief FLEXRAM itcm ecc multiple error information, including multiple error information, error address, error data
0185  */
0186 typedef struct _flexram_itcm_ecc_multi_error_info
0187 {
0188 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0189     uint8_t ItcmMultiErrorTCMWriteRead;  /*!< itcm multiple-bit ECC error corresponding tcm_wr value, which is to tell
0190                                               whether it is a write access(0x01) or a read access(0x00). */
0191     uint8_t ItcmMultiErrorTCMAccessSize; /*!< itcm multiple-bit ECC error corresponding tcm access size,
0192                                               which should be 3 (64bit). */
0193     uint8_t ItcmMultiErrorTCMMaster;     /*!< itcm multiple-bit ECC error corresponding tcm_master,
0194                                               which is to tell the requester of the current access. */
0195     uint8_t ItcmMultiErrorTCMPrivilege;  /*!< itcm multiple-bit ECC error corresponding tcm_priv,
0196                                               which is to tell the privilege level of access. */
0197     uint8_t ItcmMultiErrorECCSyndrome;   /*!< itcm multiple-bit ECC error corresponding syndrome,
0198                                               which can not be used to locate the Error bit using a look-up table. */
0199 #else
0200     uint32_t ItcmMultiErrorInfo;   /*!< itcm multiple error information, user should parse it by themself. */
0201 #endif                              /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0202     uint32_t ItcmMultiErrorAddr;    /*!< itcm multiple error address */
0203     uint32_t ItcmMultiErrorDataLSB; /*!< itcm multiple error data LSB */
0204     uint32_t ItcmMultiErrorDataMSB; /*!< itcm multiple error data MSB */
0205 } flexram_itcm_ecc_multi_error_info_t;
0206
0207 /*! @brief FLEXRAM dtcm ecc single error information, including single error information, error address, error data */
0208 typedef struct _flexram_dtcm_ecc_single_error_info
0209 {
0210 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0211     uint8_t DtcmSingleErrorTCMWriteRead;  /*!< dtcm single-bit ECC error corresponding tcm_wr value, which is to tell
0212                                                whether it is a write access(0x01) or a read access(0x00). */
0213     uint8_t DtcmSingleErrorTCMAccessSize; /*!< dtcm single-bit ECC error corresponding tcm access size,
0214                                                which should be 2 (32bit). */
0215     uint8_t DtcmSingleErrorTCMMaster;     /*!< dtcm single-bit ECC error corresponding tcm_master,
0216                                                which is to tell the requester of the current access. */
0217     uint8_t DtcmSingleErrorTCMPrivilege;  /*!< dtcm single-bit ECC error corresponding tcm_priv,
0218                                                which is to tell the privilege level of access. */
0219     uint8_t DtcmSingleErrorBitPostion;    /*!< dtcm single-bit ECC error corresponding bit postion. */
0220 #else
0221     uint32_t DtcmSingleErrorInfo;  /*!< dtcm single error information, user should parse it by themself. */
0222 #endif                            /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0223     uint32_t DtcmSingleErrorAddr; /*!< dtcm single error address */
0224     uint32_t DtcmSingleErrorData; /*!< dtcm single error data */
0225 } flexram_dtcm_ecc_single_error_info_t;
0226
0227 /*! @brief FLEXRAM dtcm ecc multiple error information, including multiple error information, error address, error data
0228  */
0229 typedef struct _flexram_dtcm_ecc_multi_error_info
0230 {
0231 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
0232     uint8_t DtcmMultiErrorTCMWriteRead;  /*!< dtcm multiple-bit ECC error corresponding tcm_wr value, which is to tell
0233                                               whether it is a write access(0x01) or a read access(0x00). */
0234     uint8_t DtcmMultiErrorTCMAccessSize; /*!< dtcm multiple-bit ECC error corresponding tcm access size,
0235                                               which should be 3 (64bit). */
0236     uint8_t DtcmMultiErrorTCMMaster;     /*!< dtcm multiple-bit ECC error corresponding tcm_master,
0237                                               which is to tell the requester of the current access. */
0238     uint8_t DtcmMultiErrorTCMPrivilege;  /*!< dtcm multiple-bit ECC error corresponding tcm_priv,
0239                                               which is to tell the privilege level of access. */
0240     uint8_t DtcmMultiErrorECCSyndrome;   /*!< dtcm multiple-bit ECC error corresponding syndrome,
0241                                               which can not be used to locate the Error bit using a look-up table. */
0242 #else
0243     uint32_t DtcmMultiErrorInfo;   /*!< dtcm multiple error information, user should parse it by themself. */
0244 #endif                           /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
0245     uint32_t DtcmMultiErrorAddr; /*!< dtcm multiple error address */
0246     uint32_t DtcmMultiErrorData; /*!< dtcm multiple error data */
0247 } flexram_dtcm_ecc_multi_error_info_t;
0248
0249 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
0250
0251 /*******************************************************************************
0252  * APIs
0253  ******************************************************************************/
0254
0255 #if defined(__cplusplus)
0256 extern "C" {
0257 #endif
0258
0259 /*!
0260  * @name Initialization and de-initialization
0261  * @{
0262  */
0263
0264 /*!
0265  * @brief FLEXRAM module initialization function.
0266  *
0267  * @param base FLEXRAM base address.
0268  */
0269 void FLEXRAM_Init(FLEXRAM_Type *base);
0270
0271 /*!
0272  * @brief De-initializes the FLEXRAM.
0273  *
0274  */
0275 void FLEXRAM_Deinit(FLEXRAM_Type *base);
0276
0277 /* @} */
0278
0279 /*!
0280  * @name Status
0281  * @{
0282  */
0283 /*!
0284  * @brief FLEXRAM module gets interrupt status.
0285  *
0286  * @param base FLEXRAM base address.
0287  */
0288 static inline uint32_t FLEXRAM_GetInterruptStatus(FLEXRAM_Type *base)
0289 {
0290     return base->INT_STATUS & (uint32_t)kFLEXRAM_InterruptStatusAll;
0291 }
0292
0293 /*!
0294  * @brief FLEXRAM module clears interrupt status.
0295  *
0296  * @param base FLEXRAM base address.
0297  * @param status Status to be cleared.
0298  */
0299 static inline void FLEXRAM_ClearInterruptStatus(FLEXRAM_Type *base, uint32_t status)
0300 {
0301     base->INT_STATUS |= status;
0302 }
0303
0304 /*!
0305  * @brief FLEXRAM module enables interrupt status.
0306  *
0307  * @param base FLEXRAM base address.
0308  * @param status Status to be enabled.
0309  */
0310 static inline void FLEXRAM_EnableInterruptStatus(FLEXRAM_Type *base, uint32_t status)
0311 {
0312     base->INT_STAT_EN |= status;
0313 }
0314
0315 /*!
0316  * @brief FLEXRAM module disable interrupt status.
0317  *
0318  * @param base FLEXRAM base address.
0319  * @param status Status to be disabled.
0320  */
0321 static inline void FLEXRAM_DisableInterruptStatus(FLEXRAM_Type *base, uint32_t status)
0322 {
0323     base->INT_STAT_EN &= ~status;
0324 }
0325
0326 /* @} */
0327
0328 /*!
0329  * @name Interrupts
0330  * @{
0331  */
0332
0333 /*!
0334  * @brief FLEXRAM module enables interrupt.
0335  *
0336  * @param base FLEXRAM base address.
0337  * @param status Status interrupt to be enabled.
0338  */
0339 static inline void FLEXRAM_EnableInterruptSignal(FLEXRAM_Type *base, uint32_t status)
0340 {
0341     base->INT_SIG_EN |= status;
0342 }
0343
0344 /*!
0345  * @brief FLEXRAM module disables interrupt.
0346  *
0347  * @param base FLEXRAM base address.
0348  * @param status Status interrupt to be disabled.
0349  */
0350 static inline void FLEXRAM_DisableInterruptSignal(FLEXRAM_Type *base, uint32_t status)
0351 {
0352     base->INT_SIG_EN &= ~status;
0353 }
0354 /* @} */
0355
0356 /*!
0357  * @brief FLEXRAM module sets TCM read access mode
0358  *
0359  * @param base  FLEXRAM base address.
0360  * @param mode  Access mode.
0361  */
0362 static inline void FLEXRAM_SetTCMReadAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)
0363 {
0364     base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK;
0365     base->TCM_CTRL |= (uint32_t)mode;
0366 }
0367
0368 /*!
0369  * @brief FLEXRAM module set TCM write access mode
0370  *
0371  * @param base  FLEXRAM base address.
0372  * @param mode  Access mode.
0373  */
0374 static inline void FLEXRAM_SetTCMWriteAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)
0375 {
0376     base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK;
0377     base->TCM_CTRL |= (uint32_t)mode;
0378 }
0379
0380 /*!
0381  * @brief FLEXRAM module force ram clock on
0382  *
0383  * @param base  FLEXRAM base address.
0384  * @param enable Enable or disable clock force on.
0385  */
0386 static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable)
0387 {
0388     if (enable)
0389     {
0390         base->TCM_CTRL |= FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK;
0391     }
0392     else
0393     {
0394         base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK;
0395     }
0396 }
0397
0398 #if defined(FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR) && FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR
0399 /*!
0400  * @brief FLEXRAM OCRAM magic addr configuration.
0401  * When read/write access hit magic address, it will generate interrupt.
0402  * @param base  FLEXRAM base address.
0403  * @param magicAddr Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].
0404  * @param rwSel Read/write selection. 0 for read access while 1 for write access.
0405  */
0406 static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
0407 {
0408     base->OCRAM_MAGIC_ADDR = FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(rwSel) |
0409                              FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR((uint32_t)magicAddr >> 3);
0410 }
0411
0412 /*!
0413  * @brief FLEXRAM DTCM magic addr configuration.
0414  * When read/write access hits magic address, it will generate interrupt.
0415  * @param base  FLEXRAM base address.
0416  * @param magicAddr Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].
0417  * @param rwSel Read/write selection. 0 for read access while 1 write access.
0418  */
0419 static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
0420 {
0421     base->DTCM_MAGIC_ADDR = FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(rwSel) |
0422                             FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR((uint32_t)magicAddr >> 3);
0423 }
0424
0425 /*!
0426  * @brief FLEXRAM ITCM magic addr configuration.
0427  * When read/write access hits magic address, it will generate interrupt.
0428  * @param base  FLEXRAM base address.
0429  * @param magicAddr Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].
0430  * @param rwSel Read/write selection. 0 for read access while 1 for write access.
0431  */
0432 static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
0433 {
0434     base->ITCM_MAGIC_ADDR = FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(rwSel) |
0435                             FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR((uint32_t)magicAddr >> 3);
0436 }
0437 #endif /* FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR */
0438
0439 #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
0440 /*!
0441  * @brief FLEXRAM get ocram ecc single error information.
0442  * @param base  FLEXRAM base address.
0443  * @param OcramECCEnable ocram ecc enablement.
0444  * @param TcmECCEnable tcm(itcm/d0tcm/d1tcm) ecc enablement.
0445  */
0446 void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable);
0447
0448 /*!
0449  * @brief FLEXRAM ECC error injection.
0450  * @param base  FLEXRAM base address.
0451  * @param memory memory type, such as OCRAM/ITCM/DTCM.
0452  * @param error ECC error type.
0453  */
0454 void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error);
0455
0456 /*!
0457  * @brief FLEXRAM get ocram ecc single error information.
0458  * @param base  FLEXRAM base address.
0459  * @param info ecc error information.
0460  */
0461 void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info);
0462
0463 /*!
0464  * @brief FLEXRAM get ocram ecc multiple error information.
0465  * @param base  FLEXRAM base address.
0466  * @param info ecc error information.
0467  */
0468 void FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_multi_error_info_t *info);
0469
0470 /*!
0471  * @brief FLEXRAM get itcm ecc single error information.
0472  * @param base  FLEXRAM base address.
0473  * @param info ecc error information.
0474  */
0475 void FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_single_error_info_t *info);
0476
0477 /*!
0478  * @brief FLEXRAM get itcm ecc multiple error information.
0479  * @param base  FLEXRAM base address.
0480  * @param info ecc error information.
0481  */
0482 void FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_multi_error_info_t *info);
0483
0484 /*!
0485  * @brief FLEXRAM get d0tcm ecc single error information.
0486  * @param base  FLEXRAM base address.
0487  * @param info ecc error information.
0488  * @param bank DTCM bank, 0 is D0TCM, 1 is D1TCM.
0489  */
0490 void FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_single_error_info_t *info, uint8_t bank);
0491
0492 /*!
0493  * @brief FLEXRAM get d0tcm ecc multiple error information.
0494  * @param base  FLEXRAM base address.
0495  * @param info ecc error information.
0496  * @param bank DTCM bank, 0 is D0TCM, 1 is D1TCM.
0497  */
0498 void FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_multi_error_info_t *info, uint8_t bank);
0499
0500 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
0501
0502 #if defined(__cplusplus)
0503 }
0504 #endif
0505
0506 /*! @}*/
0507
0508 #endif